DE2312954B2 - Traffic signal control device for a number of traffic signal stations - Google Patents

Description

The invention relates to a traffic signal control device for a number of traffic signal stations, whose Display phases are controllable by phase control signals, with a control signal generating computer and an auxiliary control device which can be synchronized with this and has an auxiliary control device by means of the operating state the computer representing control signal switchable phase control means for generating the phase control signals from the control signals i * nd when the computer is operating properly Failure of the computer due to an auxiliary control signal from the auxiliary control device, which has a frequency adjustable Pulse generator and for each traffic signal laiion one of its clock pulses, the control signals and the Has control signal processing selection circuit with a counter circuit.

From US-PS 33 63 185 is such a traffic signal control device known comprising a computer, an auxiliary control device and several traffic signal stations having, wherein the auxiliary control device and the computer are synchronized so that at If the computer fails, the display phases of the traffic signal stations are seamless, i.e. without incorrect switching, independent of the auxiliary control device are controllable.

In this known traffic signal control device however, both in the computer and, if it fails, in the auxiliary control device, several Control or auxiliary control signals, e.g. B. cycle, start, Equalization and division signals, generated simultaneously and / or synchronously, and to the traffic signal stations

ίο be transferred. To reduce the transmission lines are in this known traffic signal control device, the start and each transmit corresponding cycle pulses on the same line, but this solution requires one

great technical effort to encode these signals in the computer and in the auxiliary control device as well as when decoding these signals in the auxiliary control device and in the traffic signal stations. In contrast, it is the object of the invention to provide a To provide traffic signal control device of the known type which avoids these disadvantages and a synchronization of the computer with the auxiliary control device both at the beginning and at the end of a failure period of the computer.

The object is achieved according to the invention by that the selection circuit memory for storing the duration of the display phases, a comparator circuit for generating a coincidence signal generating the auxiliary control signal when the Memory content with the counter content and a gate circuit for suppressing the coincidence signal Has concern of the control signal.

The advantages of the traffic signal control device according to the invention can be seen in particular in the fact that the phase control device having the auxiliary control device only a control signal and for each independent traffic signaling system has to be supplied with a control signal from the computer. The production of the single phase control signal for each traffic signal station takes place either directly from the corresponding control signal of the computer or, in the event of its failure, from the successively switched through Storage and comparison of their contents with the contents of what is advanced by the clock pulse Counter. Even if the computer is working properly, the reversing device will use the Coincidence signal is generated, which thereby remains synchronized with the computer. If the computer fails the suppressed coincidence signal is enabled, from which the phase control signal is then generated in the correct phase will.

In a further development of the traffic signal control device according to the invention, the synchronization achieved between the computer and the auxiliary control device in an advantageous manner in that the Selection circuit a selection circuit for resetting the counter circuit with the control signal or the Auxiliary control signal and a gate circuit to suppress the clock pulses when a control signal is present, until the control signal is generated.

With advantageous developments of the invention The traffic signal control device can set the values for the duration of the various display phases can be set in the memories either manually or by the computer. This allows for example different traffic control patterns for different traffic volumes to different ones Times of day are prefixed.

The invention is described below using an exemplary embodiment explained in more detail with reference to the drawing. It shows

F i g. 1 is a block diagram of a traffic signal control device according to the invention;

F i g. FIG. 2 is a detailed block diagram of the process shown in FIG. 1 illustrated phase control device,

F i g. 3 is a timing diagram showing the synchronization between the computer and the auxiliary control device shows,

4 shows a timing diagram of signals before and after computer failure and

F i g. Figure 5 is a timing diagram of the phase control signals for neighboring traffic signal stations.

In Fig. 1, block 100 symbolizes a computer and block 200 symbolizes a failure monitoring device. The phase advance signal SC generated by the computer 100 is fed to a corresponding input contact point of the gate circuits 300, 301, 302. A signal S1 is fed to the corresponding other input contact point of the gate circuits 300, 301, 302. The phase lead signal SC, which has been fed to the input contact points of the gate circuits 300,301,302, appears at the output contact points of the same in accordance with the presence of the signal S1. The output signals of the gate circuits 300, 301, 302 are fed to OR gates 400, 401, 402. The signal S1 occurs when the computer 100 is working normally, and does not appear when the computer 100 is malfunctioning.

The phase lead signal SF generated by the failure monitoring device 200 is fed to the corresponding input contact point of the AND gates 500, 501, 502. The signal S1 is fed to the corresponding other input contact point of the AND gates 500, 501, 502. The signal SF generated by the failure monitoring device 200 occurs at the output contact points of the AND gates 500, 501, 502 when the signal S1 is not present. The output signals of the gate circuits 500, 501, 502 are fed to the corresponding other input contact point of the OR gates 400, 401, 402.

The output signals of the OR Torc 400, 401, 402 become corresponding traffic lines or traffic signals 600, 601, 602 carried over transmission lines 700,701,702.

Accordingly, the displays of the traffic signs are controlled in accordance with the phase advance signal SC generated by the computer 100 when the computer 100 is operating normally, and are switched in accordance with the phase advance signal SF generated by the fail-safe device 200 when the computer 100 fails.

In the in F i g. In the embodiment shown in FIG. 1, the filling monitoring device 200 is connected to the computer 100 via a control line CL and a multiple line BL . If the computer 100 is operating normally, the control parameters calculated by the computer 100 are fed to the failure monitoring device 200.

F i g. 2 shows the failure monitoring device 200. In the failure monitoring device 200, registers 1, 2, 3, 4, 5, 6 are provided for setting the corresponding phase time of the traffic signals. The data to be stored in registers 1, 2, 3, 4, 5, 6 are sent from computer 100 via a first multipath line BLX. The in F i g. 1 ComDuter 100 shown is connected to the corresponding one

The output contact point of the AND gates 21, 22, 23, 24, 25, 26 is connected via a multiple line BLl and is also connected to the corresponding other input contact point of the AND gates 21 to 26 via a first control line CLl. The output contact points of AND gates 21 to 26 are connected to the input contact points of registers 1 to 6, respectively. The data signals from the computer 100 are routed via the multipath line BLl and appear at the output contact points of the AND gates 21 to 26 when a signal is routed to the corresponding one input contact point of the same from the computer 100 via the control line CLl. The output contact points of AND gates 21 to 26 are connected to correspond to the input contact points of registers 1, 2, 3, 4, 5, 6. Therefore, corresponding values of the phase times calculated by the computer 100 are stored in the registers 1, 2, 3, 4, 5, 6 every time unit, for example five minutes. In the present embodiment, the value of the time of the first phase is stored in the register 1, the value of the time of the second phase is stored in the register 2, and the value of the time of the sixth phase is stored in the register 6 in sequence.

A counter 7 is provided for counting the corresponding phase time. The counter 7 counts in accordance with clock pulses generated by a clock pulse generator 8, and is reset every time a counter 9 advances. The clock pulses generated by the generator 8 are fed to the input contact point of a frequency divider 10. A decoder 11 is provided for controlling the divider 10, and the divider 10 generates pulse signals at its output contact point by dividing the frequency of the clock pulses by the value given by the decoder 11. The decoder 11 is controlled by the computer 100 via a trunk line BL2 . The pulse signals appearing at the output contact point of the divider 10 are called "percentage pulses". The output contact point of the divider 10 is connected to the two input contact points of the gate circuits 12 and 13. The two output contact points of the gate circuits 12 and 13 are connected to the input contact point of the OR gate 14, and the output contact point of the OR gate 14 is connected to the input contact point of the counter 7.

The signal SI is fed to the other contact points of the gate circuits 12, 13. The adjustment output contact point a bistable flip-flop 15 is with the remaining input contact point of the gate circuit 13 connected.

Accordingly, the counter 7 increments in accordance with the percentage pulses, the flip-flop 15 being set when the computer 100 is operating normally. The operation continues of the computer 100, then the counter 7 switches in accordance with the percentage pulses without Consideration of the state of the bistable flip-flop 15 continues.

The bistable multivibrator 15 ′ is set by the signal SC transmitted from the computer 100. The signal SC is also applied to the input contact point of the OR circuit 16. The output contact point of the OR gate 16 is connected to the reset contact point of the counter 7 and also to the counter 9. The output contact point of the counter 9 is connected to the corresponding one input contact

point of the AND members 31,32,33,34,35,36. The corresponding other input contact point of the AND gates 31, 32, 33, 34, 35, 36 is with the corresponding Output contact points of registers 1 to 6 connected. Those stored in registers 1 to 6 Data signals appear at the output contact points of AND gates 31 to 36 in accordance with the supply of the output signal from the counter 9 to the corresponding one input contact point of the AND gates 31 to 36. The output contact points of the AND gates 31 to 36 are connected to the input contact point a coincidence circuit 17 is connected. The output contact point of the counter 7 is connected to the other input contact point of the coincidence counter 17. It occurs at the output contact point of the coincidence counter 17 a signal coincident with the count value of the counter 7 with the data signal of AND gates 31 to 36. The output contact point of the coincidence circuit 17 is with the Input contact point of a gate circuit 500 and also with the reset input contact point of the bistable Flipper 15 connected.

The counter 9 is incremented in accordance with the output signal of the OR gate 16, and the output signal of the counter 9 opens a corresponding one of the AND gates 31 in each stage to 36 consecutive. The time value stored in each register 1 to 6 becomes the coincidence circuit 17 supplied in accordance with the corresponding output signal of the counter 9 through the AND gates 31 to 36. Every time the counter 7 counts the time stored in one of the registers 1 to 6 a signal appears at the contact point of the coincidence circuit 17. The signal occurs this way every time when one of the time values stored in registers 1 to 6 has elapsed.

In the embodiment, the times of each phase calculated by the computer are entered in the registers 1 to 6, and the times of each phase are sequentially counted in the computer 100. The computer 100 generates the signal SC when it counts the time of the corresponding phase. Since the counter 7 is reset by the signal SC , the signal appears at the output contact point of the coincidence circuit 17 simultaneously with the signal SC generated by the computer 100

As shown in FIG. 3 (A), if for some reason the signal SC is generated by the computer 100 during phase (n) at time ii prior to time / 2 when the signal from the coincidence circuit 17 occurs, the counter 7 becomes deleted at time ii and at the same time the counter 9 is incremented. In the next phase (n + 1) the phase preparation signal! SC from the computer 100 and the output of the coincidence circuit 17 at the same time O generates step on the other hand in the in FIG. 3 (B), the output of the coincidence circuit 17 at a time / 1 before the time tz at which the signal SC is generated by the computer 100, then the bistable multivibrator 15 is reset at time ft, whereby the percentage pulses are not more can be led to the counter 7. The counter 7 is later reset and, at the same time, the bistable multivibrator 15 is set by the signal SC generated by the computer 100 at time ft. Accordingly, in the next phase (77 -I- 1), both the phase advance signal SC by the computer 100 and the output signal of the coincidence circuit 17 appear at the same time n.

As described above, during normal operation of the computer 100, the counter 9 is incremented by the lead signal SC , and the count of the time of the timer 7 and the count of the time of the computer 100 occur simultaneously, and accordingly it is understood that the time , in which the signal SC is generated by the computer 100 and the time when the output signal of the coincidence circuit 17 occurs are coincident in each phase. Since the phase of the counter 9 provided in the failure monitor 200 is the same as that of the traffic signal, and the value of the time count of the counter 9 at this phase is the same as that of the computer 100, even if the computer 100 is in the mode shown in FIG. 4 fails, the control of the traffic signals 600, 601, 602 can be switched from the control by the computer 100 to the control by the fail-safe device without any difficulty.

In the above, the description has been made in connection with the traffic signal at an intersection. The signal SC from the computer 100 can, however, as it is clear to the person skilled in the art, be transmitted to traffic signals of neighboring intersections with a lead-in OFV matching the traffic flow. The mutual relationship between the phase advance signals transmitted to such adjacent intersections is shown in FIG. 5 shown. After the phase advance signal SCO to the one shown in FIG. 1 has been transmitted, the phase lead signal 5Cl is transmitted to the adjacent traffic signal 501 with a compensation value OFV1 in this phase. In the same way, after the phase lead signal SCl 711 has been transmitted to the traffic signal iiOl, the phase lead signal SC2 is transmitted to the adjacent traffic signal 502 with a compensation value OFVl in this phase. In this way the traffic signals are systematically controlled.

Since the relationship between the phase advance signals generated by the computer 1100 and those that can be generated by the failure monitoring device 200 of the type described above, the systematic control of neighboring traffic signals can be realized immediately if the computer 100 fails.

A third multipath B13 is also provided for adjusting the phase of the counter 9 at a desired time in coincidence with the phase of the traffic signals determined by the computer 100.

In the embodiment described above, the setting of the signal data in registers 1 to 6 is carried out executed by computer 100; But it can also be the case that the setting of the signals of the data in the Registers 1 to 6 done manually. The data values to be set in registers 1 to 6 are not necessary be in coincidence with the phase times calculated by the computer 100. The only condition that must be satisfied is that the sum of the data to be set in registers 1 to 6 is the same with respect to the corresponding intersections to be controlled systematically.

For this purpose 2 sheets of drawings

Claims (4)

Patent claims: 1. Traffic signal control device for a number of traffic signal stations, the display phases of which can be controlled by phase control signals, with a computer generating control signals and a phase control device that can be synchronized with this, has an auxiliary control device and can be switched by a control signal representing the operating state of the computer in order to generate the phase control signals during normal operation of the computer from the control signals and, if the computer fails, by an auxiliary control signal of the auxiliary control device, the • inen frequency-adjustable pulse generator and for each traffic signal station has a respective selection circuit with a counter circuit that processes the control signals and the control signal, characterized in that the selection circuit Speichti ( R) generating for storing the duration of the display periods, a comparator (17) for generating an auxiliary control signal (SF) Koindizenzsignals (5 2) if the memory content matches the counter content and a gate circuit (500) for suppressing the coin license signal (52) when the control signal (5t) is applied. 2. Traffic signal control device according to claim 1, characterized in that the selection circuit has a selection circuit (16) for resetting the counter circuit (7) with the control signal (SC) or the auxiliary control signal (SF) and a gate circuit (12, 13, 14, 15) for Suppression of the Taki pulses when the control signal (51) is present until the control signal (SC) is generated. having. 3. Traffic signal control device according to claim 1 or 2, characterized in that the memory (R) d \ irc \\ the computer are adjustable. 4. Traffic signal control device according to claim 1 or 2, characterized in that the memory (R) \ on hand are adjustable.