DE2265333A1 - METHOD AND DEVICE FOR EVALUATING A DIGITAL SIGNAL - Google Patents

Description

DIPL. ING KLAUS BEHN DIPL. PHYS. ROBERT MÜNZHUBER

PATENT LAWYERS

WIDENMAYERSTRASSE 6 D - ΘΟΟΟ MUNICH TEL (089) 22 25 30 - 29 51 92

February 28, 1977 A 4677 Mü / ib

MARTIN MARIETTA CORPORATION, 1800 K Street, NW, Was hi ngton, DC 20606, USA

Method and device for evaluating a digital signal

Removal from patent ... (patent application P 22 51 557.7-3-4)

nachtrag'ioh alleviated

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Telegram address: patent senior

The invention relates to a method and a device for evaluating a digital signal that has a predetermined bit rate is transmitted during successive time periods. The scope of the method and the device according to The invention is generally the transmission and control of data, but it has been shown that the Invention is particularly useful for subscriber call systems, and the invention will therefore also be used hereinafter for better explanation described using such a system.

The known paging systems generally include the selective transmission of subscriber identification signals via electromagnetic signals Waves from a large number of transmitters distributed over the call area via visual lines

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nlen frequencies. Each of the participants is customary equipped with a portable receiver, which receives and decrypts the relevant subscriber identification signal emits an audible signal.

All of these known systems suffer from an interference problem because of the property of line-of-sight propagation of these electromagnetic waves the use of a multitude of distributed over the call area Transmitter required in order to achieve complete coverage of the area in question and because all of these portable receivers must be tuned to the same carrier frequency in order to cover the entire call area to ensure reception. These known call systems are therefore with the undesirable alternatives of Boundary areas between neighboring transformers, within which the participant cannot be reached, and with Interferences as a result of the overlap of the propagation tracks of neighboring transmitters.

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In the known multiple transmission systems of the type mentioned above, analog control is generally used necessary. However, the use of analog control is difficult due to the changing Environmental conditions. In addition, the use of analog control requires a considerable amount additional energy in each receiver and with the excess of data to be evaluated, for example when from Recipients from all transmitters are visible.

In the case of the invention, digital technology is therefore intended to be used, through which the physical quantity and decreases the weight of the portable receivers and increases the lifetime of the receivers' power sources can be.

Furthermore, a new method and a new device should be created with the invention, 'with

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whose help it is possible to reduce energy consumption and to decrease the physical size and weight of the energy sources for the recipients.

According to the invention, these objectives are essentially achieved in that the transmitters operate in sequence operated and the receivers synchronized. As the recipient in the absence of a data transmission do not work, the possibility of decoding noise signals is essentially eliminated. Furthermore reduces the choice of transmitter made by the receiver as a function of the characteristics of the received one Signal considerably the possibility of decoding noise data from other, weak transmitters or a nearby transmitter that is noisy or sending out other unwanted signals.

Furthermore, the invention should reduce the occurrence of decoding errors, and there should be a new method

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drive and create a new device that receives a data signal only during time intervals, which are selected as a puncture of the reception characteristic of the received signal.

The digital technology for the transmission of data signals is particularly advantageous in that a extremely large numbers of data can be transmitted from one point to another in short time intervals, and with a minimum of outlay in terms of equipment, such as extremely precise frequency generators and frequency mixers as well as high quality decoders. For example, a digital word containing ten binary bits display over 1,000 different messages.

Of course, when using digital technology, the loss of a binary bit in a certain Signal lead to an incorrect evaluation of the signal. With the previously known digital data transmission, where a multitude of address or data signals are transmitted and by counting or comparing the bits be decoded, for example with an AND gate, for example the loss of a single pulse as a result interference or other transmission difficulty lead to incorrect information at the receiving end of the system.

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Since the method and the device according to the invention are particularly suitable for subscriber paging systems and are also described on the basis of such systems, it is a further aim of the invention to overcome the disadvantages of the known paging systems
and to provide a new paging method and device.

Furthermore, a new method and a new call system are to be created in which the received energy is determined by the selection of a time segment from a plurality of time segments
is stored within a specified call data frame for the subscriber address evaluation.

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Further features, details and advantages of the invention emerge from the following description of a Embodiment and based on the drawing. On the drawing show:

Fig. 1 To explain the general function
Block diagram of a basic embodiment of the system according to the invention in FIG
Application to a call system;

Fig. 2 is a timing diagram showing the code format;

Figure 3 is a functional block diagram of one of the portable Receiver of Fig. Ij

Figure 4 is a functional block diagram of the timing recovery circuit of Fig. 5J

Figure 5 is a more detailed functional block diagram of the synchronizing and decoding logical circle of Fig. 3i

FIG. 6 is a more detailed functional block diagram of the synchronization detector of FIG
Fig. 5;

Figure 7 is a more detailed functional block diagram of the up / down counter of Fig. 5J

Figure 8 is a more detailed functional block diagram the matrix address generator of Fig. 5;

Figure 9 is a more detailed functional block diagram of the address matrix of Figure 5;

Fig. 10 is a more detailed functional block diagram of the address interpreter of Fig. 5J

Figure 11 is a more detailed functional block diagram of the address receiving circuit of Fig. 5J

Figure 12 is a more detailed functional block diagram of the call indicator of Figure 5J

Figure 15 is a more detailed functional block diagram the timing signal generator of Fig. 5; and

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Figure 14 is a more detailed functional block diagram of the on / off logic circuit of FIG. 5 provided in the receiver.

The following description of the preferred embodiment of the invention embodied as a paging system is structured as follows to make it easier to understand:

Description of the basic system (Fig. 1)

II data format (Fig. 2)

III receiver (Fig. 3 to 14)

A time recovery circuit (Fig. 4)

B Synchronizing and decoding logic circuit (Fig. 5)

1. Synchronous detector (Fig. 6)

2. Up / down counter (Fig. 7)

3. Matrix address generator (Fig. 8)

4. Address matrix (Fig. 9)

5. Address evaluator (Fig. 10)

6. Address recording (Fig. 11)

7. Call indicator (Fig. 12)

8. Time signal generator (Fig. 13)

9.Logical on / off circuit of the receiver (Fig. 14)

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Basic system:

In Fig. 1 a basic call system according to the invention is shown. The central station 50 can if the capacity of the system requires it to include a general purpose digital computer, not shown. The central station 50 may be reachable through any suitable switching system, such as the illustrated general telephone network 52, to be able to use the existing telephone lines and switches of telephone system 52 to receive subscriber identification signals. In answer of the received subscriber identification signal, the central station 50 generates call signals for transmission to one or more a plurality of transmitters 54 distributed over the paging area are.

The transmitted by at least one of the transmitters 5 ^ Call signals are picked up by portable receivers 56, the be carried by the individual participants. The receipt of the address signal assigned to a particular participant through its portable receiver 56 gives the subscriber a Indicates that a call has been received. The subscriber can then identify the purpose of the call by looking up a phone and dialing a particular number to receive a message or directly dialing the person originating the call (if the participant knows this information).

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II. Data format:

That in the preferred embodiment of the paging system The data format used is shown in FIG. As previously described with reference to FIG. 1, the causes person dialing a subscriber identification signal for transmission to the central station 50 via the telephone system 52. This Subscriber identification signals are converted into binary form and stored in the central station 50 in queue for a subsequent decoding and combination with synchronization signals for the purpose of forming a ringing signal that for example a 30 subscriber address message word contains for repetitive transmission in a predetermined number of time periods during a main data frame. The repetition of the same message word is of course in the case of a single transmission system not required, but can be done on request.

In the example of FIG. 2, as can be seen, each main frame 58 contains 8 time segments 60 of one second each, which are designated by T ₁ - T 1 -. The identical one

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Message word 62 may be sent from a different transmitter during each of the 8 time slots of a particular main frame can be transmitted or by a group of transmitters, as will be described in detail later the number of transmitters 54 of FIG. 1 is at least equal to that The number of time slots that are accommodated in the main frame and a particular one of the transmitters 54 can be Message word 62 is transmitted in the main frame 58 during one or more time segments 60. The number of periods 60 can of course exceed the number of transmitters in the system where an increase in the call area it's planned. ·

According to FIG. 2, each message word 62 represents a series pulse train represent, preferably starting with a group of 12 binary bits, for example 12 binary ZERO-Büs, which at 64 are indicated, followed by synchronization recording signals 66 and these in turn followed by 30 different addresses or address words A1 to A30 which are mutually separated by identical synchronization hold signals 68 from FIG. 4, respectively binary bits are separated. The sync hold signal 66 preferably contains 4 identical 4-bit patterns that are carried out by a binary 32-bit signal are separated from each other, for example the binary 32-ZEROS signal in the representation of Fig. 3. The four identical 4-bit synchronization patterns

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(denoted by SA) are coded according to a predetermined binary code, for example 1101, as in the drawing shown. Thus, the sync hold signal can be represented as SA, Os, SA, Os, SA, Ös, SA, where SA determines the selected 4-bit code and ds the ^ 2 binary ZERO signals.

Each of the address words A1-A30 preferably contains a J> \ bit Bose-Chaudhuri coded address definition and a parity bit. Adjacent address words of the J> 0 address words A1-A ^ O. Are separated from one another by the synchronization hold signal 68 (denoted by SB), which is preferably a series-coded 4-bit signal which differs from the synchronization code SA. Each of the message words 62 transmitted during one of the time segments T. - T ^ contains 1,200 binary bits.

The originally 12 binary ZERO bits, which are labeled 64 in FIG. 2, are basically not required but can be used to help with the bit synchronization of the receivers, as will be described in detail later. These 12 binary ZERO bits provide a certain period of time between switching on a transmitter and the transmission of the synchronization hold signal 66, this time period

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can be useful. Of course, the original 12 binary bits need not all be binary ZERO bits, but can represent any predetermined code. A simplification of the logic is possible, however, by using ZERO bits in the described embodiment, and the use of these ZERO bits may be desirable if, for example, the communication link between the central station 50 and the transmitters ^ of FIG. 1 encompasses all directions Transmission of electromagnetic energy at radio frequencies is.

The synchronization hold signals of FIG. 2 can be used at the transmission by the transmitter 5 ^ of Fig. 1 of the individual paging receivers 56 are used to determine the bit error rate of the call signal to be determined before the decryption of the subsequent address words, as described in detail below will be. The 4-bit synchronization hold signal SB can only be assigned to the call system that works in a certain call area and can be used to both to aid in determining the bit error rate and to ensure an appropriate limit for each Address signal. When signals from a portable receiver assigned to a particular paging area, from a paging system are received in an adjacent paging area, then

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the synchronization hold signal SB assigned to the system of the adjacent area is not accepted by the receiver. A mix-up of incorrect synchronizations and possible false calls from the receiver due to signals from an incorrect one Systems are thus reduced considerably.

As previously mentioned, each of the address words A1 through A30 contains 32 bit positions. The first 31 bit positions can identify the party to be called, and the last bit can be used as the parity bit. All However, 32 bits can be used as the subscriber address. The preferred code is a highly redundant Bose Chaudhuri 31-16-3 code, for example 31 total bits are used to code a 16-bit message with a 7-bit (2x3 + 1) difference between each message. The usage these codes with an even parity bit increase the bit difference between the codes to a minimum of 8 Bits between adjacent individual addresses while enabling the system to serve over 65,500 users.

In addition to the extremely high subscriber address capacity made possible by the Bose-Chaudhuri-31-16-3 code, this code greatly increases the possibility of receiving the correct address while at the same time increasing the risk of receiving an address that is suitable for you other participant

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is true, is significantly reduced, even with a very high ambient noise level. For example, when decoding of an address for a certain participant two bits are tolerated as an error, then the probability is that a recipient receives this address, greater than 99 * 99 $ · As at in this example only two incorrect bits are tolerated when decoding the address, at least a 6-bit difference between the subscriber's address and any other transmitted address.

If the extremely high subscriber capacity of the code mentioned above is not necessary, then a Bose-Chaudhuri-31-H-5 code be used. Use of this code limits the number of connections allowed to 2 047, but increases it the number of differences between two coded addresses to at least 12 bits, which further increases the risk of false calls is decreased. On the other hand, if an even higher capacity should be required, then a Bose Chaudhuri 31-21-2 code be used. This code guarantees a subscriber capacity of over 2 million subscribers with a difference between any two addresses of a minimum of only 6 bits. This decreased minimum bit difference increased by 6 bits the risk of false calls, but the increase is very small compared to the considerable

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Increase the capacity of the system.

Regardless of which of the mentioned codes is used, the data format shown in FIG. 2 can be retained. Furthermore, it is not necessary that the central station has a bit capacity of J> 1 for storing the incoming addresses and address groups, because the highly redundant Bose-Chaudhuri-coded addresses can be generated in a simple manner from address signals that are less than J) I bits, for example from a 16-bit address signal when using the preferred Bose-Chaudhuri-31-16-3 code.

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III. Recipient:

One embodiment of a portable receiver 54 of FIG FIG. 1 is shown in detail in FIG. According to Fig. the portable receiver 54 of the invention comprises an antenna 500, an FM radio receiver 502, a time recovery circuit 504 and a logical synchronization and Decryption circle 506.

The antenna 500 can be a conventional antenna, preferably should take up little space in the receiver housing. For example, the antenna 500 can be a conventional ferrite antenna which is tuned to the desired wavelength.

The FM radio receiver 502 can also be a common one Be a receiver, preferably a very small, frequency-modulated radio receiver for receiving radio frequency call signals, which are picked up by antenna 500 and which modulates the radio frequency carrier signal.

The radio call signal picked up by antenna 500 is passed through a standard crystal band pass filter

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510 given, which is matched to the medium frequency with which the radio call signal is transmitted. The output of the crystal filter 510 is passed through a conventional
Radio frequency amplifier 512 amplified and fed to a conventional mixer 514. The output signal of a conventional oscillator 516 is also fed to this mixer 514, and the intermediate frequency output (IF) of the mixer 51k is amplified by a conventional IF amplifier 518 and
given to a conventional FM detector or discriminator 520.

A data output signal from the detector 520 is then applied to the timing and data recovery circuit 504 via an input terminal 503 and the output signal from the timing and data recovery circuit 504 via a common output terminal 505 to the logic synchronization and decryption circuit 506. A variety of signals
of the synchronization and decryption logic circuit 506 is applied to the timing and data recovery circuit '504 via a common terminal 507, as will be explained below.

The FM radio receiver 502 works in the usual way, i.e. represents changes in the frequency of the recorded

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Fixed radio signals within the desired frequency band, specifically with respect to a predetermined center frequency. There in the preferred embodiment of the invention, the ringing signals than signals encrypted by frequency shifting are transmitted, the output signal of the detector 520 of the FM radio receiver 502 contains a large number of pulses, which experience a change in the signal level every time there is a shift in the frequency of the input signal, which is given to the detector 520. These output pulses are preferably in the form of conventional split phase signals and contain what is applied to output terminal 503 SPDATA signal.

The timing and data recovery circuit 504 asserts converts the SPDATA signals from detector 502 to digital format with no return to zero (NRZ) and performs recovery the time signals from these signals. This NRZDATA signal and the generated time signals are then sent to the Given synchronization and decryption circuit 506, which carries out an evaluation, as later in detail in connection will be described with Fig. 19.

A _-1 timing recovery circuit

The timing recovery circuit 50 * 1 * of FIG. 5 is

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shown in detail in the functional block diagram of FIG. 4, the split phase data signal becomes SPDATA of the output terminal 503 of the detector 520 of FIG. 3 to a conventional pulse conversion generator 522 in the timing and Data recovery circuit 504 given. The output of the pulse conversion generator 522 is applied to one of the two Input terminals of AND gate 524 given and the output signal of AND gate 524 to reset input terminal R a conventional bistable multivibrator or flip-flop circuit 526.

The wrong output terminal Q, of the flip-flop circuit is connected to the excitation control input terminal D of the flip-flop circuit 556 and connected to the input terminals for a Analog data input of first and second analog switches 528 and 530. The output of analog switches 528 and 530 is applied to the control input terminal via resistors 532 and 534 a common voltage controlled oscillator 536 (VCO) given. The control input terminal of oscillator 536 can be via the capacitor 538 must be grounded.

The output signal of the VCO 536 is given to a counter 540 with divider 8, to a counter 542 with Tuler 7, via an inverter 5 ^ 3 to one of the four input terminals and AND gates 544 to 550, and finally through an inverter 551 to one of three input terminals of the AND gate 56O.

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The output signal of the counter 542 is applied to the time input terminal C of a conventional bi-stable multivibrator or flip-flop circuit 552 given, and the wrong outcome Q, of flip-flop circuit 552 is connected to the exciter control input terminal D of this circle 552 connected. The output signal of the wrong output terminal Q of the flip-flop circuit 552 is applied to one of the input terminals of all AND gates 544 to 550 and the output of the actual Output terminal Q, of flip-flop circuit 552 to one of two input terminals of OR gate 554. The output signal of the OR gate 554 is applied to the other input terminal of the AND gate 524 given.

The DI output signal of the first stage of the counter is applied to one input terminal of the AND gate 548 and via an inverter 547 to an input terminal of the AND gate 546. The D2 signal of the second stage of counter 542 is applied to one input terminal of AND gate 550, via an inverter 556 to one input terminal of the AND gate 548 and applied to an input terminal of the AND gate 558, which has two input terminals.

The D3 output of counter 542 is set to the other Input terminal of AND gate 558 given to the

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an input terminal of the AND gate 544, to the one input terminal of the AND gate having three input terminals and to one input terminal of AND gate 550 via an inverter 562. The D4 output signal of counter 542 becomes via an inverter 564 to the one input terminal of each AND gates 544, 546 and 560 are given.

The timing output signals CL1 to CL4 of AND gates 544 to 550 are applied to the samrael output terminal 505 together with the SPDATA signal of the detector 520 of FIG. 1 and the output signal BUZZ of the counter 540 with divider 8. In addition, the timing signal CL2 of the AND gate 546 is applied to the one input terminal of the two input terminals AND gate 566 given.

According to FIG. 4, the ZERO signal of the bus terminal 502 of the synchronization and decryption circuit 506 becomes of FIG. 5 is applied to one input terminal of an AND gate 568 having three input terminals, to the other Input terminal of the OR gate 554 to which one input terminal of the AND gate 570, which has two input terminals, to the one input terminal of the AND gate 56l, which has two input terminals, and finally via an inverter 572 to the other input terminal of AND gate 566.

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The output signal of the AND gate is fed via an inverter 563 to the other input terminal of the AND gate 561 and the output of AND gate 56I on the one input terminal of the two input terminal OR gate 574. The output of the AND gate is applied to the other input terminal of OR gate 574 and the output of OR gate 574 to the time input terminal C of flip-flop circuit 526.

An RCV signal is provided by the synchronization and decoding circuit 506 of FIG. J to the collective input terminal 507 of the time recovery circle 504 given and on the other input terminal of AND gate 570 and to the gate input terminal of analog switch 5JO. The initial signal] of AND gate 570 is applied to the gate input terminal of analog switch 528.

A PLC signal is generated by the synchronization logic and Decoding circuit 506 of FIG. 3 also to the collective input terminal 507 and reaches the input terminal of AND gate 568. The output of the AND gate is applied to the other input terminal of AND gate 568. The output of the AND gate 568 is applied to the reset input terminal R of the flip-flop circuit 552.

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In operation, the split phase data signal received by detector 520 of radio receiver 502 of FIG SPDATA is applied to the transition pulse generator 522 of FIG. 4 in order to generate an output pulse each time. when the signal SPDATA changes its signal level.

The pulses of the transition pulse generator 522 thus have a repetition sequence approximately twice the bit sequence of the impressed data signal; since the bit sequence of the split phase data signal is around 1,200 bits per second the repetition sequence of the from the transition pulse generator generated signal about 2,400 bits per second. It should be noted, however, that although the frequency of the signal of the transition pulse generator 522 should be around 2,400 pulses per second, but some pulses are lost because that SPDATA signal is present in the form of a data signal without returning to the value 0.

The output of voltage controlled oscillator 536 must be in phase with the incoming split phase data signal are synchronized to ensure that the time signals CLl-Cl4 with respect to their phase and their bit rate are synchronized with the incoming SPDATA signal. To ensure suitable synchronization of the voltage

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Controlled oscillator 536 becomes a phase lock loop used, which is based on the phase difference between the incoming SPDATA signal and the time signals signal related to control of VCO circuit 536 generated, as will be explained in detail later.

The output of transition pulse generator 522 is blanked by AND gate 524 and applied to the reset input of flip-flop circuit 526 to reset this circuit every time the SPDATA signal changes its signal level. Since it is desirable to quickly phase the voltage controlled oscillator 536 into phase with the incoming data signal during 12 dummy bits at the beginning of each message word all transition pulses originally through AND gate 524 blanked by the high signal level of the signal ZERO, which is from the word synchronization unit of the logical Synchronization and decoding circuit 506 is issued, as will be described in detail below, specifically with reference to FIG Bits and until the ZERO signal of the logical synchronization and decoding circuit 506 assumes a low signal level, both analog switches 528 and 530 are open (in preparation).

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Referring to Fig. 4, the phase detector flip-flop circuit 526 is controlled by the output of the voltage controlled during this initial fast sync period Oscillator 536 blanked and by the transition pulses of the pulse generator 522 is reset. The output signal the wrong output terminal Q ~ of the flip-flop circuit 526 is switched to one via the open analog switches 528 and 530 Given integrator, the resistors 532 and 534 and a Includes capacitor 538. The one generated across the capacitor 538 Voltage controls the output of VCO circuit 536, this output being brought in phase with each SPDATA signal at a frequency of about 16.8 KHz will.

to the
Since the / phase detector flip-flop circuit 526 is supplied

Phase information a frequency of 2.4 KHz during the period when the ZERO signal is in a high signal level and because the RC time constant of the integrator is sufficiently small, with the consequence of an increased bandwidth of the phase lock loop, the voltage-controlled The oscillator is quickly synchronized to the incoming SPDATA signal. However, there is still the option a phase uncertainty of + or - 180 °, which must be eliminated because the output signal of the transition pulse generator 522 not between positive and negative transitions

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can distinguish.

In order to determine the correct phase of the time signal, the output signal of the VCO circuit 536 is fed to the counter 542 with divider 7 and its 2.4 kHz output signal is used to blank the phase selection flip-flop circuit 552. When the flip-flop circuit 552 is blanked at the 2.4 KHz frequency, then the output controls the actual Output terminal Q, the passage of the transition pulses through the AND gate 524 and can be connected to the incoming Split phase data signal either in phase or out of phase. As long as the synchronization recording pattern SA of the incoming message word of the SPDATA signal is successfully recognized, the phase of the output signal changes of the phase selection flip-flop circuit 552 does not. However, if the Supplement or the complement (for example 00100 of the explained pattern 1101 of FIG. 3) is determined, then takes the PlC (Complement Synchronization Pattern) signal high signal level and the flip-flop circuit 552 is reset at the correct time, through the D2 ~ and DjJ Signals of the counter 542 with divider 7. The phase of the output signal of the flip-flop circuit 572 is thus reversed.

After the synchronization recording pattern SA or its complements have been determined by the logical synchronization

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and decryption circle 50β takes, as later with reference to the Figure 5 will be explained in detail, the ZERO signal a low signal level, whereby the AND gates 561, 568 and 570 are closed while AND gate 566 is opened. The CL2 signal then scans the flip-flop circuit 526 off. The flip-flop circuit 526 is thus reset to any other transition pulse which is caused by the Flip-flop circuit 552 is selected. In addition, the analog switch 528 closed, and the RC time constant of the integrator circuit is increased considerably, thereby reducing the bandwidth of the phase lock loop.

The counter 5 ^ 2 with divider 7 generates four output signals Dl to D4 at the actual output terminals of its stages 1 to 4, these signals are passed through the AND gate 5 ^ 4 to 550 decoded to produce the four time signals CLl to To generate ClA. The time signals CLl to CL4 are with a Repetition frequency of 1 200 KHz is generated and are against each other slightly out of phase, so that four time signals arise which are related to the repetition frequency are synchronized with the bit frequency of the incoming data stream and slightly delayed from one another. For example the time signal CLl is out of phase with the incoming data stream, so that a CLl pulse in the first quarter of each

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Bit position of the incoming SPDATA signal occurs. The signals CL2 to ClA can all be increased by a predetermined amount be delayed, about 50 to 100 msec, relative to the signal CLl and relative to one another, for example in the order in which they are named.

As will be described in detail later, the receiver is only activated during a single one of the time periods turned on, which represent the main frame. For example, the receiver can be powered for about a second and switched off for 7 seconds, based on a period of 8 seconds of the main data frame. During the turn-off time of the receiver, the RCV signal goes to a low signal level, and so does the two analog gates 528 and 530 are closed. The capacitor 5J58 however, it stores the voltage above it during the operating time of the receiver, and when the receiver returns is turned on, the VCO signal 536 is approx Phase coincidence with the incoming SPDATA signal, which is the synchronization of the time recovery circuit relieved. Since the frequency of the VCO signal 536 during the Time during which the receiver is switched off is kept almost constant, it is possible to switch off the Set the receiver with great accuracy in time, which makes it possible that the receiver to receive the data signal at the beginning of the desired period of the next

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Main data frame is switched on.

B_. Logical synchronization and decoding circuit:

The logic synchronization and decoding circuit 506 of FIG. 3, more precisely, it is a logic synchronizing and decrypting circuit is shown in detail in the function block diagram of FIG. According to Figure 5, the split phase data signal SPDATA at the collective input terminal 505 of circuit 506 is a synchronization pattern detector 600 and the BUZZ signal of the time recovery circuit 504 of Figure 4 to a call indicator 602. The time signal CLl of the time recovery circuit 504 of FIG. 4 is also sent to the synchronization pattern detector 600 given, through the collective input terminal 505; the signals CL3 to CL4 are on the Up / down counter 6O4 given. The time signals CLl to CL4 are then given to a logical on / off circuit 6o6 of the receiver. The signals CLl and CL2 at the input terminal 505 are applied to a matrix address generator 6o8 and, together with the signal CL4, to an address evaluator 610. The signal CL2 is applied to the timing signal generator 612 and the signals CL2 to CL4 to an address accepting circuit 614.

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A signal SA (determined by synchronization recording) at the output terminal 600 A of the synchronization pattern detector 600 is applied to the matrix address generator and the up / down counter 6o4. A delayed data signal DDATA at the output terminal 6OO B of the synchronization pattern detector 6OO is given to the address evaluator 6IO ge _r . The synchronization recording pattern complement or the output signal PlC is passed from an output terminal 6OO C of the synchronization pattern detector 6OO to the collective output terminal 507 of the synchronization and decryption circuit and to the time recovery circuit 504 of FIG.

According to Figure 5, a signal ZERO (zero count) of an output terminal 6O4 A of the up / down counter 6o4 to the Collective output terminal 507, to the synchronization pattern detector 600 and applied to the matrix address generator 608. A SYNC and a SYNC signal from the collective output terminal 604 B of the up / down counter 6O4 is applied to the address evaluator 610 and to the address recording circuit 614. The signal SYNC of the collective output terminal βθ4 Β can can also be given to the logic on / off circuit 606 of the receiver.

The matrix address generator 608 generates two frame signals CL32 and CL36 via the collective output terminal

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6O8 A on the up / down counter 604 and on the address evaluator 610 should be given. The signal CI / 52 of the matrix address generator 608 can also be applied to the address recording circuit 614 and the signal CL36 to the time signal generator 612 will. Row scan signals Rl and R9 "are through the Matrix address generator 60S is generated and given to an address matrix 616 via a collective output terminal 608B. The row scanning signal R9 can also be applied to the address pickup circuit 614. The row scanning signals C1 to C4 are given by the matrix address generator 608 to the address matrix 616, to be precise via a collective output terminal 608 C.

The address matrix 616 generates one or more address signals, for example the signals ADS1 and ADS2, depending on the scanning of the address matrix by the row and line scanning signals R1 to R9 ″ and C1 to C4 If only a single address signal is present, for example the address signal ADS1, then a signal Ä2 (no second address) is given via the output terminal 6I6 B to the address recording circuit 614.

The address evaluator 610 evaluates the incoming data signal DDATA relating to the locally generated address signals

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ADS1 and ADS2 and generates address error signals ERRjJA and ERRJ5B, which is sent to the address recording circuit via output terminal ÖlO A 6l4- are given. An error signal ERRl can via the output terminal βίο B to the up-down counter 6O4 and Signals G and G (synchronization maintenance scan) des Address evaluator 610 can use an output terminal 6IO C to the up / down counter 604. The output signal G of the collective output terminal 610 C can also be on the logical On / off circuit 606 of the receiver can be given.

The address recording circuit 614 evaluates the address error signal and determines whether or not an acceptable address has been received. A signal ADlAC (address accepted) is generated by the address recording circle for. the accepted addresses assigned to the recipient, and the signal is via an output terminal 6l4 A of the address recording circuit 614 given to the call indicator 602. A Output signal IRST (indicator reset) of the address recording circuit 6l4 is via an output terminal 6l4 B on the call indicator 602 given.

The on / off receiver logic circuit 606 controls the power-up and turning off the receiver during successive main frames of data. The RCV signals (receiver switched on) and RCV (receiver switched off) are connected to one

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Collective output terminal 6θβ A of the logical on / off receiver circuit 6θβ generated. The RCV signal is sent to the collective output terminal 507 of the logic synchronization and decoding circuit given and on the address recording circuit 6l4. The RCV signal of the collective output terminal 606 A of the logic on / off receiver circuit 6θβ is applied to the synchronization pattern detector βΟΟ, the matrix address generator 608, the address evaluator and the call indicator 602 given. A Signal FF 21 (time circuit reset) and a signal ADREC (address received) are sent via an output terminal 606 B of the logic on / off receiver circuit 606 to the time signal generator 612 given. A signal TRANS (address transmission), a signal FF6 and a signal FF8 from the collective output terminal 606 C of the logical on / off receiver circuit 606 becomes' given to the address recording circuit 6l4.

The time signal generator 612 generates various time signals S6, J and Y1 to Y5 at the output terminal 612 A, which are then passed to the logic on / off receiver circuit 606. Additional time signals Zl and YJ> are sent from the output terminal 612 B of the time signal generator 612 to the call indicator 602.

The logic synchronizing and decoding circuit 506 of FIG. 5 can also have a battery test circuit 6I8 and

709834/0377

have a force reset circuit 620. The Kraft-Rückfcä.1-Kreis 620 produces a POR output when the receiver is initially powered on. The signal POR is on the Time signal generator 612, the logical on / off receiver circuit 6o6, the address recording circuit 614, the call indicator 612 and given the battery test circuit 6l8 to reset these circuits, when the energy is switched on at the beginning. The battery test circuit 6l8 checks the battery voltage of the receiver, when the battery is switched on and generates a signal BBAD (insufficient battery voltage) when the output voltage the battery maintenance »has fallen by a predetermined value.

During operation, the split phase data signal SPDATA, which has been picked up by the discriminator circuit 520 of the receiver of FIG. 3, is keyed into the synchronization pattern detector 600 of FIG. 5, specifically by the time signal CLl. When the original 4-bit synchronization recording signal SA or its complement PlC has been recorded by the synchronization pattern detector 600, the up / down counter circuit 604 is increased by the count i by the signal SA. The signal PlC given to the time recovery circuit 504 of FIG. 4 changes the phase of the signal CLl when the complement of the synchronization

- 37 709834/0377

Recording signal is recorded.

According to FIG. 5, the address evaluator 610 then counts the number of binary digits ONE in the subsequent 32 bits of the synchronization recording signal as a function of the frame signals C1 / 5 2 and CLJ> 6 which are generated by the matrix address generator 60S. If one or more binary digits ONE is counted, then the up / down counter 60k is decremented by the count ONE. If no binary digit ONE has been counted, then the up / down counter 604 is incremented by a count ONE.

If the up-down counter 604 during the synchronization recording part of the incoming SPDATA signal reaches count three, indicating that the bit error rate of the incoming digital data signal SPDATA is below a predetermined value, then the signal SYNC takes a high signal level which gives the address part of the SPDATA signal the option of being used as a DDATA signal for the purpose of the following Evaluation in the address evaluator 610.

The address part of the signal DDATA, for example the 30 addresses described in Figure 2, without the synchronization maintenance signal SB, then by scanning the address matrix 6l6 synchronously with each address part of the arriving

- 38 709834/0377

the signal DDATA is evaluated, with the differences in signal level between corresponding bits in sequence the locally generated address signals ADS1 and ADS2 and the delayed data signals DDATA of the synchronization pattern detector 600 can be evaluated. When the number of differences in signal level between corresponding bits of the Address signals ADS1 and ADS2 and the signal DDATA is less than a predetermined number, the address recording circuit oil 4 enabled by one of the signals ERR ^ A and ERRJB to generate an address recording signal when the signal RCV assumes a low signal level. If the address is accepted and the RCV signal is low Signal level assumes an audible call indication signal from the call indicator 602 at the end of the period generated.

- 39 709834/0377

The synchronization maintaining part SB of the incoming signal SPDATA is also connected to a dem Receiver associated synchronization maintenance signal compared and in the address matrix 6l6 stored, for example the last four bits of the signal ADSl. An evaluation of this synchronization maintenance part SB ensures that the bit error rate of the incoming data signal is a predetermined value does not exceed over the rest of the time period. This evaluation also ensures that the receiver receives the signal of a transmitter in the appropriate paging system when two or more systems in the same paging area in Are operating.

Each address portion of the incoming DDATA signal contains at least six binary ONE signals in the case of the described one preferred embodiment of the invention, during the J52-bit O-signal part of the synchronization received signal contains less than six binary digits ONE. Counting 6 in a counter that is only on Thus, responding to the digits ONE in address interpreter 610 may cause an address instead of a O signal part is evaluated. The count 6 in coincidence with the CI / 56 frame signal causes the Signal G becomes high, and then another sync pickup pattern is recorded as the pattern SB, the up / down counter 6O4

709834/0377 - 40 -

decrease and a record of any synchronization maintenance pattern S Increase the up / down counter 6o4. If at the end of the period the SYNC signal is still is at a high signal level, indicating that the bit error rate of the SPDATA signal over the entire time period has been accepted, the receiver circuits are switched off until the SPDATA signal is in the same Period of time occurs during the next main frame. To switch off the receiver circuits for the desired Time interval, the signal RCV of the on / off logic circuit 6o6 will assume a low signal level, for one Time span of about 6.72 seconds (if the data frame consists of eight time segments of one second each) in Dependency on the signal S 6.7 of the time signal generator 612. The logical on / off receiver circuit 6o6 then switches the receiver circuits on again immediately, before the data signal SPDATA in the selected time segment during the next main data frame arrives.

As mentioned earlier, the call indicator 602 generates an audible alarm signal if an address is successful during of a certain period of time has been evaluated. If two different addresses are assigned to the recipient have been, for example, each address indicating that another caller or group of callers is a Connection with the subscriber wishes, then two different audible tones are eyed by the call indicator 602. That

- 41 70983 4/0377

Signal BUZZ of the time recovery circuit, which indicates that the receiver is switched on, can for example a 2.1 kh signal and given to an audible indicator, such as an electromagnetic one Converter, with which a continuous tone depending on the reception of one of the two address signals ADSl, assigned the receiver, while a pulsating one Sound is generated as a function of the reception of the other address signal ADS2, assigned to this receiver.

l_. Synchronization pattern detector;

The synchronization pattern detector of FIG. 5 is shown in detail in the functional block diagram of FIG Figure 6 shown. According to FIG. 6, the split-phase data signal SPDATA of the collective output terminal 505 of time recovery circuit 504 of Figure 4 one or more shaping amplifiers 622 are applied to the data input of a four-bit shift register 624. That CLl time signal of the collective input terminal 505 of the time recovery circuit 504 of FIG. 4 is applied to the time input C of the shift register 624. The RCV signal the output terminal 6o6A of the logic on / off receiver circuit 6o6 of FIG. 5 is connected to the reset input terminal of the shift register 6? 4 given.

- 42 70983 4/0377

When the four-bit sync recording pattern SA can be represented by 1101, then the output signals Ql, Q2 and Q4 of the actual output terminal of the first, second and fourth stages of the shift register 624 given to three input terminals of an AND gate 626 having four input terminals and the output signal Q3 of the wrong output terminal of the third stage of the shift register 624 to the fourth input terminal of the AND gate 626. The signal Pl (pattern recognized) of the AND circuit 626 is applied to an input terminal of an OR gate 628 having two input terminals given and the output signal SA (synchronization recording pattern recognized) of the OR gate 628 to the output terminal, emme 600A of the synchronization pattern detector 600 and further to the up / down counter 604 and the matrix address generator 6O8 of Figure 5

The signals ÖT, Q2 * and Q4 ~ of the wrong output terminal the first, second and fourth stages of the shift register 624 are applied to the three input terminals of a four input terminals having AND gate 63O given and the Signal Q3 from the actual output terminal of the third stage of shift register 624 to the fourth input terminal of the AND gate 630. The output signal PlC (synchronization pattern complement recognized) of AND gate 630 is applied to the input terminal of an AND gate having two input terminals 632 and to the output terminal 6OOC of the synchronization pattern detector 6OO. The ZERO signal of the

709S3Ü / 0377 - 43 -

The output terminal 6o4A of the up / down counter 6θ4 of FIG. 5 is applied to the other input terminal of the AND gate 6j> 2, and the output of the AND gate 632 is applied to the other input terminal of the OR gate 628.

During operation, according to FIG. 6, the

Signal RCY returns the shift register. 624 when the receiver turned off for the first time. The signal SPDATA is shaped by the shaping amplifier 622 and into the shift register 624 keyed in by the time signal CLl.

When the AND gate 626 is the four-bit sync pickup pattern SA picks up, then the signal SA assumes a high signal level for the duration of one CLl time pulse until the next CLl time pulse. If the Count in the up / down counter 6O4 of Figure 5 is zero and that Complement of the four-bit sync pickup pattern SA is received from AND gate 6j50, then picks up the output SA has a high signal level and the signal PlC also has a high signal level, the phase of the CLl time signal is changed, as already mentioned above has been described. If either the sync pickup pattern or its complement from the AND gates 626 and 630 is received, then that increases a high Signal SA having signal level the up / down counter 6θ4, as will be described later with reference to FIG. 7, and then AND gate 632 is closed and only one Successful reception of the synchronization »recording pattern SA by the AND gate 626 is an output signal SA with

709834/0377 -44-

can generate a high signal.

The output signal Ql of the actual output terminal the first stage of shift register 624 appears at the output terminal 600B as output signal DDATA. The DDATA signal is evaluated by the address evaluator 6IO, as will be explained later in connection with FIG.

2_. Up / down counter:

The up / down counter 604 of the logic synchronizing and decrypting circuit of FIG. 5 is detailed shown in the function block diagram of FIG. According to FIG. 7, the signal CLj5 becomes the collective input terminal 505 of the logic synchronizing and decoding circuit 500 of FIG. 5 to an input terminal of a six input terminals having AND gate 6j54, to an input terminal of the AND gate having five input terminals 636, to one input terminal of a four-input terminal AND gate 638 and to an input terminal of the AND gates 640 to 644, which have five input terminals given. The CL4 time signal of the collective input terminal 505 of the logic synchronizing and decoding circuit 505 of FIG. 5 can also be applied to the one input terminal the four AND gates 646 to 652, each having two input terminals.

- 45 709834/0377

2261333

According to FIG. 7, the decoded signal SA of the output terminal 600A of the synchronization pattern detector 600 of FIG. 20 is applied to the one input terminal of the AND gate 636 and, via an inverter 641, to the one input terminal of the AND gate 640 of the address evaluator 610 of FIG. 5 is applied to an input terminal of the AND gates 642 and 644 and, via an inverter 654, to an input terminal of the AND gates 6} 4 and 638.

The output signal G (first address signal received) of the output terminal 6IOC of the address evaluator 610 of FIGS. 5 and 10 is applied to one input terminal of the AND gate 642 and the signal (T of the output terminal 6IOC to an input terminal of the AND gates 636 and 640. The frame signal CL32 the output terminal 608A of the matrix address generator 608 of figures 5 ^nd 8 is in each case to an input terminal of the aND gates 648 and 6 ^ 4 and the output signal CL36 the collector output terminal 608A of the matrix address generator 608 each have an input terminal of the AND gates 646 and 636-642.

The output of the AND gate 6 ^ 4 is on an input terminal of the three input terminal OR gate 656 given and output signals of the OR gate 656 to the "up" input terminal of a standard two-stage up / down counter 659.

709834/0377 -46-

The output of AND gate 636 is set to second input terminal of the OR gate 656 given and that Output of AND gate 638 to an input terminal of two input terminal AND gate 658; the The output of gate 658 is applied to the third input terminal of OR circuit 656.

The output of AND gate 640 becomes

to an input terminal of a three input ski eminen OR gate 660 given and the output signal of AND gate 642 to the second input terminal of this OR gate 66O. That The output signal of the AND gate 644 is applied via an inverter 662 to the time input terminal C of a conventional bistable Multivibrators or flip-flop circuit 664 given to the third input terminal of the OR circuit 66O. The output signal of OR circuit 66O is applied to the "down" input terminal of up / down counter 659.

The output signals ÖX and Q2 of the wrong output the first and second stages of the up / down counter 659 applied to the input terminal of an AND gate 666 having two input terminals. The output signals Ql and Q2 of the actual output terminals of the first and second stages of the up / down counter 659 become the input terminals of a AND gate 668 having two input terminals. The signal ZERO of the AND gate 666 is applied to the second input

- 47 709834/0377

terminal of AND gate 65O, to output terminal 6O4A, and finally applied via an inverter 670 to one input terminal of the AND gates 6 ^ 4 and 640-644. The output signal THREE of AND gate 668 is applied to the other input terminal of AND gate 652 and via an inverter 672 the input terminal of AND gates 6 ^ 4 and 636 given and also to the other input terminal of AND gate 658.

The output of AND gate 652 becomes to the excitation input terminal S of a bistable multivibrator or flip-flop circuit 674 and the output signal of the AND gate 65O to the reset input terminal R of this flip-flop circuit 674. The output signal SYNC of the actual output of the flip-flop circuit 674 is on the Collective output terminal 6O4B given and further to the input terminal of AND gate 638. The output signal SYNC of the wrong Output terminal Q of flip-flop circuit 674 is on the collective output terminal 604B and on to the input terminal of AND gates 634 and 644.

The output signal of the AND gate 646 is applied to the excitation input terminal S of the flip-flop circuit 664 given and the output of the AND gate 648 to the reset input terminal R of this flip-flop circuit 664. The Excitation control terminal D of flip-flop circuit 664 is grounded, and the output signal ADGT (address gate) of the actual

709834/0377

neuter output terminal Q of the flip-flop circuit 664 is given to another input terminal of AND gate 644.

During operation, as shown in FIG. 7, the RCV signal becomes the up / down counter 659 in the up / down counter circuit 604 Reset to the value zero by clearing the up / down counter 659. The ZERO signal on the counter 659 responsive AND gate 666 assumes a high signal level and thus closes AND gates 634 and 640-644. If the AND gate 668 is closed, then the signal THREE assumes a low signal level unc (thus opens the AND gates 634 and 636. Since AND gate 634 also through

is

the signal ZERO closed ^ is only the AND gate 636 ready when the count in the up / down counter 659 is zero.

When the first four-bit sync pickup pattern SA or its complement is received by the sync pattern detector 600 then that takes Signal SA goes high and is signaled through AND gate 636 by the CL3 timing signal and the CL36 frame signal blanked. The output of AND gate 636 goes high and is applied to the "up" input terminal an up / down counter 659 through the OR gate 656 to increment the up / down counter by one count.

- 49 -709834/0377

The ZERO signal of AND gate 666 then takes one low and AND gates 640-644 and 6 ^ 4 are all opened, so counter 659 is either can be raised or lowered.

Before counting three is reached and the flip-flop circuit 674 is triggered, the up / down counter 659 can through the successful recording of the four-bit SA portion of the sync record signal or raised by the inclusion of the 32-bit O part of the sync capture signal will. After the flip-flop circle 674 due to the successful Recording of the sync pickup signal has been excited, becomes the sync pickup pattern SB either raise or lower the up / down counter 659. Table II shows possible combinations of the signal conditions, which cause the up / down / counter 659 to increase.

TABLE II

Data designation signal combination signal function

(high signal level)

AND gate 634

ZERO don't count zero THREE don't count three CL 32 End of 32-bit O- Signal or address SYNC " Flip-flop circle stimulates CL 3 Time (3rd phase) ERRl less than 1 error in every 32-bit O- Signal part of the syn- chroniations recording signals or SB-Mu sters counted

709834/0377 - 50 -

AND gate 636

THRI SA

CL36

CL3

do not count three sync recording patterns decodes the end of the four-bit pattern SA or SB

Sync recording signal still in the evaluation time (3rd phase)

AND gate 658

SYNC CI / 36

errT

CL ';
THRI

Flip-flop circle excited the end of the four-bit pattern SA or SB

less than 1 fault counted Time (3rd phase) do not count three

From Table II above, it can be seen that the THREE signal prevents the counter 659 from being outside a Count three is raised. In addition, the signal ERRl can indicate that less than 1 binary digit ZERO in the 32-bit 0-signal part of the keep-sync signal or that less than a single error occurs during the evaluation of the keep-sync pattern SB has been established. However, the frame signals CL32 and CL36 distinguish between these two possibilities, with AND gate 634 pointing to the Detection of the synchronization maintenance signal SB responds.

When the count of the up / down counter is 659 is at the value one or at a h & Bren value, then the counter 659 can be decreased by the opened AND circles 640-642. Table III shows the various possible combinations of signal conditions that affect the up / down

Lower counter 659.

709834/0377

TABLE III

Gate designation

Signal combination signal function (high signal level)

AND gate 640

ZERO SA

CL3

Synchronization recording Signal is still being evaluated

do not count null synchronization Recording Pattern not ent _T down

End of the four-bit pattern SA or SB
Time

AND gate 642

ZERO ERRl

CL36 CL3

first address signal received
do not count zero or more errors counted

End of four-bit pattern SA or SB
Time

AND gate 644

ZERO SYNC ADGT

ERRl

do not count zero flip-flop circle excited address gates (still for 32 bits between adjacent four-bit synchronization patterns) one or more errors counted
Time

From Table III above, it can be seen that an erroneous four-bit sync pickup pattern SA denotes Up / down counter 659 decreases via AND gate 640 and that one or more binary digits ONE in the 32-bit O part of the Synchronisatic recording signals the up / down counter 659 via the AND gate 644 lower. After the first address signal has been received,

- 52 -

709334/0377

- ■)! .. -

ssr

the signal G assumes a high signal level Tina a successful acquisition of the four-bit sync keep signal SB, indicated by a high signal level of the ERRl signal, decreases the counter 659 above that AND gate 642 turns off.

When the up / down counter 659 is counting three not reached and the flip-flop circuit 674 during the 112-bit sync pick-up portion of the incoming SPDATA signal excites, then the addresses arriving during the rest of the time period are not decoded. Count three can be achieved by the up / down counter during the il2-bit synchronization recording portion of the incoming SPDATA signals in the following way:

TABLE IV

Synchronization recording signal SA 32 0's SA 32 O's SA 32 O ¹ S SA

Counting in up / down counter 659

1 2 3 3 O O 1 2 1 2 1 2 1 O 1 '2 O O O O O O 1 2 1 O O O 1 O t-H O 1 O 1 2 1 2 1 O 1 2 1 2

3 3 3 3 3 3 3 3 3 3 3 3 1 2 3 1 2 3 1 2 3 t-l 2 3 1 2 3 1 2 3 1 2 3

- 53 -

709834/0377

Of course, the synchronization flip-flop circuit 674 can subsequently be reset before the end of the period is reached when the bit error amount of the incoming SPDATA signal is excessive, such as this is indicated by the incomplete recording of a sufficient number of successive synchronization signals after resetting the flip-flop circuit 674 at the end of a period of time. In this case the SPDATA signal is sent to the Subsequent periods of time are evaluated until the amount of bit errors in the SPDATA signal is within the desired tolerances is located. If the bit error amount of the SPDATA signal is within the desired tolerance, then will the flip-flop circle 674 is also still at the end of the time segment are in the excited state and the receiver will turned off for a predetermined period of time and then immediately before the arrival of the SPDATA signal of the same time period of the next main data frame switched on again.

2j matrix address generator;

The matrix address generator 606 of the logic synchronizing and decoding circuit of FIG shown in detail in the functional block diagram of FIG.

According to FIG. 8, the CLl time signal is the Collective output terminal 505 of the time recovery circuit of

- 54 709834/0377

4 applied to the time input terminal C of a conventional two-stage ring counter 680 and the CL2 time signal from the collective output terminal 505 of the time recovery circuit 4 to the one input terminal of an AND gate 682 having three input terminals.

- 55 -

709834/0377

The SA signal from the output terminal 600A of the synchronization pattern detector 600 of FIG. 6 is applied to the other input terminal of AND gate 682 and the signal ZERO of the output terminal 6OOA of the up / down counter 6o4 of the FIG. 7 to the other input terminal of AND gate 682. The output signal of AND gate 682 is applied to the Reset input terminal R of the ring counter 680 and to a reset input terminal R of a suitable conventional five-stage torsion ring counter 684.

The output signals Ql, qT, Q2 and Q2 ~ of the two stages of the ring counter 68O are applied to a suitable gate circuit 686 in order to generate successive line key signals Cl to C4, which appear at the output terminal 608C of the matrix address generator 608. The signal Cl des Gate circuit 686 is also applied to the time input terminal C of torsion ring counter 684 and that Signal C4 of gate circuit 686 to the AND gates, which each have two input terminals 688 and 69O.

The output signals RI-R9 of the 1-9 output terminals of the torsion ring counter 684 are blanked through a plurality of NAND gates 692 and the row strobe signals rX to R ~ 9 ~ of the NAND gates are sent to the collective output terminal 608B of the matrix address generator 608 is impressed

709834/0377

- 56 -

- 56--

and then to the address matrix circle 6l6 and the address receiving circle of FIG. 5 forwarded.

8, the signal R8 of the torsion ring counter 684 applied to the second input terminal of the AND gate 688 and the signal R9 of the torsion ring counter to the second input terminal of AND gate 69O. The frame signal Cl / 52 and the frame signal CLj56 of the output terminal the AND gate 688 and the AND gate 690 are applied to the collective output terminal 608A of the matrix address generator 608 appear and on the address evaluator 610, the up / down counter 6o4 and the time signal generator 612 of FIG. 5 forwarded.

During operation, the two-stage counter is du.:Oh the CLl time signal with a sampling rate of 1,200 bits per second is blanked and generates the successive line strobe signals Cl-C4 once during the four bits of the Time signal. The signal C1 samples the torsion ring counter 684, and the row strobe signals RI-R9 become one time generated during the nine line keys. Since both ring counters 680 and 684 are started at the same time, namely, when the first synchronization reception pattern arrives, the line key signals and the line key signals are is synchronized with the incoming] 52-bit patterns that are between the sync record signals

- 57 709834/0377

and the synchronization maintenance signals occur,

The row key signal C4 and the row key signal Re coincide exactly at the end of the 32-bit pattern. These two signals thus generate the CL32 signal exactly J> 2 pulses after receiving the SA pattern. The signals R9 and C4 coincide exactly at the time of J> 6. Pulse in the data signal after the SA signal has been recorded. The signal CI / 36 generated as a function of the signals C4 and R9 thus occurs precisely at the beginning of the 32-bit O-pattern and the address pattern received subsequently.

4. Address matrix:

The address matrix 616 of the logic synchronizing and decoding circle 506 of FIG. 5 is detailed shown in the functional block diagram of FIG.

According to FIG. 9, the row key signals RT-R9 of the output terminal 608B of the address matrix generator 608 of FIG. 5 are applied to the Rl ¹ -R9 'input terminals of a 9X4 address matrix, as shown at 694A and 694b are. If more than two addresses are to be assigned to a specific recipient, additional address matrix circles can be provided.

- 58 -

709834/0377

Each of the address matrix circuits 694 can be represented by a conventional breakdown diode matrix, with all of the output lines C1'-C4 'being connected to each of the row input lines R1'-R9' via diodes and a fuse link. The address assigned to the receiver can be permanently stored in the matrix by blowing through certain fuse links in series with the diodes, so that certain rows and lines are switched off and are not grounded by the input signals RT-R9 "while the address matrix is being scanned can thus, if a specific line-out output line in response to the line-scan-signal Cl -. C4 is read out, then those row line connections are proposed when reading a binary oNE, which are open, the Cl. ¹ - CV Output terminals of address matrix 694A are connected to an input terminal of AND gates 696-699, which have 4.2 input terminals, and also to a source of positive potential via associated resistors 700-703.

The C1-C4 row strobe signals from the output terminal 608c of the matrix address generator 608 of FIG to the other input terminal of AND gates 696 - 699 given. The outputs of AND gates 696-699 are applied to an input terminal of an OR gate 704 having four input terminals and the output signal of the OR gate 704 to the output terminal 616A,

709834/0377

- 59 -

as an address signal ADSl.

The circuit generating the second local address signal, using the address matrix 694B, can be the same as that which has been explained in connection with the address matrix 69 ^ A and is therefore no longer specifically described. The second address signal ADS2 can be used to send Collective output terminals 616A of the address matrix occur and is then sent to the address evaluator 610 of the Fig. 5 given.

The output signal 2 ~, which indicates that the second address matrix 69 ^ B is not in use, becomes applied to the output terminal 61 dB of the address matrix 6l6. The signal A2 is processed by the address receiving circuit 616 of Fig. 5 in a manner as will be described below in connection will be described in detail with FIG. 11.

^ j. Address evaluator:

The address evaluator 610 of the circle 506 of Fig. is described in detail with reference to the functional block diagram of FIG.

- 60 -

7098 3 Λ / 0377

According to FIG. 10, the address signals ADS1 and ADS2 of the collective output terminal 616A of the address matrix 6l6 of FIG. 9 is applied to an input terminal of a gate 706 which "exclusively or" (EXOR) and to an input terminal of a gate 708, which also has two input terminals EXOR '. The DDATA signal of the output terminal 6OOB of the synchronization pattern detector 600 of FIG. 6 is applied to the other input terminal of EXOR gates 706 and 708, to an input terminal of one having two input terminals AND gate 710 and given to an input terminal of an AND gate 712 having four input terminals.

The output of the EXOR gate fOß and the EXOR gate 708 is applied to an input terminal of an AND gate 71 ^ having two input terminals and to an input terminal of an AND gate 709 having three input terminals. The output signals of AND gates 714 and 709 are applied to one input terminal of an OR gate 716 having two input terminals or to the time input terminal C of a conventional error counter 711, for example a two-stage binary counter. The output signal of the OR gate 716 is applied to the one input terminal of an AND gate 718, which has three input terminals, and the output signal of the AND gate 718 is applied to the time input terminal C of a conventional error counter 720, for example a two-stage binary counter.

709834/0377 - ^6l ~

The output signal Ql of the actual output terminal the first stage of the error counter 720 is applied to one input terminal of a two input terminal AND gate 722 given and to an input terminal of an OR gate 724 having two input terminals The output signal Q2 of the actual output of the second stage of the error counter 720 is applied to the other input terminal of the AND gate 722 and to the other input terminal of the OR gate 724 and the output signal ERRl of the OR gate 724 to the output terminal 610B of the address evaluator 610 and further to the up / down counter 6O4 of FIG. 7. The output signal of AND gate 722 is applied to the input terminal of the AND gate 718 and via a further inverter 728 to the collective output terminal 610A as an address error signal given.

The output signals Q1 and Q2 of the actual output of the first and second stages of the error counter 711 are applied to the input terminals of an AND gate 713 having two input terminals. The output signal ERR3B of the AND gate 713 is applied via an inverter 715 to the input terminal of the AND gate 709 and via an inverter 717 to the collective output terminal 6l0A of the address evaluator 610, as an ERR JiB address error signal, which is then finally given to the address receiving circuit 614 of FIG.

709834/0377

The SYNC signal of the collective output terminal 6o4B of the Up / down counter 6O4 of the Pig. 5 and 7 will be on top of the other Input terminal of AND gate 714, to a second input terminal of AND gate 712 and to the one input terminal of an AND gate having four input terminals 730 given. The SYNC signal of the collective output terminal 6o4B is transferred to the other input terminal of the AND gate 710 and to the reset input terminal R a conventional bistable multivibrator or flip-flop circuit 732 given. The output of the AND gate 710 is applied to the other input terminal of the OR gate 716.

The frame signals CL32 and CL36 of the collective output terminal 6O8A of the matrix address generator 608 of FIG. 5 and 8 are each to the one input terminal of an AND gate 734 and to the one input terminal of an AND gate 736 having two input terminals. The CL32 frame signal can also be applied to the input terminal of AND gate 730 from terminal 608A of the matrix address generator 608 of FIG. 8.

10, the output of AND gate 736 is applied to the input terminal of the three input terminals OR gate 738 given and the output signal of the AND

- 63 -

709834/0377

Gate 73 ^ to the second input terminal of the OR gate 738. The output of the OR gate 738 is set to the Reset input terminal R of the error counters 7II and 720 and to an input terminal of an AND gate 740 having two input terminals. The output signal of AND gate 740 is applied to the reset input terminal R of a conventional three-stage counter 742 and the outputs of the wrong output terminal of the first stage and the actual output terminals of the second and third stages of the counter 742 are each fed to the input terminal of a three input terminal AND gate 744 connected. The output of AND gate 744 is applied to the input terminal of AND gate 730 and via an inverter 746 to the input terminal of the AND gate 712; the output of the gate 712 is based on the time change output C of the counter 742 given. The output of the AND gate 730 is applied to the excitation input terminal S of the Flip-flop circuit 732, and the output signals G and G of the actual and false outputs of the flip-flop circuit 732 appear at the collective output terminal 6IOC of the address evaluator 610, whereupon it is then sent to the up / down counter 6o4 of FIG. 7 and to the on / off logic receiver circuit 6θβ of FIG. 5 can be given. The signal G is applied to the second input terminal of the AND gate 740 10 given.

The time signal CLl of the collective input 505 of the

709334/0377

- 64 -

Logical synchronization and decoding circuit 506 of FIG. 5 is applied to an input terminal of AND gate 730 given and the signal CL2 of the terminal 505 to the one input terminal of the AND gates 509, 712 and 718. The Time signal ClA of input terminal 505 is applied to one Input terminal of AND gates 734 and 736 given. That Signal RCV of the collective output terminal 606A of the logical On / off receiver circuit 606 of FIGS. 5 and 14 is applied to the third input terminal of OR gate 738.

During operation, as shown in FIG. 10, the signals ADS1 and ADS2 of the address matrix 616 are in sequence after given to the EXOR gates 706 and 708, where they relate to the delayed data signal of the synchronous Pattern detector 600 are evaluated. The signal level of each bit of the DDATA signal becomes the signal level of the corresponding bit of the logically generated address signals ADS1 and ADS2 compared and each time a difference in the signal level between the bits of the signal DDATA and the locally generated address signals ADSl and ADS2 occurs, the output of the EXOR gate and the EXOR gate 706 and 708 which are connected thereto assume a high signal level.

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When the SYNC signal is high, indicating that the up / down counter 6o4 succeeded counted up to the value j $, i.e. a synchronization is present, the mentioned counting during the synchronization reception part of the DDATA signal occurs, the output signal of the EXOR gate 706 is applied to the AND circuit 718 via the OR gate 716. The output signal of EXOR gate 708 is applied to AND gate 709 regardless of the condition of the up / down counter

As long as the count in the error counter 711 and the count in the error counter 720 is below the value 3, the AND gates 709 and 718 should be open, and those of the EXQR gates 706 and 708 generated error signals are blanked via the AND gates 718 and 709 by the timing signal CL2, and these error signals are then counted by the error counters 720 and 711. If the count in the error counter 711 and that reaches the value 3 in the error counter 720, then the output signals AND gates 713 and 722 go high and AND gates 708 and 718 close; in addition, the signals ERR3B and ERR ^ A will go low, indicating that three or more There are differences between the received and the locally generated addresses. The signals ERR3Ä "and ERRjJB

709834/0377 " ⁶⁶ "

are made by the address receiving circuit 614 of FIG checked at the end of each address part of the message word to determine whether or not one of the respective Address assigned to the recipient has been successfully evaluated, as detailed below will be described.

The output signals Q1 and Q2 of the error counter are also applied to the OR gate 724. If during of the original synchronization recording part of the message word the SYNC signal is high indicating that the up / down counter 604 of FIG. 7 is still has not reached count 3, then the signal DDATA is through the AND gate 710, the OR gate 716 and the AND gate 718 applied to the error counter 720. Of the Error counter 720 is reset immediately after receipt of the first synchronization reception pattern SA and then it counts the number of digits ONE in the 32-bit O part of the sync recording pattern. If one or If several digits ONE have been counted in this part of the synchronization recording signal, then the ERRl signal assumes of the OR circuit 724 assumes a high signal level and the count in the up / down counter 6o4 is decremented by count 1, as has already been explained before.

709834/0377

The DDATA signal is also applied to a three-stage counter 742 via AND gate 712. The three-stage Counter 742 counts the number of digits ONE in that part of the signal DDATA which is between the synchronization receiving part and the synchronization maintaining part, thus located between the patterns SA and SB; when a count of 6 is reached then that takes The output of AND gate 744 goes high, indicating that the first address portion of the DDATA signal has been received. Then the synchronization maintaining parts SB of the incoming Data signal with a locally generated synchronization maintenance signal compared which is assigned to the particular receiver (the last four bits of the local generated address signal ADSl), and then the ERRl signal shows through a high or a low Signal level indicates whether a successful or not a successful decryption of the synchronization maintaining part of the incoming SPDATA signal has been made.

As already described above in connection with FIG. 2, the incoming signal preferably contains a data stream of the following pattern:

S _A 32 O ¹ SS _A 32 O's S _A 32 O's S _A Μ _χ S _ß M ₃ S _ß

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- 68 -

where S = 1101 or any other suitable four-bit pattern;

32 0 ¹ S = 32 subsequent ZERO signals; Sg = some four-bit pattern j and

M ₁ , M ₂ , M, M ^ ₀ = any 32-bit pattern without any NULL signals if the pattern is a 31 »16, 5 BCH code with even parity.

The identifier of the binary count signal ONE in the data stream after synchronization is as follows: Synchronization can be achieved at the end of the second, third and fourth S pattern, depending on the error rate of the data stream. Counting the digits ONE in the 32-bit intervals allows the location to be identified of the signal in the data stream. This is possible because the 32-O signal pattern does not contain digits ONE and all

M pattern (M ,, M ₂ , M-, ^ "3? ^ At least 8 binary digits

ONE included. This condition is made by using the BGH code (Bose-Chaudhuri) guarantees even parity.

The entire data stream consists of alternating 4-bit words and 32-bit words, and the 4-bit words become always used for synchronization.

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The first three, and only the first three 32-bit words are used for synchronization. The other 50 of the 32-bit words (M ,, Mp etc.) are used for the addresses used. However, data technology is not limited to the use of exact patterns or sequences.

6. Address admission group:

The address recording circuit 6l4 of the logic synchronizing and decoding circuit 506 of FIG. 5 is detailed in the functional block diagram 11 shown.

Referring to Fig. 11, the signals ERR3A and ERR ^ B of the Output terminal 610A of the address evaluator 610 of FIGS. 5 and 10 to the one input terminal of the AND gate 750, which has four input terminals, and to an input terminal of an AND gate, which has four input terminals 752 given. The CL32 frame signal from output terminal 608A of matrix address generator 608 of FIGS. 5 and 8 becomes given to the second input terminal of the AND gate 750 and to the second input terminal of the AND gate 752. That SYNC signal from output terminal 6o4B of up / down counter 6O4 5 and 7 is applied to an input terminal of AND gates 750 and 752 and the CI / 3 timing signal of the input terminal 505 of the synchronization and decryption logic circuit 506 of FIG. 5 to the fourth input terminal

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- 7 0 -

the AND gates 750 and 752 and further to an input terminal of an AND gate having two input terminals

The output of AND gate 750 is set to Excitation input terminal S of a suitable bistable Multivibrators or flip-flop circuit 756 given and the output of AND gate 752 on the excitation input terminal S of a bistable multivibrator or flip-flop circuit 758. The output signal of the actual Output terminal Q, of flip-flop circuit 756 becomes to the one input terminal of an AND gate 76Ο having two input terminals and the output signal the actual Q output terminal of flip-flop circuit 758 to the one input terminal of one of two input terminals having AND gate 762. The "address # 1 accepted" output ADAC of the AND gate 760 and the "address no. 2 accepted" output signal AD2AC of AND gate 762 are applied to a collective output terminal 614A and given to the call indicator 602 of FIG.

The RCV signal of the output terminal 6OOA of the logical On / off receiver circuit 606 of Figs. 5 and 14 is opened one input terminal of an AND gate 764 having three input terminals and one input terminal of an AND gate having three input terminals 766. The SYNC signal of the collective output 6O4A of the up / down

709834/0377 _ _{? 1} _

Counter 604 of FIGS. 5 and 7 is switched to the other input terminal each of AND gates 764 and 766 are given. The FF6 signal of the collective output terminal 606C of the On / off receiver logic 606 of FIG. 5 is applied to the third input terminal of each AND gate 764 and 766 given.

According to FIG. 11, the FF8 signal is transmitted via the collective output terminal 606C of the logic on / off / receiver circuit 606 of FIG. 5 is applied to the other input terminal of the AND gate 754 and to the one input terminal an AND gate 768 having three input terminals. The output signal λ2 * of the address matrix 616 of FIG is connected to one input terminal of the AND gate, which has three input terminals, via input terminal 616B 770 and the CL2 and CL4 timing signals of the timing recovery circuit 4 via the collective input terminal 505 to the AND gates 768 and 770. The The R9 signal of the output terminal 608B of the matrix address generator 608 of FIG. 8 is applied to the third input terminal of the AND gate 770.

The output of AND gate 764 is applied to the input terminal of a three input terminal OR gate 772 and the output signal of AND gate 754 to the second input terminal of OR gate 772 and finally an output terminal 6l4B of the address

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Recording circle 6l4 as an "indicator reset" output signal IRST given. The output of the OR gate 772 is applied to the reset input terminal R des Flip-flop circuit 756 given and the output of the wrong output terminal Q of the flip-flop circuit 756 the third input terminal of AND gate 768.

The outputs of AND gates 766, 768 and 770 are each on an input terminal of a four Input terminals having OR gate 774 given and the output of OR gate 774 on the reset input terminal R of flip-flop circuit 758. The POR output of output terminal 620A of circuit 620 5 is applied to one input terminal each of the OR gates 772 and 774 and the "address transmission" signal TRANS from the on / off receiver logic circuit 606 of FIG. 5 via terminal 606C to the other input terminal the AND gates 760 and 762.

In operation, as shown in Fig. 11, the address error signals ERRJ5A and ERRJ5B of address evaluator 610 of FIG. 10 through AND gates 750 and 752 at the end of each " Address part of the incoming data signal DDATA is examined, i.e. when the frame signal CL ^ 2 is high Signal level assumes and when the up / down counter 6o4 the Count has reached 5, which corresponds to a synchronization condition. If any of the address error signals

709834/0377 '^7J>'

ERRjJA or ERR ^ B is at a high signal level, indicating that there are fewer than three errors between the logically generated and received address signals, then the output of the respective AND gates 750 and 752 assumes a high signal level for the Duration of the CL3 time signal, which causes the associated flip-flop circuit 756 or 758 is excited.

The address transition signal TRANS of the on / off receiver logic circuit 606 of FIG. 5 goes high Signal level at the end of each time segment in which the incoming data signal has been evaluated. if the signal TRANS assumes a high signal level and if one of the flip-flop circuits 756 or 758 has been activated, then the corresponding ADAC or AD2AC output signal of AND gates 7βθ or 762 also has a high signal level indicating that one of the address signals associated with the receiver was successful during the respective Period of time has been deciphered. The signal having a high signal level is set on the call indicator 602 of FIG. 5, which emits an audible alarm signal indicating that one or the other other of the addresses assigned to the recipient has been received and successfully evaluated.

709834/0377

The POR signal (energy at rest) of the circuit 620 of FIG. 5 initially sets the flip-flop circuit 756 and flip-flop circuit 758 back when the receiver is switched on. If the bit error amount of the incoming data signal SPDATA after receiving the first address part of the message signal becomes excessively high, i.e. when the SYNC signal assumes a high signal level, then AND gates 764 and 766 then become one assume a high signal level and the flip-flop circuit 756 or 758, via the OR gates 772 and 774. The indication of a call by the call indicator 602 of FIG. 5 is thus prevented if the bit error amount of the incoming data signal is too high Point in time during the decryption of the address signals in a certain period of time a certain Value exceeds.

Signals FF8 and CLJ5 received from on / off receiver logic 606 of FIG. 5 and the timing recovery circuit 4 to the AND gate 754 or 756 and 758 at the beginning of each new time segment or of each data subframe. However, if both of the addresses assigned to the particular recipient are included and successful for the same period of time

- 75 -

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have been evaluated, then the output signal of the wrong output terminal of the flip-flop circuit 756 closes the AND gate 768, which prevents the flip-flop circuit 758 from being reset until both addresses are taken have been and have triggered call displays separately from each other, as detailed below in connection will be described with FIG.

! Reputation indicator

The call indicator 602 of the synchronization and decryption logic 506 of FIG. 5 is shown in detail in the functional block diagram of FIG. According to FIG. 12, the two "address recording" signals AD1AC and AD2AG of the output terminal 6l4A of the address recording circuit 6l4 of FIGS. 5 and 11 are applied to the excitation input terminals S of the bistable multivibrator or flip-flop circuit 776 and 778, respectively. The output signal of the actual output terminal Q of the flip-flop circuit 776 is applied to the one input terminal of an AND gate 78Ο having two input terminals and the output signal of the actual output terminal Q of the flip-flop circuit 778 is applied to the one input terminal of a three input terminal AND -Gate 782. The output signals of AND gates 780 and 782 are given to two input terminals of an OR gate 78k having three input terminals and the output signal of the OR

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Gate 784 to one input terminal of an AND gate 786 which has two input terminals AND gate 786 is fed to a conventional electromagnetic converter 790 via an inverter 788.

The RCV signal of the output terminal 6OÖA of the logical On / off receiver circuit βθβ of Fig. 5 is on the second Input terminal of AND gate 78Ο given and to an input terminal of AND gate 782. A Y3 time signal of the Output terminal 612B of the time signal generator 612 of FIG. 5 and 15 are connected to one input terminal of the AND gate 782 given and the Zl time signal of the common terminal 612B of the time signal generator 612 on the back part input terminal R of the bistable multivibrator or flip-flop circuit 792.

The POR signal (energy in reset) of the output terminal 62OA of circle 620 of FIG. 5 is applied to the one input terminal of a three input terminal OR gate 794 given and to the excitation input S of the flip-flop circuit 792. The "indicator reset" signal IRST of output terminal 614B of the address recording circuit 614 of FIG. 11 is applied to the second input terminal of the OR gate 794 and the output signal of this OR gate 794 to the reset input terminal R of the

- 77 '- 709834/0377

Flip-flop circles 776 and 778.

The output signal of the actual output terminal Q of the flip-flop circuit 792 is applied to the one input terminal of an AND gate 796 having two input terminals and the output signal of the wrong output terminal Q of the flip-flop circuit 792 via the output terminal 602A of the call indicator to the logic on / off receiver circuit 606 of FIG. 5 as an FF7 signal. The "bad battery" output signal BBAD of output terminal 618A of the Battery test circuit 6I8 of FIG. 5 is via an inverter 798 given to the other input terminal of AND gate 796 and the output signal of AND gate 796 to the third Input terminal of OR gate 784.

According to FIG. 12, a manually operable reset switch is shown 800 is inserted between earth and the input terminal of a conventional inverter 802 through a resistor 8o4 in parallel with capacitor 806. The input terminal of inverter 802 is also connected to a source of positive DC potential applied, through a resistor 808. The output of the inverter 802 is on the third Input terminal of OR gate 794 given.

In operation, the signals AD1AC and AD2AC are at the end of a successfully received time period from the address

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Recording circle 614 of FIG. 11 on call indicator 602 and are stored by flip-flops 776 and 778. If both are assigned to the recipient Addresses have been received during the same period of time, then the address pick-up signals ADlAC and AD2AC at different times, as previously explained, transmitted to the called party to indicate that two addresses have been received by the portable receiver.

When the ADIAC signal excites flip-flop circuit 776, if the AND gate 78Ο is open, and if finally the receiver is switched off at the end of the time segment, i.e., the RCV signal goes high, then the output of AND gate 78Ο goes high Signal level and thus opens the AND gate 786 via the OR gate 784, whereby the continuous tone signal BUZZ of the 4 is given to the electromagnetic converter 790 via the inverter 788.

When flip-flop 778 is energized by the AD2AC signal, AND gate 782 is opened.

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If the receiver is switched off at the end of the time segment, then the Y3 signal is blanked via the AND gate 782, thus generating a series of pulses at its output terminal, with a repetition frequency of about 4.16 Hertz. These pulse trains at the output terminal of AND gate 782 are passed through OR gate 784 given to AND gate 786 and sample an interrupted BUZZ signal through AND gate 786 and inverter 788 into converter 790. A continuous audible tone emitted by the transducer 79O indicates that the first one has been assigned to the receiver Address has been received, an interrupted or modulated tone against the fact that the second address has been received has been.

When the receiver is first turned on, then the flip-flop circuit 792 is activated by the POR signal of the circle 620 of FIG. 19 and is excited about 0.96 seconds later by the Zl signal of the time signal generator 612 of FIG. 19 is reset. During this time the battery is checked, and if the battery is OK, i.e., when the BBAD signal is at a low signal level, then the output of AND gate 796 goes high and samples the BUZZ signal through the AND gate 786 into transducer 790 for about 1 second.

When an address is received and successfully decrypted and the transducer 790 emits a tone

- 80 709834/0377

SÄ

then the subscriber can manually flip-flop circles Reset 776 and 778 to turn off converter 790 by manually depressing the reset switch 800 can be effected, with which an immediate grounding of the inverter 8θ2 then takes place. This way it becomes a positive Pulse generated at the output terminal of the inverter 8θ2 and

OR through gate 794 to the reset input terminal

both flip-flop circuits 776 and 778 given. Qj, time signal generator;

The timing signal generator 612 of the synchronization and decryption logic circuit 506 of FIG shown individually in the functional block diagram of FIG.

Referring to Fig. 1J> , the CI / 56 frame signal of terminal 608A of the matrix address generator 608 of Fig. 8, which signal occurs at the beginning of each sync capture and sync maintenance pattern, if the receiver is in the correct manner is synchronized, given to the time input terminal C of a standard six-stage binary counter 8IO. The output signals Y1-Y5 of the output Kiemmander first to fifth stages of the counter 8IO are given to a collective output terminal 612A of the time signal generator 612 and from there to the logic on / off receiver circuit

- -81 709834/0377

of Fig. 5 · The Y3 signal of the actual output of third stage of the binary counter 810 is on the collective output terminal 612B and on to the call indicator 602 of FIG.

The Y5 output of the actual output of the fifth stage of the binary counter 810 is passed through an inverter 811 is applied to the time input terminal C of a conventional counter 812 with a divider 8. The output signals Zl, Z2 and ZjJ the actual output terminal of the first through third stages of counter 812 become four on three input terminals Given input terminals having AND gate 8l4. The output signal S6,7 of AND gate 814 is via the collective output terminal 612A of the logic on / off receiver circuit of FIG. 5 and the signal Zl of the first stage of the counter to the collective output terminal 612B and further to the call indicator 602 of FIG. 12 is given.

The signal POR of the output terminal 620A of the

'Energy in reset circuit 620 of FIG. 5 is applied to the given an input terminal of an OR gate 816 having three input terminals and the signals FF21 and ADREC of the Output terminal 606B of the logic on / off receiver circuit of FIG. 5 to the other two input terminals of the OR gate 816. The output signal of the OR gate 816 is applied to the reset input terminal R the counters 8IO and 812 given. That

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Time signal CL2 of the collective input terminal 505 of the synchronization and decryption logic circuit 506 of FIG Fig. 5 is applied to the fourth input terminal of the AND gate 814.

During operation, according to FIG. I3, both the counter 810 as well as the counter 812 were originally reset by the signal POR of the circuit 620 of FIG. 5, by the "address received" signal ADREC of the logic on / off receiver circuit of FIG. 5 and by the On / off receiver logic circuit time reset signal FF21 5. The counter 8IO is thus reset after the synchronization receiving part of an incoming Data signal has been received and is thereupon by the transmission signal CI / 36 of the time recovery circuit 4 at the beginning of each synchronization receive and synchronization maintenance signal SA and SB blanked. The counter 8IO thus counts the number of address signals received.

The Y3 signal of counter 810 produces the interrupted one Signal for the second address tone in the call indicator of Fig. 12 and the signals Y1 - Y5 are set to the logical on / Out receiver circuit 606 of FIG. 14 to generate signals 29 DEC and 30 DEC indicating that the 29th and j50, respectively. Addresses have been received, as will be explained in more detail later in connection with FIG.

709834/0377

The signal Ϋ5 of the counter 810 is to

used to operate the counter 812. The output signals of the counter with divider 8 are through the AND gate 8l4 decoded to generate the pulse S6.7 (6.27 seconds "receiver off?), which is used to generate the Switch off the receiver after the DDATA signal has been decrypted in a selected period of time is. The signal Zl of the counter 812 with divider 8 creates the 0.96 second open gate for the battery test circuit of the call indicator 602, as has already been described above in connection with FIG. 12 '.

8th_. Logical on / off recipient group:

The on / off receiver logic circuit 606 of the synchronization and decryption logic circuit 506 FIG. 5 is shown in detail in FIG. 14, the signal G, indicating that a first address has been received from the output terminal 6IOC of the address evaluator 610 of FIG. 10 to the time input C of a bistable multivibrator or flip-flop circuit 8I8. The excitation control terminal D of the flip-flop circuit is connected to a positive DC voltage potential, and the signal CI / 5 of the input terminal 505 of the synchronization and Decryption logic circuit is applied to the reset input terminal R of the flip-flop circuit 818 given.

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- Wr-

The ADREC output signal (address received) of the actual output terminal of the flip-flop circuit 818 is applied to the excitation input terminal S of a bistable multivibrator or flip-flop circuit 820 and to the collective output terminal 606B of the logic on / off receiver circuit 606 given and forwarded to the time signal generator 612 of Fig. 15. The output signal FP6 of the actual output terminal of the flip-flop circuit 820 indicates that the receiver is in the synchronous state and that a first address has been received. This FF6 signal is applied to the input terminal of an AND gate 822 which has three input terminals and via the collective output terminal 606C of the logic on / off receiver circuit 606 is applied to the address receiving circuit 614 of FIG. The transition signal TRANS of the AND gate 822 is applied to the excitation input terminal S of a bistable multivibrator or flip-flop circuit 824 and via the collective output terminal 606C is applied to the address receiving circuit 614 of FIG.

The output signal of the actual output terminal Q 1 of the flip-flop circuit 824 is applied to the one input terminal of an AND gate 826 which has three input terminals and the output of AND gate 826 to the excitation input terminal S of a bistable multivibrator or flip-flop circuit 828. The "receiver switched on" output

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signal RCV of the wrong output terminal Q of the flip-flop circuit 828 is applied to the collective output terminal 606A.

The RCV signal is also applied to the one input terminal of a two input terminal AND gate 830 given and the output signal of AND gate 830 to the time input terminal C of a bistable multivibrator or flip-flop circuit 832 and further via an inverter 834 to both the time input terminal C of a bistable multivibrator or flip-flop circuit 836 as well as to the collective output terminal 606A, namely as an output signal RCV (receiver switched off).

The excitation control input terminal D of the flip-flop circuit 832 and that of circle 836 are marked with connected to a positive DC voltage potential, and the excitation input terminal S of the flip-flop circuit 832 and of circuit 836 are grounded. The output signals FF8 and FF21 of the actual output terminal Q of the flip-flop circuits 832 and 836 are via the associated output terminals 606C and 606B are applied to the address receiving circuit 614 of FIG and to the timing signal generator 612 of FIG. 13. The signal CL4 of the collective output terminal 505 of the timing recovery circuit 504 of Fig. 3 goes to the reset input terminal R of the two flip-flop circuits 832 and 836 given.

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The Yl time signal of the output terminal 612A

of the timing signal generator 612 of FIG. 13 is on the one Input terminal of an AND gate having five input terminals 838 given and via an inverter 840 to the one Input terminal of an AND gate 842 having five input terminals. The Y2 time signal of the collective output terminal 612A of the time signal generator 612 is applied to the second input terminal of the AND gate 842 and via an inverter 844 the second input terminal of AND gate 838. The signals Y3-Y5 are similarly from the bus terminal 612A of the Time signal generator 612 given to the other input terminals of AND gates 838 and 842.

The 29DEC output signal (29 addresses decoded) of AND gate 838 is applied to one input terminal of AND gate 822 and the 30DEC output signal (30 addresses decrypted) of the AND gate 842 to the input terminal of the AND gate 826. The time signal CL2 of the collective output terminal 505 of the time recovery circuit of FIG. 4 is applied to one input terminal of each of AND gates 822 and 826.

The time signal CLl of the collective input terminal 505 is applied to the one input terminal of an AND gate 846, which has two input terminals, and the output signal of AND gate 846 to reset input terminal R of the flip-flop circuit 820. The signal SYNG of the output terminal 6Ο4Γ

709834/0377

- Rv -

of the up / down counter 6o4 of FIG. 7 is set to the other Input terminal of AND gate 846 given.

The signal POR of the Ausgarigsklemme 62ΟΛ of the "energy in reset" circuit 620 of FIG. 5 is applied to the input terminal of an OR gate 848 having two input terminals and the output of the OR gate 848 to the reset input terminal R of the flip-flop circles 828 and 824. the FF? signal, these are to a 0.96 seconds negative going pulse during the performance of the battery check, from the output terminal 602A of the paging indicator 602 of FIG. 12 to the second input terminal of the aND Gatters 8 ^ 0 given.

In operation, as shown in FIG. 14, the signal G

of the address evaluator 6IO of FIG. 24 the fllp-flop circuit stimulate when a first address signal has been received. The ADREC signal (address received) actuates the flip-flop circuit 820, and the FF6 signal of the FLLp flop circuit 820 offre t the AND gate 822 for the remainder of the time period until the flip-flop circuit 820 is reset by the loss of synchronization what is indicated by the signal SYNG.

When AND gate 838 has a count of 29

decrypted, indicating that all addresses have been received then the transmission digital TRANS takes a high

- 88 7 0 0 Π 3 U i 0 3 7 7

- -88- -

Signal level and triggers the flip-flop circuit 824, whereby the AND gate 826 is opened. When AND gate 842 decrypts a count 30 indicating that it was successful decrypted address signals have been transmitted to the call indicator 602 as previously described is, then the output of AND gate 826 goes high and triggers flip-flop circuit 828, bringing a "receiver off" signal RCV through the AND gate 830 and the inverter 8j54 with a high signal level will.

The RCV signal remains at its high signal level until the signal S6,7 of the timing signal generator 612 of Fig. IjJ resets flip-flop 828, which occurs approximately 6.72 seconds later. The RGV signal is of course during these 6.72 seconds at a low signal level and can be used to power the to receiver circuit 502 of FIG. 3 in any suitable manner during those 6.72 seconds.

The RCV signal energizes flip-flop circuit 836 when the receiver is turned off, i.e. when the RCV signal assumes a high signal level. About 6.72 seconds later, the RCV signal triggers flip-flop circuit 832.

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Shortly after the excitation, the flip-flop circuits 8 ^ 6 and 832 are reset by the CL4 time pulse, and a very short pulse FF21 is thus generated, which is fed to the time signal generator 612 of FIG. 1J> as a reset signal when the Receiver is switched off first. A short pulse (the FF8 signal) will thus arrive approximately 6.72 seconds later on the address recording circuit 614 of FIG. 11 and generate the signal IRST (call indicator reset). The FF7 signal delays the RCV signal until after the battery test, which lasts 0.96 seconds, which delays the supply of energy to the receiver. This delay prevents modulation of the VCO signal in timing recovery circuit 504 of FIG. 4 from any signal during the battery test.

Advantages of the invention

The method and the device according to the invention applied to a paging system emerge from the above detailed description. In this embodiment the invention avoids the problem of delay compensation, as occurs in the simultaneous transmission of the Ringing signal through a plurality of transmitters of a

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Rufgebietes occurs, namely by a pole operation of the transmitter in such a way that they are separated from each other Send time periods.

The occurrence of delay problems in systems with a large number of transformers is avoided by that those transmitters, which transmit in the same time period, are spatially separated from each other, with which then with respect to the overlapping of the port planting patterns no longer occurs. The number of transformers in one Call area can thus be increased considerably in order to avoid the failure of the receivers in blind zones without however, that interference occurs between the transmitters. Frequency offset problems are also avoided because each of the transmitters can transmit on the same carrier frequency without interference.

Through the use of modular units, the call system described can be used if the need changes be expanded. The system also operates with "end-to-end" dialing and with NNX codes. The need and cost of adapting elements to connect the Call system with the existing telephone system and with other existing call systems is also used avoided, and the mode of operation is fail-safe.

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By using conventional microcomputers, the system described can be used for controlling a large number of can be used by subscriber call systems within a single call system for controlling the call systems in different call areas and for connection to existing sound systems.

By using digital technology, analog noise problems are avoided, and physical ones Equipment size is reduced considerably; the portable receivers, for example, can access about the Size of a cigarette pack can be reduced. The capacity of the system is considerably over that the known systems increased; the capacity of a single channel is 60,000 addresses at a call rate of 3 »75 per second and a bit rate of 1,200 bits per second in the voice range. Single addresses or double addresses can be assigned to each recipient.

By using a high Bose Chaudhuri code and the special address evaluation, the probability of the decryption with an 8-bit separator between immediately adjacent addresses and two or fewer error bits assume a probability value of 0.996 for the assumption that the probability

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possibility of accepting another address from 3 χ 10 ~ with a bit error rate of 0.01. For a bit error rate of 0.001, however, the ratio becomes assumption to be incorrectly assumed to be 0.999995 to 3 χ 10 ^.

The likelihood of achieving synchronization within a full second of the data signal, for example a main frame, with a bit error rate of 0.01 is about 0.9 * 1-2 compared to the Probability of incorrect synchronization of 10 ~. -With a bit error rate of 0.001 that is Ratio between the probability of correct synchronization and incorrect synchronization with 0.9995

- "52

to assume 10 ^.

The above explanations explain the effectiveness and usefulness of the method and the device according to the invention applied to a subscriber paging system. However, the invention has a variety of others Possible applications in data transmission and in the control of remote facilities. The invention can thus also be embodied in other embodiments, without deviating from the inventive concept. The embodiments explained above are therefore actual only examples and in no way limiting.

709834/0377

Claims (6)

PATENT CLAIMS ί 1, method for evaluating a digital signal that is associated with predetermined bit rate during successive time periods is transmitted, characterized in that the transmitted digital signal (62) received, the bit error rate between the transmitted and the received digital signal determined at least one of the time segments (T-]) as a function of the Bit error rate detection is selected and the digital signal (62) received in the selected time segment is evaluated. 2. The method of claim 1, wherein the digital signal has a digital address part and a digital synchronization part contains, characterized in that the bit error rate is determined as a function of the synchronization part (SA, SB) and the address part (A ^ -A, q) is evaluated in the selected time segment (T ^) will. 3. Recipient for carrying out the method according to claim 1, characterized by a device (56) for receiving a digital signal which is transmitted at a predetermined bit rate during one after the other of the following time segments (60) is transmitted by circuits (600,604) for evaluating the bit error rate between the transmitted and received digital signal, through dialing circuits (606) for selecting at least one time segment as a function of the evaluated bit error rate and by means of switching circuits (610,614) to evaluate the in the selected time period 709834/0377 received digital signal. 4. Receiver for performing the method according to claim 2, characterized by a device (56) for receiving the transmitted digital signal, by circuits (600, 604, 606) which respond to the synchronization part of the received digital signal and that bit in at least one of the time segments -Determine the error rate of the received digital signal, which is above a predetermined value, by means of circuits (610) for evaluating the address part (A1-A30) of the digital signal which is received in a certain time segment (T ₁ ), which corresponds to the excess determined Bit error rate is selected, by a detector (600) for detecting the synchronization part of the digital signal, by an up-down counter (604,659) which gives an output signal, by circuits (604,606,660) which are connected to the detector and the Output signal of the up-down counter as a function of the determined synchronization part of the change digital signal, by a generator (674) for generating a signal as a function of the output signal of the counter and by selection circuits (606) for selecting a specific time period (T.) as a function of the generator signal. 5. Receiver according to claim 4, characterized by circuits (606,612) which are made by the generator signal and put the receiver out of operation for a period of time that follows the period of reception. 6. The method of claim 1 for decoding a digital 70933 4/0377 Signal, characterized in that the transmitted digital signal received a certain signal depending on the Bit error rate between the transmitted and received digital signal above a predetermined value in at least one of the time segments generated and that received during a time segment selected as a function of the particular signal generated digital signal is evaluated.