DE2265015C2 - Word processing system - Google Patents

Description

The present invention relates to a word processing system according to the preamble of claim 1.

In particular, the invention relates to the possibility of a recorded on a record carrier To print the text in an adjusted form so that the lines on the right edge are aligned with one another. This possibility is very useful for the operator because they record a text regardless of the right margin can.

This option can also be used to change the format of a text while it is being printed be used. To be more precise: During the recording mode, one can, for example, 50 characters recorded in the lines having text, which is then for example 60 characters in the Lines can be printed automatically.

There is a word processing system (US-PS 32 97 124 according to DE-OS 14 36 673) is known in which during of the printing operation, the format of a text is recorded on a tape in advance. The operator selects the new format, and the system automatically limits a "setting range" from a preselected number of characters. If the system in this area has a spatial Character or a character in the form of a hyphen is identified by this System automatically ordered a carriage return. If no spatial / or the shape of a hyphen having characters are found in this area, the printing operation stops and the operator stops puts a hyphen in a suitable place in the word that exceeds the setting range a.

It is clear that this word processing system has the disadvantage that the adjustment of the lines only in the limits of the »setting range« can take place,

as a result, the lines are not printed exactly in line with the right margin. Only in the case where the spatial characters or characters in the form of a hyphen at the beginning of the setting area are found, the text is printed in an adjusted form

From US-PS 35 09 817 is eui line printer became known, the adjusted lines of proportionally spaced characters with Can print with respect to a pre-set right margin, in which a right margin preceding Adjustment range is limited and after loading a line to be printed in a buffer which ends the process when a space is loaded into the adjustment area an adjustment process is carried out which, through successive sub-cycles, selects the last character of the line shifts and a predetermined number of previous characters depending on the Start of the last character in the adjustment area in the memory locations on the right of the memory buffer or into the corresponding places next to the right edge. At the end of such an adjustment process, the printing of the line is carried out. Such a line printer has the disadvantage that an adjustment process rigidly from the previously set right edge and Adjustment range depends and thus is not able to create a multi-cell text with a desired complex preparation in a single automatic operation, with the text Le for example some lines adjusted with reference to a predetermined right margin and others with reference to has another right margin justified because it is necessary for such editing that Stop printing to set the new margin. In addition, such a printer does the Adjustment by changing the positions of the characters only in a right part of the line, usually in one area comparable to the adjustment range. This can result in uneven space of the word in the adjusted line, because the space between words only expands in the right part of the line appears.

From the "IBM Technical Disclosure Bulletin", Vol. 12, No. May 12, 1970, pages 2254 and 2255, is des further an automatic adjustment and printing device known in which the lines to be printed successively read from a magnetic tape and stored in a line buffer memory and at an adjustment logic is activated before the line is printed, which determines the total exclusion value of the stored Line, the amount of additional exclusion needed to adjust the line, and the value calculated by which each inter-word space should be expanded for the purpose of adjustment. Then the Line is printed and as it is pressed, each space code is under control of the adjustment logic expanded. Again, this type of adjustment device, while having the disadvantage of unevenness of the printer according to US-PS 35 09 817 eliminated, unable to during playback and pressing a text change the right one Edge with respect to which the adjustment is carried out line by line when the Printing is not interrupted for the purpose of changing the right margin itself.

In addition, in these two machines belonging to the state of the art, those for adjustment The necessary calculations are all carried out immediately before printing, which makes the entire printing process is slowed down.

It is therefore the technical object of the present invention to provide a word processing device create that is able to predetermine different lines of the same text with reference to different ones adjust right margins with high speed printing. According to the invention, this technical problem is solved by the word processing system specified in claim 1 solved.

Developments of the invention are given in the subclaims.

The invention is explained in more detail below with the aid of an exemplary embodiment shown in the drawing described. Show it:

Fig. 1 is a block diagram of a printing system according to the invention;

Fig. 2 is a block diagram of the central unit of the system of Fig. 1;

FIG. 3 is a block diagram of a timing circuit of FIG Central unit according to Fig. 2;

Fig. 4 is a diagram of the circuit according to Fig. 3 generated clock signals;

5 shows a circuit for generating the working states the central unit of Figure 2;

6 to 12 which correspond to the same number of work states of the central unit according to FIG Command circuits;

13 shows an input circuit of the central unit according to FIG. 2;

FIG. 14 is a block diagram of a control unit for the input and output device of the system according to FIG Fig. 1;

15 shows a piece of magnetic tape of the system according to FIG. 1;

Fig. 16 shows a detail of the magnetic tape of Fig. 15;

Fig. 17 is a block diagram of the control unit of the apparatus for recording and reading the magnetic tape the system of Fig. 1;

Fig. 18 is a flow chart showing the operation of the control unit of Fig. 17;

19 and 20 are flow charts showing the entry of commands into the system of FIG. 1;

Fig. 21 is a flow chart relating to recording of text;

Fig. 22 is a text relating to printing Flow chart;

Figure 23 is a flow chart relating to the left or right justification of a line of text.

The automatic printing system according to the invention contains a central unit 5 (Fig. 1) with a processing device 39 and a core memory 42. The central unit 5 is connected to a group of peripheral devices connected, to which a typewriter 6, bo a magnetic tape memory 7 and an operating keypad 8 belong. The typewriter 6 is connected to the central unit 5 via its own control device 9, the commands and data coming from the typewriter 6 in a suitable form in the Zentraleinb5 Heil 5 and vice versa.

The typewriter 6 is of known type and has an input / output device 12, which from the Central unit encode 5 characters and the

relevant commands transmitted into the typewriter and can be of any known type.

With the help of the typewriter 6 it is possible both to enter texts and to store them in the memory 42der Central unit 5 to transfer as well as the one with I lilfeder automatic printing system to select the processing operations to be carried out and, as below will be explained in more detail below to print the processed texts in their final form.

The magnetic tape memory 7 is also connected to the central unit 5 via its own control device 10. The memory 7 can contain all the commands for controlling the printing system, on a case-by-case basis are selected and transferred to the memory 42 of the central unit 5, and the magnetic ι Can contain recording of the texts that are entered via the typewriter 6. These lexte can be removed from case to case by the operator and entered into the central unit 5 to be printed by the typewriter 6 :.

The control keypad 8 is connected to the central unit 5 via a further control device 11 and contains a plurality of keys, each assigned to a particular group of commands of the system; are. As a result, it is possible with the help of the keys to select the appropriate group of commands, without using the typewriter 6.

In a first period of time, the text to be processed is entered on the typewriter 6, at the same time the printing of the actual text and its transmission via the input device 12 and the Control device 9 in the memory 42 of the central unit 5 causes. From here the text is transferred to the control unit 10 is transferred to the tape memory 7 to be recorded. Now the operator can do this Text both by adding or removing lines or paragraphs, and by changing the length of the Correct or modify lines and correcting spelling mistakes. To do these operations: cause the operator selects the typewriter 6 or the control keypad 8 Command group that corresponds to the intended change.

Each command group is made up of an example: four-letter label so that it can be easily identified. As a result of this During the process, the selected command group is transferred from the tape memory 7 to the memory 42 of the central unit 5 transferred to take effect. As a result, the central processing unit executing the selected commands processes 5 the text and then transfers it to the oäPiuSpCiCiiCr /. Aiii uiCSC WciSC Will u6r TcXt in uci desired shape is recorded to be then printed by the typewriter 6. ;

The processes described above are carried out by the central processing unit 5 by executing a command sequence BP which is stored in the tape memory 7.

The central unit 5 contains a timing circuit or a timer 20 (FIG. 2) which can supply the clock signals necessary for the flow of data within the actual central unit 5. The timer 20 essentially consists of an oscillator 21 (FIG. 3). which delivers a signal C with a frequency of <6 MHz (Fig. 4). This signal acts on a shift register 22 (FIG. 3) formed from six flip-flop circuits F1 to F6. that carries out its entire work cycle in twelve line spaces, each with a duration of 2 ys. The output signals of the flip-flop circuits FX to Fb are shown in FIG. 4 and are each denoted by the reference symbols TX to F6. In order to obtain the signals required for time control, the outputs of the six flip-flop circuits FX to F 6 are coupled to one another via gate circuits, the outputs of which supply the clock signals for the central unit 5.

For example, to obtain a signal 7S is the Flip-flop circuitFl with the flip-flop circuit F3 coupled. More precisely, the direct output of the flip-flop circuit 3 is provided via an inverter 23 (FIG. 3) connected to an output of an AND gate 24, while on the other hand the output of the flip-flop circuit Fl is applied to the other input of the gate 24. The output 75 'of the gate 24 is located therefore to level "1" when the outputs of the flip-flop circuit cn F1 and F3 have the values 1 and 0, respectively. On the other hand, he is on in the other cases Level »0«. It is thus clear that by appropriately coupling the outputs of the other flip-flop circuits Fl to F6 all other clock signals according to Fig. 4 can be achieved.

The central unit 5 contains a register 30 (FIG. 2) with a length of three bits, which is composed of three flip-flop soundings. The register 30 is provided with three F.ingängen 30a, 30 b and 3or, each of the typewriter 6 (Fig. 1), the externcn memory 7 or the Bcdienungstastenfeld 8 are connected. The register 30 (Fig. 2) is also provided mitdrci Ausgängcn31 a, 31 /> und31 c, which form a same number of inputs of a logic circuit 31 to a register 32 having a length of eight bits the code of 8- Can enter bit character that indicates the peripheral device, which the corresponding input 30a. 30 b or 30 c of register 30 has excited.

More precisely, during the execution of a command by the central unit in Heil 5, a peripheral device 6, 7 or 8 can interrupt this command in order to transmit data or commands to the central unit 5. For this purpose, the peripheral device 6, 7 or 8 then energizes the corresponding input 30 a, 30 6 or 30 c of the register 30 and thus the input 31 β, 31 b or 31 c of the logic circuit 31, which the corresponding X bit Drawing supplies.

Furthermore, can select if two peripherals that of the respective inputs 31a, 31b and 31 r at the same time erregen.die logic circuit 31 from the two peripheral devices that has towards the other priority and in accordance with a given riiuiiiäisbefcni as an output signal a corresponding to this peripheral device link of eight bits provides. For this purpose, the logic circuit 31 consists essentially of a logic circuit with three inputs and eight outputs. The voltage values of the eight outputs optionally form the linkage of eight bits corresponding to each of the inputs 30 a, 306 and 30 c.

The three inputs 31 a, 31 b and 31 c are also connected to the logic circuit 31 in such a way that each of the inputs can only cause the corresponding combination of eight bits in a manner known per se if the input with the higher priority is set to "O" Level is. For example, the input 31 can b as an output from the logical circuit 31, its associated combination of eight bits only exciter

gen when the input 31 α is at the "O" level. This obviously has the consequence that input 31 a has priority over input 31 b. The same also applies to the input 31 c in comparison to the input 31 b.

As already stated, the outputs of the logic circuit 31 form the same number of inputs for the register 32. The outputs of the register 32 are connected to a logic reset circuit 34 via a channel 33. The circuit 34 has three outputs 34 a, 34 b and 34 c, which are each assigned to a combination of eight bits transmitted from the register 32 via the channel 33 into the circuit, so that the logic reset circuit 34 actuates the output from case to case which corresponds to the combination of eight bits present on the channel 33.

Each of the outputs 34 a, 34 b and 34 c is connected to a corresponding reset circuit for the three flip-flop circuits forming the register 30, so that when one of these outputs is energized, the corresponding flip-flop circuit of the register 30 is set to zero. In this way, if two signals are present at the same time as input signals for register 30, for example at inputs 30 α and 30 b, the logic circuit 31 enters an 8-bit character in register 32, which the peripheral device with higher Priority rank corresponds to the typewriter 6 assigned to the input 31 a. Consequently, this character is transmitted via the channel 33 to the logic circuit 34 which only excites the output 34 a corresponding to the typewriter 6. The flip-flop circuit of the register 30 corresponding to the peripheral device with a higher priority rank, ie the flip-flop circuit connected to the input 30a, is consequently set to zero. In this way, remains after the connected to the upper-level peripheral device operations have been performed, the peripheral device corresponding with a lower priority level flip-flop circuit energizes the register 30, that is, b is connected to the input 30 of flip-flop circuit. As a result, the 8-bit character corresponding to it is entered into the register 32, whereupon the processes described above are repeated so that the peripheral devices are always taken into account by the central unit 5 in accordance with the predetermined priority order.

The outputs of register 32 are also connected to a further register 41 via a channel 40, which completely coincides with the register 32 and forms an input register of the core memory 42. That Characters stored in register 41 are transferred to a counting circuit 44 via a channel 43, whose mode of operation is known and the characters entered into them via channel 43 are increased by one Unity can increase.

The outputs of the counting circuit 44 are in turn connected to the inputs of the register 32. To this The content of the input register 41 is increased by one unit as soon as on via the channel 40 Word of eight bits is entered. As will be explained in more detail below, this enables the Cells of memory 42 in which the data or instructions of the program under development are contained, are accessible one after the other.

The bits contained in the input register 41 are also used in an address decoding circuit 45 of the memory 42 transferred. The address decoding circuit 45 can based on the combination of the in 8 bits present in register 41 select one of the cores of memory 42. The core memory 42 has has a storage capacity of 1024 eight-bit characters and Ί is in four zones called pages, each with one Storage capacity divided by 256 characters. Each side is identified by a code number 0, 1, 2 and 3. Therefore, ten bits are necessary to recognize a cell of the memory 42, namely two for

ι »Detection of the side and eight to detect a cell in the area of the determined side.

The memory 42 contains eight identical core matrices arranged in eight planes. Every core matrix is off thirty-two rows and thirty-two columns for

i "> formed a total of 1024 cores, so that each matrix has a storage capacity of 1024 bits. As is known, go through each core of memory 42 four conductors through: a write or blocking conductor, a read or sensing conductor and two addressing conductors. in the

2 <i individually, each blocking or scanning conductor runs in Row through all the cores of each level so that there are consequently eight sample and eight barred lines. The two Addressing conductors, on the other hand, are arranged at right angles to one another and intersect at a corresponding one Core. Each addressing conductor runs in series through all in the same row and column of the cores arranged in eight matrices. More precisely, those of the first row and the first column run one Addressing conductor assigned to the core matrix in series

i «through all the kernels of the eight levels arranged in the first row and in the first column of each matrix. As a result, there are a total of thirty-two addressing conductor pairs.
The decoding circuit 45 can be a logic circuit of any known type and is therefore not described in detail. The decoding circuit 45 has in particular eight input conductors to which the signals present in the input register 41 are applied, and thirty-two outputs which are connected in sequence to the thirty-two addressing conductor pairs. Each core is selected when the two addressing conductors crossing in it are excited at the same time. Each addressing conductor pair is excited in accordance with a special combination of the signals present on the eight input conductors of the decoding circuit 45 and thus selects a corresponding group of eight cores which are brought into the 0 state. In order to feed the information coming from one of the peripheral devices 6, 7, 8 into a core of the memory 42 selected in this way, these peripheral devices are connected via a channel 46 formed from eight conductors to the input of a logical memory input circuit 47 to be described in more detail below. The output of this logic circuit 47 is formed from eight conductors forming a transmission channel 48. These conductors are connected to the corresponding blocking conductors of each of the eight arrays of memory 42.

bo Via the blocking conductors that correspond to those cores into which a 0 is to be written, a current is supplied in such a way that no switching or change of state of the selected core is effected, while the conductors corresponding to those cores in which a 1 is written is to be, the change of state is brought about in a known manner.
Accordingly, the logic circuit 47 leads to

Reading the information recorded in the cores to the addressing conductorpaur one to the one when writing supplied current to the opposite current, so that switching takes place only in the cores in which a 0 was recorded. As a result, an induced voltage is only present in the scanning conductors, passing through a core in which a 0 was recorded. The eight scan lines are through one Output channel 49 of memory 42 to an output register 50 connected. The one read into the memory 42 and recorded in the output memory 50 Information can have different meanings. Namely, it can rely on the peripheral devices 6, 7, 8 data to be transmitted or to memory addresses to be used afterwards or to data that are temporarily are to be stored in order to then be compared with other data read into the memory 42 or to be transferred to other addresses of the memory 42, or to refer to codes of the commands, which are to be executed by the central unit 5 during the execution of an instruction sequence.

For this purpose, the register 50 is connected to the peripheral devices via a channel 51, so that the in the Memory 42 to transfer read-in data into these devices. Register 50 is also about a Channel 55 is connected to register 41 in order to enter the memory address to be used next. The register 50 is also connected via a channel 56 to an eight-bit register 57 in order to store the enter data to be saved temporarily. Finally, the register 50 is on via a channel 58 another eight-bit register 59 is connected in order to enter the codes of the commands therein. The temporarily Data to be stored in the Rcgister57 can also be obtained from the register 32 as well as from the register 50 come. For this purpose, the output of the register 32 is connected to the input of the register via a channel 66 57 connected.

The register 59 is connected via an output channel 60 to a decoding circuit 62 which has thirteen outputs 62 to 62 _n , the same number as the number of instructions used by the central processing unit 5. The decoding circuit 62 is a logic circuit of the type described with reference to the circuit 31.

As will be explained in more detail below, each instruction is identified by an eight-bit code. the first four bits of the code distinguish the commands from one another, while the second four bits are the so-called Form "address change", the meaning of which is explained in more detail below.

The decoder circuit 62 energizes the one of the thirteen output conductors which corresponds to the command expressed by the four-bit code present on the channel 60. The outputs 62, to 62, _{3 of} the decoding circuit 62 control a logic control device 63, which supplies a series of commands, denoted below by the symbols COM 01 ... COMTl , in a manner to be described in due course, which the transmission of the data within the Control central unit 5. In detail, these commands activate the gate circuits shown by a circle in FIG. 2 and thereby enable the information to be transmitted along the transmission channel in which these circuits are inserted, from one register to the other or from the memory 42 (FIG. 2 ) into one of the registers 50, 57, 59 connected to it and thus execute the respective commands.

In Fig. 2, its special command is given next to each gate circuit. For example, the command COM 01 activates a gate circuit 64 which allows the contents of the register 32 to be transferred to the register 41 via the channel 40.

^r ) The register 59 is divided into two parts, each formed from four clip-flop circuits. The first four bits of the code of the commands, which determine the type of command, are fed to the first four flip-flop circuits. The outputs from these flip-flops

ίο are combined in channel 60. The second four flip-flop circuits of the register 59 are supplied with the bits forming the address change. the Outputs from these flip-flop circuits are combined in a further channel 61.

r> The bits of the address change have accordingly the command type has different meanings. More precisely, the bits of the address change can be a of the peripheral devices 6, 7, 8, to which an instruction is directed, or one designated by the instruction

2 (i determine the pressed command or the memory page, to which a given address belongs. In addition, the bits of the address change can indicate that a Address or a data value is to be increased by one unit.

In the first-mentioned case, the bits of the address change are present on a channel 64 'and are used by a decoding circuit 65 of the same type as circuit 62, which controls the peripheral device on the basis of one of its three outputs 65 ₁ , 65 _{2, 65 3} exciting

Selects the content of the address change. In this way the decoding circuit connects across the channel 51 the register 50 with the selected peripheral device for transferring the data between the central unit 5 and the selected peripheral device.

r> If the bits of the address change indicate a memory page, the gate circuit 121 is activated by the logic control device 63 actuated, as a result of which the first two bits of the address change via a Channel 70 are fed to a register 71 with a length of two bits, which in this way contains the address the page of memory 42 stores. The content of the register 71 and that of the input register 41 form a complete memory address, which, as already discussed, is made up of ten bits that represent the 1024 cells of the Determine memory 42. The content from registers 71 and 41 can be changed or changed independently of one another since the bits read separately into the two registers 59 and 32 are assigned to registers 71, 41 are supplied via the respective channels 70 and 40. This possibility allows, for example, the in one and the same page of the memory containing data while keeping the content of the register 71 constant to address. As will be explained in more detail below, the number of the page can be accessed via a channel 72 can also be fed directly into the logic decoding circuit 45. The logical control device 63 can also be transferred from the register 59 via a channel 75 Address change bits can be set. A conductor 76 also connects the logic Circuit 31 with the logic control device 63. In this way, the logic circuit 31 transmits each time if a peripheral device 6,7,8 is one of the flip-flop circuits of the register 30 exciting interrupt causes a signal on the conductor 76. This Signal is then used to control logic device 63 to generate the actual interrupt to operate the corresponding commands.

The operating state in which the central unit 5 is during the execution of a command is called the "machine country". Each machine state has a duration of 2 ys and is determined by the clock signal 7S, the course of which is shown in FIG. In each machine state determined in this way, the logic control unit 63 (FIG. 2) generates a series of commands as a function of the signals present at its inputs, which, as already mentioned, are characteristic of the individual commands. More precisely, the commands are executed by the central processing unit 5 through the successive sequence of a plurality of machine states. In each state, the operations to be carried out by the central processing unit 5 are determined. For this purpose, the logic control device 63 contains two blocks 63 ^ i and 63 B. The block 63 A , shown in detail in FIG through the decoding circuit 62 transmitted input signals. In FIG. 6 to 12 illustrated block 63 B generated for each machine state a sequence of relating to the selected instruction commands to COMOl Comil.

In detail, the block 63 A has as inputs the conductors 62, -62, 3 (FIG. 2) coming from the decoding circuit 62, each of which is assigned to one of the thirteen commands. In addition, the block 63 A has as an input the conductors 75 and 76 coming from the second row of flip-flop circuits of the register 59 and from the register31 as well as a conductor 100 coming from the logic memory input circuit 47 corresponding output MA-MG r> of a series of flip-flop circuits FA-FG belonging to the block 63 A. Since each machine state has a duration of 2 as , each of the flip-flop circuits FA-FG must remain energized for a period of 2 as. To achieve this, A 63, the clock signal 7S is directed into the block, which excites the inputs of the flip-flop circuits FA-FG via the AND circuits DA-DG. The outputs MA-MG of the flip-flop circuits FA-FG set the block 63 B in such a way that the commands assigned to the individual instructions are generated in each machine state. In detail, each circuit shown in FIGS. 6 to 12, of which the block 63 B is composed, is excited by a corresponding signal MA-MG and furthermore set by the same input signals as for the block 63 A.

Since the need for time control of a number of the commands COM 01 -COM 11 arises in the area of a machine state, clock signals 77?, 77 and TM (FIG. 4) generated by the time control circuit 20 (FIG. 3) are also assigned to the circuits of block 63 B assigned as input

The commands COM 01 -COM 11 generated by block 635 of logic control device 63 also act on logic memory input circuit 47 (FIG. 2) of memory 42. This logic circuit 47 also has two channels 80 and 81 as inputs, each with a length of eight bits. The channel 80 comes from the output register 50, while the channel 81 comes from the register 57. The logic circuit 47 also has as input a channel 82 with two bits, which comes from the register 71 ". The channels 80, 81 and 82 transmit the contents of the registers 50, 57 and 71 in the logic input circuit 47 so that they can be processed therein in accordance with the corresponding commands COM 01 -COM 11 generated by the logic controller 63. The results of these by a combination of eight bits The processing operations shown are supplied via the output code 48 to the cell of the memory 42 determined by the address contained in the address register 41.

More precisely, the logical memory input circuit 47 simply transfers the data present at its inputs to the output channel 48 when one of the commands COM 03, COM 14 and COM 17 acts on the circuit. The command COM 03 acts on a gate circuit 85 (FIG. 13), as a result of which the bits that come from the register 50 and are present on the channel 80 are transferred to the channel 48. The commands COM 14 and COM 17 acting on the two gate systems 86 and 87 determine the transmission of the bits present in each case on channels 81 and 46 to output channel 48. In this way, those present in register 57 (FIG. 2) and those from one of the peripheral devices 6, 7, 8 incoming characters into the memory 42 without being processed.

On the other hand, when the command COM 06 acts on the logic circuit 47, the character present on the input channel 80 from a counting circuit 88 (FIG. 13) is increased by one unit and then transmitted to the output channel 48 via a gate circuit 89. When the command COM 19 is generated, the eight bits present on the input channel 81 are passed into an exchange circuit 90 which exchanges the first four bits with the second four in a manner known per se. The new character obtained in this way is transmitted to the output channel 48 via a gate circuit 91.

The logic circuit 47 (FIG. 2) can also compare the content of the output register 50 with the content of the register 57. More precisely, if the command COM 20 is present, a comparison circuit 98 known per se (FIG. 13) is actuated. comparing the contents of registers 50 and 57 coming from the registers via channels 80 and 81 with one another. The comparison made by the comparison circuit 98 is indicative of the equality or inequality of the characters present in the two registers 50 and 57. The result of this comparison is represented by a bit generated by the comparison circuit 98 and supplied via a conductor 95. This bit is equal to 1 if the characters present in the two registers 50 and 57 are the same, and equal to 0 if they are different.

The bit E is read into a register 96 (FIG. 2) via the conductor 95. The content of the register 96 can be read into another register 97 which corresponds to it when the command COM 26 is generated. Conversely, the COM 13 command creates the reverse transmission. The bit E can also condition the operation of the logic control device 63 via the conductor 100 during the execution of special commands.

In addition, if the command COM 21 is present, an AND circuit 92 (FIG. 13) carries out the logical AND operation between the eight bits present in each case on the input channels 80 and 81. The result of this process is

Bit character is formed, which is transmitted to the output channel 48 via a gate circuit 93. If, on the other hand, the command COM 22 is present, a circuit 94 carries out the logical F. exclusive-OR operation between the bits present on the input channels 80 and 81, respectively. As is well known, the result of this logical operation is 1 if both bits are different and 0 if both bits are the same. This result is then transmitted to the output channel 48 via a gate circuit 99.

As already mentioned, all of the command groups setting the operation of the central unit 5 are recorded in the magnetic tape memory 7 (FIG. 1) in a link to be described in more detail below. So that these command groups can be executed by the central unit 5, they have to be transferred individually from this memory 7 to the core memory 42 (FIG. 2). The commands which form the selected group are then executed in sequence by the central processing unit. To transfer the command groups from the magnetic memory 7 to the core memory 42 , a special command group known as the "initial command group" is used. This command group is composed of 64 characters and is also recorded in the external memory 7 at two positions predetermined by the magnetic tape.

The control unit 10 of the memory 7 can recognize the two addresses in which the initial command group is recorded in a manner which will be described in more detail below. If these addresses are recognized, the control unit initiates the transmission of the »initial command group« in the following way. The central processing unit 5 is normally in the idle state, so that all of its registers are set to zero. When the line control device 20 (FIG. 2) generates the signal TS , the output MA of the flip-flop circuit FA is brought to the level 1 via the AND circuit DA (FIG. 5), so that the central unit 5 is in the state A is brought.

Then an AND circuit 112 (FIG. 6) of the block 633 energized at the time 75, which generates the command COMOL, which opens the gate circuit 64 (FIG. 2), causes the transfer of the contents of the register 32 to the register 41 and thus to the address decoding circuit 45. In addition, the output MA directly generates the command COM 18 (FIG. 16), which transfers the content of the register 71 to the circuit 45 by opening the gate circuit 113 (FIG. 2). The address 00000000 of the memory 42 - since all registers of the central unit 5 are set to zero - - is then read into the decoding circuit 45. The content of the corresponding cell is now transferred to the output register 50.

In the meantime, the control device 10 of the magnetic tape storage device 7 already has what is to be transmitted to the central unit 5 Characters selected and inserted into the input channel in a manner to be described in more detail below 46 entered.

An AND circuit 114 (Fig. 6) of the block 63 5 in turn generates a command COM 17 which opens the gate circuit 87 (Fig. 13) of the circuit 47 and the transmission of the first character present on the channel 46 from the tape memory 7 in causes the cell of the core memory 42, the address of which is indicated by the decoding circuit 45.

At the time following the time period TS /.V (Fig. 4), an AND circuit 115 (I "ig. 6) of block 63 B generates the command COM 04, which opens a gate circuit 116 (Fig. 2) and the contents of the register increased by one unit from the counter circuit 44

41 is transferred to register 32 . In this way, the link 00000001 is read into the register, so that the address of the memory 42 increases.

Then the central unit 5 controls the operation of the control device 10 of the memory 7 so that it is in the Memory 42 selects the next character to be entered

in and into the channel 46. Then, the same operations as described above are repeated so that the following information is recorded in the cell 000,000,000 of the memory 42 . In this way, the sixty-four characters of the initial command group are recorded in the first sixty-four cells of the memory 42. Since each machine state has a duration of 2 \ xs , the entire transmission of the initial command group has a duration of 128 \ ls.

If the content of register 32 has the binary value 64

2 (i reached, the flip-flop circuit with the place value 64 of the register 32 assumes the value 1, so that it generates a signal R 64 which excites an AND circuit 120 (FIG. 6) of the block 63 £. The AND circuit 120 then generates a signal RBT, which is a flip-flop

2> circuit 35 (FIG. 2) resets so that its output assumes the value 0. At this point in time, the register 32 is set to zero by a signal Λ 4 generated by an AND circuit 121 (FIG. 6) of the block 63 B , since the output signal BT of the flip-flop switch

j (i ment is zero. At this point in time, the result is thus achieved that all the registers of the central processing unit 5 (FIG. 2) are set to zero and that the initial instruction group is recorded in the core memory 42. This group contains the instructions which the can load subsequent commands into the memory 42.

All subsequent commands begin with state A. For these commands, however, the flip-flop circuit 35 is deleted, ie its output BT has the value 0. If the commands COM 01 and COM 18

m, (Fig. 6) are generated again, the address of the cell of the memory 42 recorded in the registers 32 and 71 is transferred to the decoding circuit 45 (Fig. 2). The content of this cell is thereby read and then transferred to the output register 50.

As a result, the memory is read when BT = 0

42 instead.

Since reading the core memory 42 is known to destroy information, the information removed from the selected memory cell must be rewritten. For this purpose, an AND circuit 123 of block 63 B (FIG. 6) excited by the signal BT generates the command COM 03, which closes the gate circuit 85 (FIG. 13) of the logic circuit 47 and now the contents of the output register 50 (FIG. 2) into the same cell of the memory 42 in which it was stored at the time TR. The command COM 04 in turn transfers the content of register 41, increased by one unit, to register 32.

An AND circuit 122 of block 63 B (FIG. 6), controlled via an inverter by signal BT, now generates command COM 05 at time TR following time TS (FIG. 4). This command which opens the gate circuit 124 (FIG. 2) is transmitted

hi the contents of register 50 representing the first character of the command into register 59, so that during state A the first character of the command is read.

Now an AND circuit 124 of block 63 A, also controlled by an inverter (Fig. 5) by the signal ßrgesteuiert the flip-fiop circuit FB at the time TS via the AND circuit DB, so that the output MB of this flip- Flop circuit is brought to level 1. At the same time, the flip-flop circuit FA is reset, as a result of which the central unit 5 changes from state A to state B.

During state B , the commands COMOL, COMIS and COMVi common to all instructions are generated, which, as already mentioned, transfer the content of the cell of the memory 42 determined by the content of the register 32 to the output register 50 and the subsequent writing of this content into the same Effect cell of the memory 42. These operations in the course of state B produce the reading of the second character of the instruction, since the address transferred to register 32 has been increased by one unit during the course of state A.

During state B will be produced on the individual instructions relating commands on the basis of the contents of the register 59 by the block 63 B as well, which contains the code of the command. The first four bits of this code are transmitted via channel 60 to decoder circuit 62 which energizes the output corresponding to the command expressed by the four input bits. Will be discussed in more detail below, this output will remain energized throughout the entire command for execution of the actual time required, so that it causes the generation of commands by the logic control unit 63 in the course of the machine states generated by the block 63 A.

The execution of the individual commands by the central unit 5 will now be described. There are thirteen instructions are provided for running any program and they can be made up of two or more three characters of eight bits each can be formed. The first character of each command is used to identify the actual command and has the format:

60 bl 62 63

64 65 66 bl.

The first four bits 60-63 represent the code of the Command, while the second four bits 64-67 represent the address change. The commands are in as regards the number of characters from which they are formed, of essentially two types.

The commands of the first kind are composed of three characters, the first of which is the command determines, while the second and third characters are the addresses of the cells of the core memory 42 determine on the content of which the actual command is to operate. The content of these cells is called an operand designated. In detail, the operand whose address is represented by the second character of the command is determined as the first operand and the operand whose address is determined by the third character of the command is designated as the second operand.

The instructions of the second type are composed of two characters wi, of which the first characterizes the command, while the second character defines the address of the cell of the operand in the memory 42. The commands of the second type vverdene, referred to as external commands as they, as nachslchend more detail erläu- b ^r, tert, the transmission of commands or information from the central unit 5 in one of the connected to it peripherals 6, 7, 8, or vice versa enable.

The thirteen instructions are divided into four with respect to the machine states necessary for their execution Groups, which are described in detail below.

The first group of commands includes the commands which are executed by the central unit 5 with the aid of the sequence of the five states A, B, C, D, E. The time required for their execution is therefore 10 μ-s.

These commands are: Transfer (TRA) Exchange (SCA), Compare (CFR), Logical Product (AND) Exclusive-OR (EX OR), Free Transfer ('/ KL) and are to be split up using Tables I and II 27 and 28 are described separately in their details below.

1. Transmission (TRA)

The transfer command identified by the code 1000 causes the transfer of the first operand from the address given by the second character of the command to the address given by the third character specific address. As previously mentioned, the address of the cells of memory 42 is such that each memory cell by the number of the page and by the number of the cell in this page. In reality the commands are structured in such a way that all addresses refer to the commands of a single program referring operands in one and the same page of memory called the "current page" lie. In addition, as will be explained in more detail below, during the execution of a program Reference can be made to operands or instructions whose address belongs to »Page 0«. Therefore an operand or an instruction can either belong to the "current page" or to the "page 0".

The code relating to the memory page to which the operands of the instructions belong is supplied with bits b 4 and b 6 of the address change in the following manner. If bit 64 =!, The memory cell specified by the second character of the command (address of the first operand) belongs to the current page; if bit b 4 = 0, the memory cell belongs to page 0. If bit b 6 = 1, the memory cell specified by the third character (address of the second operand) belongs to the current page; if 6 6 = 0, it belongs to page 0.

During the execution of a program it may also be necessary after the execution of a command increase the memory address of the two operands by one unit or not. This possibility is expressed by the value assumed by bits 6 5 and 6 6. When bit 65 = 1, becomes the address of the first operand is increased by one unit after the instruction has been executed; if 6 5 = 0, remains them unchanged. The same occurs with the address of the second operand if 6 7 = 1 or 6 7 respectively = 0.

As already mentioned, the code of the instruction TRA is read in the course of the state A and supplied to the decoding circuit 62 via the register 59 (FIG. 2). During state B , this circuit decodes the code of the command, while commands COMOL, COM 18 and COM 03 are generated, which read the second character of the command, ie the address of the first operand. According to the code of this command, the decoder circuit 62 energizes the output 62, (FIGS. 2 and 7) and thus the

Output of an OR circuit 130 (FIG. 7) of block 635.

If bit 6 5 of the address change of the command has the value 1, the second character of the command accepted in the output register 50 (FIG. 2), increased by one unit, must be rewritten into the memory. In this case, the inputs of the AND circuit 131 (FIG. 7) of the block 635 are all at the level 1, so that the circuit 131 generates the command COM 06. This command opens the gate circuit 89 (FIG. 13) of the storage circuit 47, as a result of which the character contained in the register 50 is fed via the input channel 80 to the counting circuit 88, which increases it by one unit; it is then transferred to memory 42 via output channel 48.

On the other hand, when bit Z? 5 of the Adiesseii change is zero, the output of AND circuit 131 (Fig. 7) is at zero level, as a result of which command COA / 06 is not generated. In the course of state 5, since a gate circuit 300 of block 635 is now energized, command COM 04 is generated at time TR and opens gate circuit 116 (FIG. 2), which, as already discussed, the transmission of the Register 41 taken over and caused by the counter circuit 44 increased by one unit address in the register 32. At the same time 77? (Fig. 4) the output of a further AND circuit 132 (Fig. 7) of block 635 is energized, as a result of which the command COM 15 is generated. This command jo causes the gate circuit 146 '(FIG. 2) to be energized, which causes the contents of the register 50 to be transferred to the register 57.

For this reason, the second operand representing the address of the first operand is read during state 5 Character of the instruction has been carried out and this address has then been transferred to register 57. Unless that Bit 65 is equal to 1, this address is also rewritten into the memory, increased by one unit been.

The transition of the central unit 5 to state C now takes place. For this purpose, the outputs 62 ₇ , 62m, <> 2 _n and 62.3 (FIG. 5) of the decoding circuit 62 are all at level 0, since only the 4-> output 62 corresponding to the command TRA , is excited. Via the inverter circuit 134, these outputs excite the corresponding inputs of an AND circuit 133 of block 63/1. In addition, since the output 62 _{6 of} the circuit 62 is also at zero level, the input 136 of an OR circuit 137 of the block 63/4 is excited via an inverter 135. In this way, the AND circuit 133 of block 63/1 is actuated, which in turn actuates the input 138 of a further AND circuit 139 of block 63/1. Since the other input of this AND circuit 139 is connected to the output MB of the flip-flop circuit FB , the AND circuit DC is excited at the time 72?, As a result of which the flip-flop circuit FC has the output MC sets the level 1. At the same time, the AND circuit DC resets the flip-ω-flop circuit FC to zero, as a result of which the central processing unit 5 thus changes from the state B to the state C.

The state Γ is used to read the first operand. This is because the AND μ circuit 140 (FIG. 8) of the block 636 generates the command COMIQ at the time TS. This command, which opens the gate circuit 114 (FIG. 2) of the channel 55, causes the transfer of the address of the first operand from the register 50 to the input register 14.

If the address of the first operand to the current page of the register 42 is needed, since the bit 64 of the address change of the instruction TRA has the value 1, the input 142 of the AND circuit 143 (FIG. 8) is energized. The input 144 of the circuit 143 is also excited via an inverter, since the output 62 1 of the decoding circuit 62 is at zero level. The AND circuit 143 consequently generates the command COM 18 which, as already mentioned, causes the contents of the page register 71 (FIG. 2) to be transferred to the address decoding circuit 45.

On the other hand, if bit 64 is at the zero level, the command COMIS is not generated and no bit is read into the address decoding circuit 45, so that the selected memory page is page 0.

At the same time, the content of the memory cell selected by the address of the first operand is read and the content is transferred to the output register 50. In addition, at the time of 77? (Fig. 4) an AND circuit 145 (Fig. 8) is opened so that the command COM 15 is generated. This command, which opens the gate circuit 146 '(FIG. 2), causes the first operand to be transferred from the register 50 to the register 57. Finally, the command COM 03 is generated by a further AND circuit 146 (FIG. 8) and controls the writing the same information that has been extracted into the cell of the memory 42. In this way, in state C, the reading of the first operand is carried out, which is rewritten in the row and transferred to the register 57.

The transition of the central unit 5 to state D is then effected. Since the output 621 of the decoding circuit 62 has the value 1, an OR circuit 147 (FIG. 5) of the block 63/4 and consequently the input 148 of an AND circuit 149 are now excited. Since the other input 150 of the AND circuit 149 is excited by the flip-flop circuit FC , the flip-flop circuit FD is excited at the time TS via the AND circuit DD . At the same time, the AND circuit DD resets the flip-flop circuit FB to zero, as a result of which the central unit 5 changes from the state 0 to the state D.

State D is used to read the address of the cell into which the first operand is to be transferred. At time 75 (FIG. 4), an AND circuit 155 (FIG. 9) of block 636 generates the command COMQ1, which transfers the content of register 32 to input register 41 by opening gate circuit 64 (FIG. 2). The content of register 32 has been increased by one unit during state C, so that the address of the memory cell is read into input register 41 which follows that in which the content was read during state C.

If bit 66 of the address change is 1, the current page is selected by the command COM 18 via an AND circuit 156 (FIG. 9). In this case, the outputs are 62 _I2 and 62 ₁₃ of the decoding circuit 62 np.mlich to zero level and excite via two inverters together with the bit 66, the AND circuit 156. Now, the COMlS command via the circuit 113 transmits (Fig. 2 ) the content of the storage register 71 into the address decoding circuit 45. Since the content of the register 71 has not been changed during the foregoing states, it determines the

current page.

If the bit b 6 is equal to 0, the command COM 18 is not generated by the AND circuit 156 (FIG. 9), so that no bit is read into the address decoding circuit Λ5 , which causes the selection of the page 0.

At the same time, the memory cell selected by the third character of the command, ie by the address of the cell into which the first operand is to be transferred, is read. This content is then transferred to the output register 50. In addition, the command COM03 (FIG. 9) is directly generated by the flip-flop circuit FD and causes the read address to be rewritten in the selected cell.

When bit II of the address change is 1, it energizes an input of an AND circuit 157 (Fig. 9). Since the output 62, _{2 is} at the level 0, the other input is also excited, as a result of which the AND circuit 157 in turn excites an ODHR circuit 158 and thus an AND circuit 159. The AND circuit 159 then generates the command COM 06 which, as discussed above, sets the memory input circuit 47 (FIG. 2) in such a way that the address which has been removed from it and increased by one unit is rewritten into the selected memory cell. During state D , an AND circuit 160 generates instruction COA / 04 at time TR which, as discussed above, causes the contents of register 32 (FIG. 2) to be increased by one.

Finally, at the time TS (FIG. 2), an AND circuit D £ (FIG. 5) is excited, which in turn directly excites the flip-flop circuit FE , as a result of which the output ME is brought to level 1. The AND circuit DE also resets the flip-flop circuit FD to zero, as a result of which v, the central unit 5 changes from the state D to the state E. The state E is used to transfer the first operand, which was temporarily stored in the register 57 during the state C, into the cell of the memory 42 whose -to address was read during the state D. At the time TS the command COM10 is generated by an AND circuit 160 (FIG. 10) of the block 636, which, by acting on the gate circuit 141 (FIG. 2), the transmission of the taken during the state D and into the The address read in from register 50 is effected in register 41.

If bit 66 is equal to 1, an AND circuit 162 (FIG. 10) generates command COM 18 which, as already mentioned, transfers the contents of page register 71 (FIG. 2) to address decoding circuit 45 causes. Since the output 62 of the circuit corresponding to the transfer command is at level 1, an OR circuit 163 (FIG. 10) and thus an AND circuit 164 is energized. In this way, the r> command COM 14 is generated which, acting in the manner already mentioned on the memory input circuit 47 (FIG. 13), transfers the first operand contained in the register 57 into the memories selected by the address decoding circuit 45 - t> o cell causes. Accordingly, during state K, the first operand is transferred from the cell, which corresponds to the address determined by the second character of the command read out during state B , into the cell which corresponds to the address determined by the third character read out during b5 addition D .

At the instant 75 (FIG. 4) following the operations described, the flip-flop circuit / E (FIG. 5) excites the input 166 of an AND, provided that no interruptions from one of the peripheral devices 6, 7, 8 occur Circuit 167. Its other input 168 is fed through an inverter 169 by a di; Signal INT that indicates interruption is energized because it has the value 0. The output 204 of the AND circuit 167 in turn energizes the flip-flop circuit FA via the AND circuit DE , as a result of which the central unit 5 passes from the find state to state A , whereupon the execution of the next command can be initiated.

2. Exchange (SCA)

The exchange command (SCA) is identified by the code 1010 and causes the transfer of the first operand read in the cell determined by the second character into the cell determined by the third character, whereby the first four bits are replaced by the second \ 'ier bits of the first operands are exchanged. Changing the address of this command has the same meaning as changing the address of the TRA command.

The command SCA is recognized by the decoding circuit 62, which thereupon generates a signal _{at the output 62 2.} The instruction is executed in a manner completely identical to that in which the instruction TRA discussed above is executed. The only difference is that during the fine AND circuit 175 (FIG. 10) excited _{by the output 62 2} , the command C0M19 is generated. This command, which acts on the memory input circuit 47 in the manner described above, causes the contents of the register 57 (FIG. 2) to be transferred into the selected memory cell with the exchange of the two bit groups.

3. Comparison (CFR)

The comparison command (CfR) is by code 1001 and causes the bit-wise comparison between the first operand and the second operand, the result of which is expressed by the bit £ read into the register 96 (FIG. 2) of the central unit 5 will. Changing the address of this command has the same meaning as changing the address of the preceding commands.

The command CFR is recognized by the circuit 62, which thereupon generates a signal at the output 62. The CFR command is executed in the same way as the TRA command. The only difference is that the commands CO / W03 and COM20 are generated during state £. The command COM 03 is now namely generated by an AND circuit 176 (FIG. 10) and causes the contents of the output register 50 to be written, ie the second operand to be written into the selected memory cell. The command COM20 is generated at time 77 (FIG. 4) by an AND circuit 177 (FIG. 10) and, as already mentioned, sets the memory input circuit 47 (FIG. 2) so that between the contents of the registers 50 and 57 a comparison is made and, provided the content of the two registers is the same, bit E = 1 is read into register 96.

4. Logical product (AND)

The AND command is identified by code 1111 and causes the logical AND function bit by bit between the first operand and the second

Operands. Changing the address of this command has the same meaning as changing the address of the previous commands.

The AND command is recognized by the circuit 62, which then generates a signal _{at the output 62 4.} This command is executed in exactly the same way as the CFR command. The only difference is that during state E the output 62 ₄ energizes an AND circuit 178 (FIG. 10) which in turn generates the command COMIX. This acts as mentioned>"on the Speichareingangsschaltung 47 in such a way that the logic function is performed between the contents of registers 50 and 57th The result of this comparison represented by an eight-bit characters on the one hand to the memory cell This is made possible by the fact that the address of the second operand is present in register 41 during state E.

5. Exclusive OR (ORE)

2 (1

The ORE instruction is identified by code 1110 and causes the exclusive OR function bit by bit between the first operand and the second operand. The result of these operands is stored in the cell of the second operand in the memory 42. With this command, the address change also has the same meaning as the address change of the previous commands.

The command ORE is recognized by the circuit 62, which then _{generates a signal at the output 62 S} , and acts in the same way as the command AND. The only difference is that during the state £ the output 62 ₅ energizes an AND circuit 179 (Fig. 10), which in turn sends the command COM2! generated. As already mentioned, this instruction acts on the memory input circuit 47 in such a way that the exclusive-OR operation is carried out.

6. Free transmission (TRL) w

The command free transfer (TRI.) Is identified by the code 1011 and causes the transfer of the first operand from the line defined by the second character into the cell defined by the third character on any page of the memory 42, in contrast to the command TRA. The side in which the transfer takes place is identified by bits hU and 67 of the address change. If 66 = 67 = 0, the address specified by the third character belongs to page 0, while if 66 = 0 and bl = 1, it belongs to page 1, if 66 = 1 and bl = 0 to page 2 and, if 66 = bl = 1. belongs to page 3. Bits 64 and 65 of the address change have the same meaning as bits b4 and 65 of the address change of the command TRA.

The command TRL is recognized by the circuit 62, which thereupon _{generates a signal at the output 62, 2} , and is executed in the same way as the command TRA with the exception that in state D the output 62 _{] 2} fco is an OR circuit 180 (Fig. 9), which in turn command COM2! generated. This command, which acts on a gate circuit 185 (FIG. 2), transfers bits 66 and b1 of the address change, ie the address of the memory page to which the first operand is to be transferred, into decoding circuit 45.

The second group of commands includes commands that relate to a constant that represents the first operand and is expressed by the second character of the command. These commands are: constant transfer (TRC), free constant transfer (TLC) and constant comparison (CDQ. The aforementioned commands are executed by the central unit 5 with the aid of the sequence of states A, B, D, E. The time required for their execution is accordingly 8 VS These commands are assigned to the outputs 62 _m , 62, ₃ or 62 || of the decoding circuit 62.

They are executed in essentially the same way as instructions (TRA), (TRL) and (CFR), with the exception that state C is not executed. This is because the operations carried out in states A and B correspond entirely to the operations carried out by the corresponding commands of the first group. More precisely, the code of the command is read during state A and the second character, which is now the constant, is read during state B. Since the constant is now read during state B , it is not necessary to execute state C which, on the other hand, is used to read the first operand into memory 42 by the corresponding instructions of the first group.

Since one of the outputs 62 | _U , 62 _{! 3} , 6Z ,, is at level 1, the OR circuit 186 (Fig. 5) is energized. This circuit energizes the input 187 of an AND circuit 188, while its other input 189 is energized by the flip-flop circuit FB , as a result of which the AND circuit 188 at the time TS (FIG. 4) the flip-flop circuit FD excited via the AND circuit DD. The AND circuit DD also resets the flip-flop circuit FB to zero by acting on the corresponding reset circuit, so that an immediate change from state B to state D takes place.

1. Constant transfer (TRC)

The constant transfer command (TRC) is identified by the code 1100 and causes the constant expressed by the second character of the command to be transferred to the cell specified by the third character of the command. The constant can also be increased by one unit or not after the command has been executed under the control of bit 65 of the address change. If 65 = 0, the constant remains unchanged; if bit 65 = 1, the constant is increased by one unit. The memory address determined by the third character can also be increased by one unit or not under control of the bit bl of the address change. If 67 = 0, the address remains unchanged; if 67 = 1, the address is increased by one unit.

It should be noted that bit 64 of the address change is always zero and is not used. Therefore, bit 66 of the address change is used to determine the memory page to which the address expressed by the third character belongs. If 66 = 0, the address belongs to page 0; if 66 = 1, it belongs to the current page.

The command TRC is recognized by the circuit 62, which then generates a signal _{at the output 62 I0.} As already mentioned, this signal causes the central unit 5 to immediately transition to state D. During this state, the same operations as those described with the aid of the command TRA are carried out

executed, ie reading the third character of the command. During the status test, the constant is transferred to the address specified by the third character, as with the TRA command.

2. Free constant transfer (TRC)

The command free constant transfer (TLC) is identified by the code 0100 and causes the transfer of the constant specified by the second character to the address specified by the third character. Changing the address of this command has the same meaning as changing the address of the TRL command. During states A and B , the same operations as those described for the command TRC are carried out, ie reading the code of the command and the constant.

The command is recognized by the circuit 62, which then generates a signal at the output 62 ,,. As. already mentioned, this signal causes the central unit 5 to immediately transition from state B to state D. During this state, the third character of the command is read as in the case of the TRL command. The constant is then transferred to the address specified by the third character during the £ "state, as in the TRA command.

3. Constant comparison (CDC)

The command to compare a constant (CDC) is identified by the code 1101 and effects the bit-by-bit comparison between the constants expressed by the first operand and the second operand. The result of this comparison is expressed by the bit E = I when the two operands are the same and by the bit E = 0 when they are different. This bit is entered in the register 96 of the central unit 5 (Fig. 2).

The change of address of the CDC command has the same meaning as the change of address of the TRC command. The command CDC is recognized by the circuit 62, which then generates a signal at the output 62 ,, as a result of which the transition of the central unit 5 from the state B to the state D takes place. During this state, the second operand is read as with the CFR command. Finally, a comparison takes place between the constant and the second operand during state £.

The third group of commands includes the commands which are executed by the central processing unit 5 (FIG. 2) with the aid of the sequence of states A, B and C. Accordingly, the time required to execute them is 6 µs. These commands are: The Sign From Peripheral Device Command (CDP). the character-to-peripheral command (CAP) and the jump command (SAL).

These commands have a single address and are therefore made up of two characters. The first character contains the code identifying the type of command within the boundaries of the group and the appropriate one Change of address. The second character contains the memory address of the operand.

1. Character from peripheral device (CLP)

The character from peripheral device command (CDP) is identified by the code 0110 and causes the operand to be transferred from the peripheral device determined by bits 66 and 67 of the address change to the memory address determined by the second character. Bit 64 of the address change determines the memory page to which the address specified by the second> character belongs. If 64 = 0, the address belongs to page 0; if 64 = 1, it belongs to the current page. If, in addition, bit 65 = 0, the address remains unchanged after the command has been executed; if bit 65 = 1, the address is increased by one

ι »Unity increased.

During state A of CDPdurch command is recognized, the circuit 62, it produces a signal at the output 62. ₈ During state B , the second character of the command is read as with the commands of the first and second group. The second character of the command determines the cell of the memory 42 in which the character transmitted by the peripheral device 6, 7 or 8 determined with the aid of bits 66 and 67 of the address change is to be recorded.

Then the central processing unit 5 changes from the state B to the state C, since the AND circuit 139 of the block 63/4 (FIG. 5) is excited by the AND circuit 133, the outputs 62 ₆ , 62 ₇ , 62 _m , 62,, and 62 _I3 of circuit 62 are zero. During the state

y-> of the C , the output 62 «excites an AND circuit 197 (FIG. 8), which in turn generates the command COMY1 , which in the memory input circuit 47 transfers the character present on the channel 46 (FIG. 2) into the cell of the memory 42, the address of which is selected

Jo rend of state B has been read.

After these operations, the central unit 5 returns to state A. Since the output 62 _{S is} at level 1, an OR circuit 198 (FIG. 5) is always energized. As a result, one input 199 of an AND circuit 200 is excited, the other input 201 of which is excited via the inverter 169. In this case, the AND circuit 200 excites an AND circuit 202 which is opened by the output 203 of the flip-flop circuit FC. The output 204 of the AND circuit 202 excites its-

On the other hand, at the time TS (FIG. 4), the flip-flop circuit FA, as a result of which the central unit 5 changes from the state C to the state A.

2nd character according to peripheral device (CAP)

The character-to-peripheral device command (CAP) is identified by the code 0111 and causes the operand, the address of which is determined by the second character, to be transferred to that by bits 66

so and 67 of the address change certain peripheral devices. These bits have the same meaning as the corresponding bits of the CDP command. During state A , this command is recognized by the circuit 62, which then generates a signal _{at the output 62 g.}

The second character of the command read in state B now identifies the address of the character that is to be transferred to the peripheral device determined by bits 66 and 67 of the address change. As far as this order is concerned, the central

bo unit 5 due to the fact that the AND circuit 133 of the block 63A (Fig. 5) is energized, from the state B to the state (Tuber. During the state C the reading of the character takes place whose address during the State B has been selected, and at the same time its temporary storage in the output register 50 (Fig. 2) In addition, the output 62 _q energizes the AND circuit 195 (Fig. S), which in turn generates the command COAfOS

is transmitted to the selected peripheral device in order to prepare it to receive the character transmitted from the central unit 5. After these operations, the central unit 5 returns to state A as in the case of command CDI ¹ .

3rd jump (SAL)

The jump instruction (SAL) is identified by the code 0010 and enables you to pass from one instruction to another instruction even if these instructions are not consecutive in the course of the program being executed. The second character of the SAL command indicates the stored address of the next command to be executed by the central unit 5.

The same operations as described for the previous instructions are also performed during states A and B for the SAL instruction. Bits 66 and 67 of address change 2 «, on the other hand, determine the page to which the cell specified by the second character of the command belongs, as in the case of the TRL and TLC commands. This memory cell now contains the first character of the command to be executed afterwards.

The jump can be conditional or unconditional. For example, in the case of a comparison carried out by the CDC instruction, the result is expressed by the bit E read into the register 96 (FIG. 2) of the central processing unit 5. The command SAL can then be conditioned either by the bit E = 0 or by the bit E = 1, depending on the particular arrangement of the program being executed.

The value of the bit E , which determines the execution of the jump instruction, is identified by the bits J? ύ4 and 65 of the address change of the command. More precisely, there are the following two cases: 64 = 65 = 0 door the command SAL caused by the value E = Q , which is carried out if £ "= 0; 64 = 0 and b 5 = 1 for that caused by the value E = Conditional jump command 1. 4 <>

The second character read during state B and recorded in the output register 50 now represents the memory address to which the jump is to take place.

The block 63Λ contains a logic circuit 105 (Fig. 5), which can send out an output signal CV in a known manner, which represents the following logic function:

CV = 64 +65 - £ + 65 E.

50

Therefore CV equals 1 if 64 = 65 = £ = 0 or 64 = 0 and 65 = E = 1.

If the jump condition is not fulfilled, ie if E = 1 and E = O in the two cases mentioned, the signal CV = 0. Then an AND circuit 210 of the block (AA is excited because the two inputs 211 and 212 are open level 1 are located, while the output 62 ₆ is energized the circuit 62. Consequently, energizes the AND circuit 210 via an OR circuit 213 to the input 214 of an AND circuit 215, whose other input is to 216 then energized by the inverter 169th In In this case, the AND circuit 215 excites the input 217 of an AND circuit 218, the other input 219 of which is connected to the output 220 of the flip-flop circuit FB . Consequently, the output 221 of the AND circuit 218 excites the flip-flop circuit FA at time TS via a conductor 204. Accordingly, if the jump condition is not fulfilled, the central unit 5 returns from state B to state A , as a result of which the jump command is not executed.

If, on the other hand, the jump condition is fulfilled, ie if the bit £ "has the values 0 or 1 in relation to the two preceding cases, the signal CV is at level 1. This signal accordingly excites an OR circuit 137 and via the AND circuit 133 also the input 138 of the AND circuit 139. The other input of this circuit is excited by the flip-flop circuit FB , provided that the central processing unit 5 is in state B. As a result, the flip-flop circuit FC is at the time TS via the AND -Circuit DC energized.

The central processing unit then changes from state B to state C, during which the AND circuit 140 (FIG. 8) generates the command COMIQ , which causes the contents of register 50 (FIG. 2) to be transferred to address register 41. In this way, the memory address to be followed by the jump is temporarily stored in register 41. At time 77, an AND circuit 225 (FIG. 8) generates the command COMII which, by opening a gate circuit 121 (FIG. 2), transfers bits 66 and 67, which indicate the page to which the address belongs, to the page register 71.

Another AND circuit 226 also generates the command COMII, which can disable the counting circuit 44 (FIG. 2). In this way, when the command COM04 is generated at the time TR by an AND circuit 227, the same address temporarily stored in the register 41, that is, the second character of the command indicating the address from which the next command is executed, becomes , read into register 32.

After the operations carried out in state C have been completed, the central unit 5 changes to state A , as in the case of the commands CDP and CAP. During the following state A , the address determined by the second character of the command and by bits 66 and 67 of the address change is then read into the address registers 41 and 71.

The unconditional jump is executed, for example, when any of the peripheral devices interrupts a program that is being executed. For example, the interruption can be caused when a peripheral device has carried out the operation indicated by a command CAP supplied to it by the central unit 5 or when a peripheral device enters a character into the central unit 5 with the aid of a command CDP. As a result of this interruption, it is necessary for the central processing unit 5 to store a jump instruction in a memory cell which makes it possible to return to the last address considered before the interruption by the program. This jump command is therefore not conditioned by the value of the E bit. It is identified by the bits Z> 4 and 65 of the address change, which in this case assume the values 1 and 0, respectively. The output signal CW of the circuit 105 (FIG. 5) is then always at level 1 regardless of the value of the bit E. In this case, the central processing unit 5 carries out the same operations as have been described for the conditional jump instruction with the condition fulfilled .

There is also an unconditional jump command called the "re-entry" jump command, the meaning of which is explained in more detail below. This command is identified by bits b 4 and 6 5 of the address change, both of which assume the value 1.

men. In this case, too, the signal CK is always on Level 1, as a result of which the central processing unit 5 carries out the same operations as for the conditional jump instruction has been described with a fulfilled condition.

The fourth group of commands includes the commands that are executed by the central unit 5 with the aid of the sequence of states A and B. The conditional jump instruction also belongs to this group if, as already discussed, the jump condition is not fulfilled.

This group also includes the instruction to peripheral device (COP) command, which is identified by the code 0101, and the transfer of the instruction, the code of which is determined by the second character, to that determined by bits 66 and 67 of the address change Peripheral device effected in the manner described with reference to the commands CDP and CAP. It should be noted that bits 64 and 65 of the address change are not used by this command and are therefore always at level 0.

During state A, the decoding of the instruction now takes place by the circuit 62 which energizes the output 62. ₇ During state B , the second character of the command representing the instruction to be transferred to the selected peripheral device is read out and transferred to AusTabelle I.

gear register 50 instead.

Two AND circuits 230 and 231 (FIG. 7) excited by the output 62 ₇ now generate the command COMm and COMW, respectively. The command COM0S causes the contents of the output register 50 to be transferred to the peripheral device, while the command COM09 is transferred directly to the central unit 5 in order to indicate that the character coming from the central unit is a command and not a character.

After these operations have been carried out, the OR circuit 213 (FIG. 5) _{excited at the time TS by the output 62 7 of} the circuit 62 causes the flip-flop circuit FA to be excited in the same way as has been described for the jump instruction with the condition not fulfilled is, as a result of which the central unit 5 consequently transitions from the state Sin to the state A.

The characteristics of each command are given in the summary tables below, where in Table I shows the symbol for each command, the corresponding designation, the one associated with the command Code, the corresponding output of circuit 62, bits 64 and 65 and their meaning are indicated. In Table II shows the machine states in which each command is executed by the central unit 5, the group to which the command belongs, the value of bits 66 and 67 and their meaning are given.

symbol command code exit Λ4 and 65 meaning TRA transmission 1000 62, SCA exchange 1010 62 ₂ 64 = 0 1st operand is on CFR comparison 1001 62, Page 0 AND Logical AND function 1111 62, 64 - 1 1st operand is on ORE Exclusive-OR 1110 62 ₅ current page TRC Constant transfer 1100 62 lu CDC Constant comparison 1101 62 ,, 65 = 0 1st operand TRL Free transfer 1011 62 ,: unchanged TLC Free constant transfer 0100 62.3 65 = 1 1st operand + 1 CDP Sign of peripheral device 0110 62 _p CAP Character by peripheral device Olli 62 " COP Instruction to peripheral device 0101 62- 64 = 65 = 0 not used SAL Leap 0010 62, 64 = 0 Jump conditional 65 = 0 by £ = 0 64 = 0 Jump conditional 65 = 1 by E = 1 64 = 1 unconditional 65 = 1 Leap 64 = 1 Re-entry 65 = 0 Leap Table II symbol Machine states group Z> 6 and bl meaning

TRA SCA CFR AND

A, B, C, D, E

66 =

66 =

2nd operand is on page 0
2. Operand is on the current page

continuation

Svmbul

Machine states group Λ 6 and /> 7

meaning

ORE TRC

67 =

2. Address unchanged

CDC A, B, D, E II 67 = 1 67 = 0 2nd address + 1 TRL A, B, C D, E I. 66 = 0 67 = 1 as for jump command 66 = 0 67 = 0 TLC A, B, D.E. II 66 = 1 67 = 1 66 = 1 67 = 1 CDP A, B, C IU 66 = 0 67 = 0 Tape storage 66 = 1 67 = 1 typewriter CAP 66 = 1 Control keypad COP AWAY IV 67 = 0 SAL A, B, C UI 66 = 0 67 = 1 2nd operand is on page 0 66 = 0 67 = 0 2nd operand is on page 1 66 = 1 67 = 1 2nd operand is on page 2 66 = 1 The 2nd operand is on page 3

As already mentioned, during the execution of one of the commands described above, an interrupt command can reach the central unit 5 (FIG. 2) from any of the peripheral devices connected to it. For the purpose of executing the current command, the execution of the program being executed is then interrupted and a further series of commands is executed. The machine states used to execute the interruption are states F and G, so that the interruption is executed in 4 μβ.

When one of the peripheral devices 6, 7 and 8 supplies an interrupt signal INT , the logic circuit 31 (FIG. 2) energizes the conductor 76, which feeds the signal // V into block 63/4 (FIG. 5). If at the time the signal // vTs is supplied, an instruction of the first or second group ending with the state E is in execution, the central unit 5 continues the execution of the instruction until this state has been reached. Then, as already mentioned, the output ME of the flip-flop circuit FE is excited and the input 232 of an AND circuit 233, the other input 234 of which is excited by the signal INT. Accordingly, the circuit 233 energizes the flip-flop circuit FF at the time TS , so that the central processing unit 5 changes from the state E to the state F.

If an instruction of the third group, the execution of which ends with the state C, is being executed at the time the signal INT is supplied, the interrupt to be carried out only begins when this state is reached. This is because the output MC of the flip-flop circuit FC and consequently the input 203 of an AND circuit 248 are excited. The other input 235 of this circuit is only energized when an AND circuit 236 is energized. This only occurs when both conductor 76 and the output of OR circuit 198 are at level one. This OR circuit is energized when an instruction ending with the state C is in execution, namely to the extent that it is suspended; into the output corresponding to the instructions SAL, CAPuM C '/;/'

bO corridors 62 ₆ , 62 ₈ , 62 are connected. In this way it can never happen that the execution of an instruction which does not end with the state C can be interrupted by the signal INT in the state C. When the AND circuit DP is energized via the AND circuit 248, the central processing unit 5 changes from the C state to the F state.

Correspondingly, the signal / AT only has an effect in the case of a command of the fourth group that is being executed and ends with state B if this state has been reached. This is because the output 220 of the flip-flop circuit FB excites the input 240 of an AND circuit 241, the other input 242 of which is excited by a further AND circuit 243. The AND circuit 243 is only energized when both the signal / TVTaIs and the output of the OR circuit 213 are at level 1. This only occurs if the COP command or the jump command with the condition not met is being executed. In this way, the possibility is prevented that the execution of a never-ending with the state B command irr state B is interrupted. When the AND circuit 241 is energized, the central processing unit 5 goes from state B to state F.

In any case, during the state F ir the reading of the memory cell selected during the previous state takes place, as is known, as if the central processing unit 5 had returned to state A. The content of this cell is transferred to the output register 50 in the manner described above.

Then, at the time TM (FIG. 4), an AND circuit 245 (FIG. 11) generates the command COM25, the. by acting on the gate circuit 246 (FIG. 2), the contents of the register 32 are transferred into the register 57. This content corresponds to the memory address of the last command being executed. At the same time, the command COM25 sets all flip-flop circuits of the input register 41 to level 1 by acting on the respective setting circuits. In this way, cell 255 is selected because the configuration 11111111 of register 41 corresponds exactly to this cell.

The page to which this cell belongs is page 0, because the content of the register is not transferred to the address circuit 45 71 because the gate is closed 113 / "is the gate 113 opening command C0M \% During state that is not is generated, as a result of which the configuration 00 is present in register 71.

Then the output A / F of the flip-flop circuit / Fun directly generates the command COMH (FIG. 11), which acts on the memory input circuit 47 (FIG. 2), the character 001011 followed by the bits contained in the register 71 reads into the output channel 48. For this purpose, the logic circuit 47 contains a circuit 101 (FIG. 13) which is formed, for example, from six flip-flop circuits which are set by the command COMH in such a way that the bit configuration 001011 is achieved at their outputs. The circuit 101 also adds the two bits coming from the register 71 via the input channel 82 to this configuration. The eight bit configuration is then transferred to output channel 48. The output channel 48 forms the input of the memory 42 (FIG. 2), so that the configuration of eight bits is written into the cell of the memory 42 selected by the address contained in the input register 41. As already described, this address corresponds to cell 255 on page 0.

As already mentioned, the character 001011 determines the reentry jump instruction, on the other hand the bits in the register 71 determine the current page. At time 77? (Fig. 4), an AND circuit 247 (Fig. 11) generates the command COM 04, which reads the content of the input register 41 increased by one unit, ie the character 00000000 corresponding to cell 0 on page 0, into the Register 32 causes.

Thus, it is clear that during the Fin state, cell 255 from page 0 is the re-entry jump instruction and the address 00000000 is read into the address register 32.

At the instant TS (FIG. 4) following these operations, the central unit 5 changes to state G , since the AND circuit DG (FIG. 5) is energized. During state G , at time TS, another AND circuit 250 (FIG. 12) generates the command COMO1, which causes the contents of register 32, ie the address corresponding to cell 0 on page 0, to be transferred to input register 41 .

At the time 77V following the time 73T, an AND circuit 251 (FIG. 12) also generates a signal RO, which resets the flip-flop circuits of the page register 71 (FIG. 2) in a known manner and thus resets page 0 selects. The output MG of the flip-flop circuit FG also directly generates the command COM 14 (FIG. 12) which, by acting on the memory input circuit 47 in the manner already described, is stored in the register 57 (I'ig. 2 ) contained stored address of the last instruction in execution in the cell 0 of page 0 of the memory 42 transfers.

With the help of the operations just described, there is an instruction for one in cell 255 on page 0 WicdereinlriH jump to the page to which the address of the at the time ι of the occurrence of the interruption belongs to the command being executed. This address is also in Cell 0 of page 0 has been saved.

After these operations, a further AND circuit 252 (FIG. 12) generates the command COM26 at the time TR following the time TM (FIG. 4). This command acting on a gate circuit 253 (FIG. 2) transfers the content of the logic circuit 31 to the register 32, ie reads the address corresponding to the peripheral device 6, 7 or 8 that caused the interruption into the register 32. At the same time, the content of the register 32 is read into the logical reset circuit 34 via the channel 33. In addition, the command COM26 acting on a gate circuit 255 transfers the possible comparison bit £ from register 96 to register 97, where it is stored for the entire duration of the interruption. This is because register 96 could be used during the actual interruption if, for example, the interruption contains the command CFR or CDC .

If the INT signal in the course of a command through more than one of the peripheral devices 6, 7, 8 at the time 77? (Fig. 4) the following time Π is generated, an AND circuit 256 (Fig. 12) generates the command COM 24 and opens a gate circuit 257 (Fig. 2). This thus causes the resetting of the flip-flop circuit of the register 30 corresponding to the peripheral device with a higher priority which caused the interruption. In this way, after the execution of the program corresponding to the interruption brought about by this peripheral device, another possible interruption corresponding to a peripheral device with a lower priority can be brought about.

After these operations, the central unit 5 returns to the state A at the time TS following the time TI insofar as the AND circuit DA (FIG. 5) excited by the output MG of the flip-flop circuit FG is open at this time will. Thus, the execution of the first instruction in the series of instructions relating to the interrupt, the address of which has been temporarily stored in register 32, is started. Consequently, during state A, in which the central processing unit 5 is at the end of the interruption, the command COMO1 is generated, among other things, which enables the transfer of the address corresponding to the first command to be executed from the register 32 to the input register 41. This instruction is then executed along with the rest of the interrupt-related series of instructions under the same conditions as described above in accordance with the nature of the instruction proper.

To resume the interrupted commands by the central unit 5, the last command is the the series of commands relating to the interruption is always an command for an unconditional jump to the address of cell 255 of page 0. In this cell, as mentioned above, the first character is a Command for a re-entry jump to the cell 0 on page 0 following cell 255 saved second character of command specific address has been saved.

The re-entry jump command is then issued by the central processing unit 5 in the manner described above is carried out and causes the central processing unit 5 to return to the same conditions under which it was at the time of the interruption. To be more precise, am linde of the re-entry branch instruction in the register 41 by the / while

Character of the actual command specific address, ie the same address at which the central unit 5 was at the time of the interruption, recorded. In addition, during state B of the re-entry jump command, since bits 64 and bs of the address change both take the value 1, the command COM 13 is generated by the AND circuit 258 (FIG. 7). This command, which acts on the gate circuit 259 (FIG. 2), transfers the bit E from the register 97 into the register 96. As a result, the bit E , which was in it at the time of the interruption, is temporarily stored in the register 96. After the re-entry jump command has been executed, the system returns to state A, which leads to the continuation of the interrupted program.

The control unit 9 (Fig. 1 and 14) for the typewriter6 controls the exchange of data and commands between the typewriter 6 and the central unit 5. The output device 12 of the typewriter 6 contains an input circuit 12 'for recording the codes of characters and the codes of the function characters from the control unit 9. These codes are made up of eight hits, six of which are used to determine the character, one a Shift bit to determine uppercase and lowercase letters, while one bit is used as a parity bit, for example can be used. The six bits of the character act in a known manner on a number of six electromagnets to select the character or function to perform. jo

The input and output device 12 also contains an output circuit 12 "to the codes of the seven characters and the functions that are entered in a known manner on the keypad 27 (1 or the keypad 271 to be transmitted to the control unit 9. The π transmission of the codes takes place by switching from in Fig. 14 instead of six switches of any known type, not shown.

The functional conductor 65 connecting the control unit 9 to the central unit 5 is only excited by the decoding sound 65 if this sound selects the typewriter 6 in the manner described above. The data is also exchanged mitderZentraleinheil 5 via the Speichcrcingangsschaltung 47 dcrZcntraleinhcit5angeschlüssencn Ausgangskanal46 ^ and via the connected to the output register 50 of the central unit 5 input channel 51st

The input channel 51 transfers the data present in the output register 50 to an eight-bit register w 273 of the control unit 9. The operation of the control unit 9 is controlled by the central unit 5 with the aid of the external commands COP and CAP for receiving a command or a character from the central unit 5 and controlled with the aid of the command CDP for the transmission of a ^r > ^r > character in the central unit 5. More precisely, the control unit can be brought into a transmission or reception state by the central unit 5 with the aid of the command COP. As already mentioned, the command COP generates two commands m> COMQ8 and CO / W09, which are fed to a decoding circuit 274 of the control device 9 via a conductor 269. The decoder circuit 274 acts in a known manner to decode the received command. If this command is the command (ΌΛ / 08, the <v> sound 274 excites the output COMOH '; if it is the command COM09 , it excites the output COMW. These outputs set the control device 9 to the transmit or receive state .

If the central unit 5 intends to receive characters from the control device 9 with the aid of the command CDP, it sends a command COP to the control device 9 which generates the command COM 08. This command, together with the signal which selects the control unit 9 and is present on the conductor 65 ₂ , an AND circuit 275, which acts on the reset circuit of a flip-flop circuit 276 in such a way that it then indicates that the control unit is in Transmission status is.

When the operator presses a character key on the keypad 270, the output circuit 12 "excites in a known manner via a conductor 277 an AND circuit 278, which in turn is opened by the flip-flop circuit 276. This is the reset circuit of a flip-flop -Circuit 279, the output signal of the AND circuit 278 opens a gate circuit 280, so that the character; n entered on the keypad 270 is transmitted to the output channel 46. The conductor 277 is connected to the input 30o of the register 30 via an OR circuit (FIG . 2) and causes an interruption in the operation of the central unit 5 in the register in the manner described above first: contain characters of a command CDP , as a result of which the central unit 5 to receive the on the channel 46 existing character is set.

If the operator actuates a function key on the keypad 271 (FIG. 14), the keypad delivers to the conductor 285 a signal that, in the same way as in the case of conductor 277, the transmission of an interrupt signal in the central unit 5 causes. This makes the central unit to receive the Channel 46 has been prepared for the existing function symbol. Conductor 285 also energizes an AND circuit 282, which in turn acts on the setting circuit of the flip-flop circuit 279, opens the gate circuit 283, which brings a channel 284 with the output channel 46 in connection.

The keypad 271 also delivers to a conductor

286 a signal corresponding to the actuated function key. This signal acts on a decoding circuit

287, which supplies the code corresponding to the key pressed. This code is made up of eight bits of which bits 64, 65 and 66 are always zero to assign a function character from a printable character differentiate. This code is fed to the output channel 46 via the channel 284 and the gate circuit 283.

If a command signal is to be transmitted into the control device 9, the central unit 5 sends it to it on the channel 51 a command CAP , which generates the command COM09. This command is decoded by the decoding circuit 274, which thereupon excites the output COM 09 '. This output acts via an AND circuit 290 on the setting circuit of the flip-flop circuit 276, which brings the control device 9 into the receiving state. This state is characterized by an output signal R of an AND circuit 291 which is opened by the flip-flop circuit 276 at the time TN. The AND circuit 291 is opened at the point in time TN , since at this point in time during the command CAP the central unit 5, as described above, is already in the memory 42 the peri-

The characters to be supplied to the peripheral device are removed and transferred to the input channel 51 of the control device 9 connected register 50 (Fig. 2) has temporarily stored

When the CAP command is executed, the character present on the channel 51 is then transferred to the register 273 by the central processing unit 5. Provided that this character is a service character, as mentioned above, by the zero bits A4, Λ5 and A6. A dccodicrschallung 299 connected to the register 273 supplies a signal) '. while, if this character is a print character, the decoding sound 274 in; in a manner known per se supplies a signal W instead.

In the first-mentioned case, a gate circuit 295 is opened, as a result of which the information present in the register 273 is fed to the decoding hall 287 via a channel 296. This circuit provides a signal at an output 297, that is, via a gate circuit 298 which is opened by the signal> the input sound 12 'of the typewriter. It should be noted that the gate sounds 295 and 298 are only oiled if the reception state is (K I) and the / calibrates a function symbol is () 1 and W = 0).

If the character present in the register 273 is printable, the signal W is sent to a gate circuit 300 so that it is transmitted to the input circuit 12 'of the typewriter 6. It should be noted that the gate circuit 300 is only opened when the control unit 9 is in the receive state (R = 1) and the calibration can be printed (V / = 1 and Y = 0).

What has been said here for a single character also applies to successive ones, both received and also transmitted characters.

Whenever the input circuit 12 'has received a character, it delivers on a conductor 301 Signal which inputs an interruption into the central unit 5 via the input 30a, so that the central unit is prepared for feeding another character.

On the basis of the content of the memory cell identified by the interruption, the central unit 5 can now supply a command or a character by means of a following instruction. If, for example, the control device 9 is in the transmission state, the central unit can either supply a command CDP, as a result of which the transmission is continued, or a command COP for reception, as a result of which the control device 9 is set to the reception state. The character is of course supplied from the central unit 5 with the aid of a subsequent command CAP.

The control keypad 8 is used to supply a number of commands via the corresponding control device 11 to the central unit 5. More precisely, this keypad contains a main switch, not shown in the drawing, for the power supply to all units of the printing system. It also contains a start button, known per se, which enables the operation of the units to be started in such a way that the memory 42 of the central unit 5 is loaded with the initial command group in the manner described above. These instructions also allow the memory 42 to be loaded with a special set of instructions called "load" instructions c which can load the memory 42 with any other effective set of instructions in a manner to be discussed further below. The keypad 8 also contains a display lamp which is brought to light up with the help of a command from the control center inheil 5 korn mend en. For this purpose, since the exchange of commands between the central unit 5 and the keypad 8 takes place by means of a command COP , this command "does" the keypad 8 in the manner described for the control device 9 of the typewriter 6 the command

κι COP with the help of the decoding sound 65 (Fig. 2i di> keypad 8. Which only accepts a special command expressed by the second character of the command CiIP and formed from eight bits all at level 1. This command acts in a known manner the keypad 8 to cause the indicator lamp to light up.

The keypad 8 for its part can only send an interrupt signal to the central unit 5 by actuating the .in the input 30c of the circuit 30 (Fig. 2).

2i) deliver disruptive stasis. The interruption key then sets the central unit 5 in the manner described above in order to execute a series of commands linked to the interruption coming from the keypad.

The control device IO for the magnetic tape memory 7 controls the reading and writing of addresses. Programs and data in memory 7.

The memory 7 consists of an endless magnetic tape 310 contained in a cassette (FIG. I5).

in The cassette is interchangeable so that the system can contain any number of cassettes. The tape 310 contains a series of parallel tracks P \, Pl ... PN, on which the data are serially in blocks Bi ... B256 corresponding to one line of printing

J3 are recorded. Each block is separated from its neighboring block by a zone called an erasure zone, in which no recording takes place
Each memory block has a fixed length and comprises 80 characters of eight bits each. The characters of each block are consecutively numbered, fixed from 0 to 79. The characters from 6 to 78 are used to record the data relating to a corresponding print line, while the characters from 0 to 5 are used as function characters. More precisely, the first function symbol contains a constant which is used by the central processing unit 5 to extract from the tracks PX. . . P / V select the one that contains the block in which the next characters are to be recorded. The address of this block is determined within the boundaries of the selected track by the second / calibration, while the cassette itself is indicated by the third / calibration. The fourth / oak indicates the number of / ciches that each / hurry can reveal. This number can be selected by the operator in a manner to be described in more detail below so that the length of a print line is extended or reduced. The fifth / oak indicates the number of currently

wi contained / calibrate in the print line. The sixth / calibration symbol indicates the function to be carried out on this line, for example centering, underlining, etc. Finally, the 79th character is to _u uf the other ncuiumdsicbzig / calibrate beziehen-

bj of the longitudinal parity sign.

In addition to the track PX ... / W, the tape 310 also contains a track PO which contains the addresses / 1 ... / 256 of the data blocks. Each address

block IX ... / 256 is made up of twenty-five characters, only one of which is used to contain the address of the data block or the program block. Since this character contains eight bits, it is sufficient to determine one data block from the 256 data blocks in the selected track. The remaining twenty-four characters in each address block are used as function characters. The first three of these characters in particular can represent two constants that are used to identify an address block or a program block. PO on the track in which the sign of the effective commands of the printing system are recorded is recorded namely between an address and the next one formed of 70 characters program block BP \ ... BP256.

Each address block / 1 ... / 256 is used to select the data blocks which geometrically follow it in the direction of advance of the tape. For example, the data blocks Bl recorded on the tracks Pl ... PN are selected by the address block / 2. In order to clearly select a data block, the track to which it belongs must first be selected and then selected from the 256 blocks.

The control device 10 is via an input channel 51 (FIG. 17) to the output register 50 (FIG. 2) of the central unit 5 and connected to the input circuit 47 of the memory 42 via an output channel 46. In detail, the two channels 51 and 46 are connected to a register 318 via two gate circuits 316 and 317 of the control device 10 connected. The register 318 can use the bits temporarily stored in it a shift register 319 via two gate circuits 320 and 321. Register 318 transfers the Bits also in a decoding circuit 325, which correspond to the bits obtained from the register 318 can generate a variety of commands. The decoding circuit 325 acts on a time control device 326. which generates the operation of the control device 10 controlling clock signals.

The decoding circuit 325 can also be actuated with the aid of a signal present on the conductor 327 which is at level 1 when the start button of the keypad 8 is actuated. The decoding circuit 325 is connected via a gate circuit 328 to a four-digit register 329 which can supply a signal to a conductor 330 which, by acting on a read head of the magnetic tape memory 7, selects the track corresponding to the bits contained in the register 329 .

The register 319 is also connected to a further decoding circuit 335 , which sends out a signal at its output 336 if an address is present in the Regisier3i9. The signal present at the output 336 acts in turn on a circuit 337 which, when excited, supplies an interrupt signal to the input 306 of the circuit 30 (FIG. 2) of the central unit 5.

The register 319 is connected via a gate circuit 338 to a signal shaping circuit 339 which, at an output 340 , can supply signals corresponding to the characters contained in the register 319 from case to case. These signals are used by a writing device of the memory 7, which is not shown in the drawing. Finally, the register 319 is connected to a reader 342 of known type which can serially read the bits recorded on the tape 310 and transfer them to the register 319 via the conductor 343.

The exchange of data between the central unit 5 and the control device 10 takes place by means of the commands COP, CDP, CAi generated by the central unit 5. The control unit is initially in the idle or unemployed state. This state is shown symbolically in FIG. 18, which schematically illustrates the sequence of operations carried out both by the central unit 5 and by the control unit 10. The operations carried out by the control unit are indicated in rectangular blocks, while the logical decisions or alternatives are represented by rhombuses. On the other hand, the operations carried out by the central unit 5 are indicated by arrows which symbolically open gate circuits in order to enable the control device to transition from one operating state to the other.

In order to write or read information on the tape 310 of the magnetic tape memory 7, the central unit 5 supplies the control device 10 with a so-called “selection” command COP in the manner described above. Since, provided that the selected peripheral device is the memory 7 in the first character of the command 66 = 0 and 67 = 1, these bits acting on the decoding circuit 65 (FIG. 2) of the central unit 5 cause the conductor 65 ₂ (FIG. 2) to be excited and 17), which excites an input of an AND circuit 350 of the control unit 10 (FIG. 17). The other input of AND circuit 350 is excited by the COMOS command generated during state B by the COP command. In this way the gate circuit 316 is energized so that the second character of the instruction present on the channel 51 can be introduced into the register 318. The second character is simultaneously introduced into the decoding circuit 325 which, when it detects a so-called selection character, supplies a signal to a conductor 352 which causes the tape 310 to start up. The selection character is characterized by the fact that bits 65, 66, 67 have the value 001.

At the same time, the decoding circuit 325 supplies a signal L in a known manner, which opens the gate circuit 328 and transfers the four bits of the character present in the decoding circuit to the register 329. These bits are used to select a track from tracks PA ... PN of tape 310 . The register 329 now supplies a signal to the conductor 330 which is used by the memory 7 in a known manner for selecting the track.

In addition, the signal L prepares the reader 342 in a known manner for reading the addresses. The reading device 342 serially supplies the bits of the first character of the first address block read to the register 319. These operations are represented symbolically by block 353 (FIG. 1S).

It is also possible to switch the control device 10 to the address reading state by pressing the start button of the keypad 8 bring to. This button or key acts on circuit 325 in such a way that a selection command COP is simulated. That leads to the Circuit 325 performs the same operations as those described above, as a result of which the Control unit 10 likewise assumes the reading state represented by block 353.

As already mentioned, the address blocks c / 1 ... / 256 of the tape 310 are determined if the first three characters represent the corresponding constant. As a result, the decoding sounder operates 335

(Fig. 17) when it detects that the block read is a Address block is the circuit 337, which enables the supply of an interrupt command on the input 30Λ of the Circuit 30 of the central unit 5 (Fig. 2) causes. These operations are symbolic by the blocks 354 and 355 (Figure 18). Now the central unit is leading 5 the interruption.

The interruption now causes the central processing unit 5 to execute a jump instruction to the cell of the memory 42 (FIG. 2) corresponding to the memory 7 and in which the command CDP is stored. The central processing unit 5 then feeds the command CDP on the channel 51 to the register 318 (FIG. 17) of the control device 10. This command is decoded by the circuit 325 which supplies a signal M which brings the control device into the address transmission state (block 356 of FIG. 18). The signal M also opens the gates 321 and 317, so that the address extracted from the register 319 is transferred to the register 318 and from there via the channel 46 and the memory input circuit 47 (FIG. 2) into a predetermined cell of the core memory 42.

The central unit 5 then executes a command CDC by means of which it compares the address received from the control unit 1 (1) with the constant temporarily stored in the register 57 (FIG. 2) representing the address of the block the two characters is negative (bit E = 0), the central unit 5 does not feed a command to the control unit 10 (logical decision 357 according to FIG , 355, 356 of Fig. 18. If the comparison between the two characters is positive (bit E = 1), the central processing unit 5 supplies the command COP , which can be used for reading or writing 357 is of course reached with the aid of a conditional jump instruction, if the condition is not met (bit E = 0), the central processing unit 5. returns to the state as already discussed A back; on the other hand, if it is satisfied (bit E = 1), the central processing unit 5 executes a jump instruction to a memory address in which the first character of an instruction CW is recorded.

The type of command (write or read) is determined by the second character of the command COP , which is decoded by circuit 325. When this character indicates a read command, the decoding circuit 325 supplies the signal L which, by actuating the reading head 342, produces the serial reading of the bits of the first character of the selected block, which are transferred to the register 319 (block 358 of FIG. 18). When this register is full, it operates the circuit 337, which supplies the central processing unit 5 with an interrupt signal (block 360 of FIG. 18). By means of a command CZV, the central unit 5 effects the transmission of the character taken from the control device 10 into the memory 42 (block 361 according to FIG. 18). In this way, all characters of the selected block are transferred to memory 42.

If the central processing unit 5 determines that the character removed is the last of the selected block, it feeds a so-called end command COP to the control unit 10 (logical decision 362 according to FIG. 18). The decoding of the last character of the block is carried out by the central unit 5 with the aid of a command CDC. which causes the constant representing the sequential number of the character extracted from case to case to be compared with the constant representing the maximum number of characters in the block. If the comparison is positive (bit E = I), the central processing unit 5 delivers an end command COP by means of a procedure which completely corresponds to the procedure used to deliver a command COP for reading.
The decoder circuit 325 (Fig. 17) of the control unit

κι 10 decodes the second character of the end command COP and supplies command signals, not shown in the drawing, which in a known manner cause the control device 10 to transition into a state corresponding to the end command COP (block 363 according to FIG. 18).

When this symbol indicates the end of reading the block with stopping the tape, the control unit returns 10 back to the initial state (FIG. 18). If, although the end of reading the block is indicated, the reading of the next block is started, the control device returns to the mode indicated by block 358 (FIG. 18) shown condition back. When finally the sign for reading the block and at the same time for the Reading of a block that does not follow the block is started, the control unit returns to Address reading, d. H. to the state represented by block 354.

If the central unit 5 intends to record or write data in the selected block, it sends the control device 10 a command COP

«Ι to write to (logical decision 359). This Instruction is decoded by circuit 325 (Fig. 17), which consequently with the aid of a signal // the circuit 337 excited. The circuit 337 feeds an interruption to the central unit 5 (block 365 according to FIG. 18),

is whereupon the central unit 5 sends a command CAP to the control unit 10 in the manner described above. When this command is recognized by the decoding circuit 325 (FIG. 17), it supplies a signal A 'which, by opening the gate circuit 320, transfers the character to be recorded or written from the register 318 to the register 319. At the same time, the circuit 325 energizes the timing control circuit 326 which, by means of a clock signal TH, causes the bits in the shift register 319 to be shifted so as to be introduced into the waveform shaping circuit 339 in series. These operations are represented by block 366 of FIG.

When the entire character has been recorded, the writing instrument delivers a signal J.

which causes the transmission of an interrupt signal by the circuit 337 (block 367, Fig. 18). As a result, the central unit 5 can deliver an end command COP or a command CAP in the manner described above (logical decision 368). In the first-mentioned case the control device 10 returns to its unemployed state and in the second case to its state identified by the block 366 according to FIG. 18.

As mentioned above, the operation of the auto-

The bo matic printing system is controlled by command groups that each relate to a special processing operation to be carried out on a text. These instruction groups are recorded on the magnetic tape 310 (FIG. 15) in the program blocks 5Pl ... BP256 located on the track PO

be in the content.

The processing operations on the format enable the characters in a print line to be increased or decreased, the so-called alignment of the lines, ie the alignment of the right edge of the lines, to achieve one or more words in a line or one or more Underline lines or center one or more words with respect to the length of the line to be printed. On the other hand, the processing operations on ^{| (1} allow the content to delete one or more lines, add new lines or paragraphs, or correct errors.

Each of the processing operations described is determined by a corresponding command group, the "ι"> to take effect from magnetic tape storage? into the core memory 42 of the central unit 5 (Fig. 2) which it executes in the order in which it is recorded in memory 42 are. - '«

To transfer a command group from the tape memory 7 to the core memory 42, the operator presses the start pushbutton of the keypad 8. The decoding circuit 325 (Fig. 17) is then operated in the manner described above and brings the control device 10 of the tape memory 7 to the read state 358 ( Fig. 18). The central processing unit 5 then leaves its unemployed state represented by block 380 of FIG.

Now the addresses recorded on the track PO of the memory 7 κι (FIG. 1) are read and fed to the central unit 5 by the control device 10. Since each address is preceded by an interruption, this causes the central processing unit 5 to execute a jump instruction to a cell of the memory 42 (FIG. 2), the address of which is determined by the interruption itself in the manner described above. A command CDC is recorded in this address, by means of which in the central unit 5 in the circuit 98 (FIG. 13) the address coming from the control device 10 with the address in the regi- ·? » ster 57 temporarily stored compares. Since the address is made up of eight bits which are all zero, is the transmission of the first program block, when the control unit 10 supplies the information recorded on the tape 310 and indicated by eight zero bits address of this block of the central unit 5, from the band memory 7 in the core memory42 instead. The loading of the initial instructions is symbolically represented by block 381 (FIG. 19). The addresses of the cells of the memory 42 in which the characters of this block are recorded are supplied by the address circuit 45 of the memory 42. As already mentioned above, the command group recorded in the first block comprises the initial commands which enable the central processing unit to record subsequent commands in the manner described in more detail below.

As described above, the central processing unit 5 carries out the recording of the initial commands during the state A , the remaining in this state being determined by the output signal BT of the flip-flop circuit 35 (FIG. 2) when the initial instruction group has been completely written into the memory 42 , the central processing unit 5 turns to the execution of the instructions contained in the initial instruction group (block 382 of FIG. 19).

At this point in time, the central processing unit 5 (FIG. 2) is still in state A and the address of the cell following the cell occupied by the last command of the initial command group is recorded in the address decoding circuit 45. When the central processing unit 5 changes to state B in order to execute the first instruction of the initial instruction group, the content of the cell of the last instruction is stored in the output register 50 and then, due to the generation of the instruction COM 15 (FIG. 5), in the register 57 ( Fig. 2) transferred.

The first command of the initial command group is a command COP, by means of which the central unit 5 brings the control unit 10 to the read state 358 (FIG. 18). The central unit 5 then compares the addresses supplied by the control device 10 with the previously temporarily stored contents of the register 57 (FIG. 2). This content is the address of a block recorded on tape 310 contained in the load instructions, which relates to a further instruction group associated with a particular processing operation performed on the text. If this address is recognized by the central unit, the block identified by it is transferred from the tape memory 7 to the core memory 42. The operations carried out by the central unit 5 for recording the block of load commands are symbolically represented by block 382 (FIG. 19) and the same as those carried out by blocks 354, 355 and 356 (FIG. 18) described above are symbolic shown.

The instruction block written in this way into the memory 42 contains, as mentioned above, the address of a second block which is also a load instruction block. This second block is then written into memory 42, as described above. The central unit 5 is now in its working state, which is symbolically represented by block 383 (FIG. 19). In this state, the initial instruction group and the two loader program blocks are in the memory 42 because they have been written into it.

The load blocks enable, among other things, a special group of commands called "select" commands to be written in, which commands a special group of commands set up on keypad 270 (FIG. 14) of typewriter 6 from all of the command groups recorded on track PO of the magnetic tape to be selected.

After the state of charge represented by block 383 (FIG. 19), central unit 5 is faced with a logical decision represented symbolically by block 384. This logical decision or alternative expresses the possibility that the central unit 5 has a group of generic commands or the group of "selection" commands as load. This logical decision is represented by a conditional jump instruction recorded at the beginning in the first load block.

With the aid of the conditional jump instruction, the central unit 5 can now execute a jump to the cell of the memory 42 which contains an instruction CW in order to select, as described above, the address of the program block recorded in the track PO (Fig. 15), that of the operator corresponds to the command group entered on the keypad 270 , whereby the central processing unit 5 is brought into the state represented by the block 386 (FIG. 19) for loading the generic commands. With the help of this jump, the central unit 5 can jump

execute a cell in memory 42 containing a COP instruction associated with the select instruction group (block 385 of FIG. 19). The central unit 5 executes the jump command to one or the other cell depending on whether the operator has entered a particular processing operation on the keypad 270 or not.

If the operator has not entered a processing operation, the central unit 5 executes a jump command to the memory cell containing the command COP for “selection”. The address of this cell is represented by the second character of the jump instruction. The first command of this group is a command COP directly to the control device 9 of the typewriter 6. With the help of this command, the central unit 5 sets the control device 9 to the receiving state, whereupon it uses the following commands CAP of the typewriter to display the label JOB? feeds. These operations are symbolically represented by block 388 (FIG. 20). The control device 9 it Runs - ¹ H of the input circuit 12 '(Fig. 14) the command appears to print this label to which consequently on the print sheet. The central unit 5 then sets the control device 9 to the symbolic r by the block 389 (FIG. 20) with the aid of a following command COP. transmission state shown.

The operator then uses the keypad 270 (Fig. 14) of the typewriter 6 to input the label or group of characters that make up the desired group of commands. As already stated for κ j in the description of control unit 10, control unit 10 brings about an interruption after each character. The state in which the central unit 5 is now is represented by block 390 (FIG. 20). Thereafter, each Ji character transmitted by the control device 10 is temporarily stored in a cell of the memory 42 (block 391). Upon receipt of each character, the central unit 5 has to make a logical decision represented by block 392, whereby it checks whether the label has been completely fed. The central unit 5 checks in detail whether the last character coming from the typewriter 6 is the fourth character of the mark or not. As usual, this logical decision is represented by a jump instruction caused by the result of the comparison operation carried out by the instruction CFR. The execution of this command is the same as for the logical decisions discussed above.

If the last character received is not the fourth character on the label, the central unit 5 sends a command COP to the control device 9 of the typewriter 6, by means of which it brings the control device 9 into the transmission state represented by block 389. The next character is then fed into the central unit 5, so that the central unit 5 returns to the state represented by block 389. When the fourth character is supplied, the central processing unit 5 checks whether the label supplied corresponds to one of the labels recorded on the track PO of the tape 310 (block 393). The comparison takes place naturally with the aid of a CFR jiatt command, which is repeated until the selected label is recognized

When the operator has made a mistake in pressing the keys for inputting a label instructs the central processing unit 5 to the control device 9 by means of a command COP re-printing of the label JOB? (Block 388) as a result of which the operator re-enters the label.

If the label has been entered correctly, the central unit 5 executes a jump command to the cell of the memory 42 in which the address / 1 ... / 256 is recorded in the memory 7 of the first block of the command group entered. Then the central unit 5 commands this cell of the memory 42 to be read and, with the aid of a command TRA, transfers the address read therein to the cell of the memory 42 corresponding to the second character of the jump commands of the load command group 386 (Fig. 19) perform operations. The address / 1... / 256 of the first command block of the memory 7 to be transmitted into the memory 42 is contained in the cell determined by this character. These operations are shown symbolically in block 394 (FIG. 20). It is thus clear that in accordance with each label entered on the keypad, the address of the first command block can be changed in accordance with the label entered, so that the corresponding block selected by the label in the memory 7 can be transferred to the memory 42. The central unit 5 then transfers the selected block to the memory 42 with the aid of the operations described with reference to FIG. 19 and symbolically represented by block 386 (FIGS. 19 and 20).

In summary, when the printing system starts up, the initial commands (block 381 according to FIG. 19) are first transferred to the memory 42, which read the load commands from the tape memory 7 (block 383), and finally "load" the last-mentioned commands into the selection commands the memory 42 (block 385) if a label has not been selected by the operator. When these commands are loaded, will printing the label find JOB? (Block 388 of Figure 20). Thus, the operator selects a group of work commands by writing a label. The "select" commands select the address of this group between the various groups assigned to the work commands and supply the address to the load commands (block 394). Finally, the load instructions load the selected instruction group into the memory 42 (FIG. 20, block 386), as a result of which they can be executed by the central processing unit 5.

When a text is to be recorded, the operator inserts a sheet of paper over the roller of the typewriter 6 (FIG. 1) and actuates the start pushbutton of the keypad 8. In this way, the central unit 5 is set so that it carries out the initial commands , which writes the load command and the selection commands in the manner described with reference to FIGS. 19 and 20 in the memory 42 (FIG. 2). The selection commands then control the printing of the label “JOB?” By the typewriter 6. Then the central unit uses a command COP to send a command “return to beginning with line transport” to typewriter 6 in a manner known per se.

The operator then enters a label "REGI" (block 410 according to FIG. 21) on the typewriter, which the central unit 5 sets so that in the blocks BP1 ... BP256 of the tape 310 a group of so-called "recording" - Selects commands (block 411) and transfers them to memory 42. These are suitable for presetting the arrangement of the marginal edges and for controlling the recording of the text subsequently written on the typewriter

in the tape store ?. The recording commands supply the central unit 5 with the addresses of the blocks ß1 ... ß256 of the tape 310 ( FIG. 14) in which the typewriter lines or lines of print are to be recorded.

For this purpose, each of the tracks P1 ... PN of the tape 310 contains a special block called a table block. This table block is located in each track at a predetermined point and is accessible by the central unit 5 in the manner described in more detail below by means of an address which is kept unchanged during the entire operation of the printing system. As an example, it is assumed that the table block of each track PX ... PN (FIG. 14) is the respective block β1. The table block is made up of 67 eight-bit characters, so that the first 64 characters contain a total of 512 bits. These bits are grouped in pairs, each of which is assigned to a data block Bl ... ß256 . More specifically, associated with the first pair of bits of the data recorded on the track Pl table block B 1 to the same block B 1, the second pair and so on so that the pair 256 associated with the block ß256 the block Bl ....

Since the two bits of these pairs can have four configurations, this configuration is possible with each an information location is connected to the corresponding block. More precisely is the meaning of these information words summarized in the table below:

in

First bit Second bit Meaning

0
0
1
1

Block free and recordable

Block occupied and recordable

Block free, but not recordable
Block cannot be used

The first corollary indicates that the block Irei and unrecognizable lsi and its sequence can be occupied by the data. The / broad combination r indicates. dal! the block occupied, but by means of erasure of the data contained him ■ n is aulzeichnungsräliig. The third combination indicates that the block of data is free, but cannot be recognized, for example, due to a change in the magnetic material of the tape 310 -, or as a result of abrasion. This prevents any part of the I c.xtes from being lost because it is recorded in a destroyed block. The last combination is used to indicate that the block cannot be recorded if its content is not desired to be changed, for example in the table block's fill.

After the first 64 / calibration of a table block, a group of further three characters is recorded, which are the same for all table blocks. The first of these characters indicates a COP selection command. the. we mentioned above, a track / M ... / - "V of the magnetic tape 310 can select COP This command is used, as will be explained below can hi closer to the first free and up / eiehnungslahigen block select containing track.. The second / calibration of the group of three gives the address of the first free and recordable block, while the third gives the label of the tape cassette to which this block belongs and to indicate recordable blocks of the tape, while the third character can be used in the case of simultaneous use of a plurality of cassettes and is not considered here brought up to date.

The first of the »Aufzcichnungsw commands is a selection command COP directly to the control device 10 of the tape memory 7, by means of which the track P1 of the tape 310 is selected and which brings the control device 10 into the read state 358 (FIG. 18). If the address corresponding to the table block B1 of the track P1 is recognized, which, as mentioned above, cannot be changed, the "Aufzeichmingsw" commands control the reading of the table block. This state is represented symbolically by block 412 (FIG. 21). The table block ßl corresponding to the track P \ is consequently transferred to a zone of the memory 42 by the central processing unit 5.

A jump command contained in the "recordw" commands then causes the central processing unit 5 to execute a jump to the cell of the memory 42 in which the first character of the indicator has been recorded. This cell is always the same regardless of the table block, since the characters defining the indicator have a fixed location in the table block which, as is known, is always serially recorded in the same zone of the memory 42.

Since the first character of the indicator is a command COP for selecting the track containing the first free and recordable block, the address of this Ii lock is also recorded in the next cell of the memory 42 , so that the first free and recordable block of the tape memory 7 is marked in this way. This state is symbolically represented by block 413 (FIG. 21).

With 11 il Ic of the selection command COP , the control device Kt of the tape store 7 is brought into the address reading country (block 414) in the same way as described with reference to FIG. 9. The selection of the free and recordable block indicated by the indicator takes place in the manner described with reference to FIG. 18 (block 415 according to FIG. 21).

Starting from the address of the free block, the central unit 5 then selects a series of 23 free and recordable blocks in the following manner. With the aid of a command 77? C, it transfers the address indicated by the indicator, increased by one unit, to a cell of the memory 42. This new address determines the data block which follows the data block determined by the indicator. The central unit 5 then checks on the basis of the content of the table block ßl whether the data block determined by this address is free and recordable. This is because it uses a CDC command to check whether the bits of the table block corresponding to this address both have zero values.

If the block identified by the new address is occupied, according to the result of the comparison, bit E = 0. The central unit 5 then executes an IRC command, by means of which it transfers the address of the occupied block, increased by one unit, to another

Cell of memory 42 transfers. The same operations as described above are then repeated to judge whether the block with this last address is free and recordable. If the result of the comparison is positive (bit E = 1), the central unit 5 records the new address in the memory 42 in two stages on. In the first stage, the central unit issues a conditional jump command to a memory cell in which a command TRL is recorded. In the second stage, it uses this command to transfer the address given by the indicator to the memory cell following the last cell occupied by the table block, so that the second block of the 23 blocks that are searched for is recorded. The operations just described are summarized by block 416 (FIG. 21). The operation is repeated for the remaining blocks, which may be located in separate locations on the tape 310. In this way, the central unit 5 selects a group of free and recordable Dalenblocks. The number 23 for these blocks has been chosen because this is usually the average number of lines of writing contained on a typewritten sheet.

If the number of free and recordable blocks is less than 23, the central unit 5 goes over to reading the table block belonging to the next track with the aid of the next selection command COP, so as to always deliver 23 free blocks. In order to determine whether the free blocks are less or more than 23, the central unit 5 transfers the table block corresponding to the data block following the block determined by the indicator into a cell of the memory 42 in order to check with the aid of the execution of an instruction CDC whether these bits are all zero bits and 46 in number. If this is the case (logical decision 425), ie if at least 23 free blocks are present, the central unit 5 carries out the operations described above with reference to block 416, while otherwise it jumps to the address reading status (block 414) to read the table block of the next track to read.

The central unit 5 then sets the control unit 9 of the typewriter 6 to the receiving state with the aid of a command COP. Then it supplies the address of the first free block by the following command C / tPaer input circuit 12 '(Fig. 14). The input circuit 12 'then commands the typewriter 6 to print this address on the left edge of the sheet under the label REG1 in the manner described above (block 417 of FIG. 21). With the aid of the selection command CW recorded in the first character of the indicator, the central unit 5 brings the control device 10 of the tape storage device 7 into the state for receiving and selecting the free address (block 418). Then the central unit 5 feeds a group of four spaces to the control unit 9 of the typewriter 6 with the aid of commands CAP in order to cause the typewriter carriage t> o to advance by four steps. At this point, the operator can use the keypad 270 of the typewriter 6 to enter a code which corresponds to an operation which the central unit has to carry out during the subsequent printing of the text on the printing or writing line. The operations that the central processing unit 5 can perform include determining the right edge of the line, centering and underlining.

The operator operates to cause the codes corresponding to these operations to be entered the one-step backspace key of keypad 270 (logic decision 417 'of Figure 21) which causes the carriage of the typewriter 6 moved back one step.

Then the control unit 9 of the typewriter 6 supplies the central unit 5 with the code for “one-step backspace” with the aid of a command CDP. The central unit 5 for its part recognizes this code with the aid of the circuit 98 (FIG. 13) of the memory input circuit 47 under the control of a command CFR. As a result, the central unit 5 supplies the control unit 10 with a command CDP which adjusts to the transmission state. Since the second character of the command CDP is an address of the cell of the memory 42 in which the character coming from the control device 10 is to be recorded, this character is not recorded in the memory cell following the cell in which the address of the print line is to be recorded had been recorded.

The operator can then select one of a group of alphanumeric keys on keypad 270 Press the keys that are assigned to the operations that the central unit 5 is to carry out. The control unit 10 then leads the code corresponding to this key to the central unit 5, which this code in the selected Cell of memory 42 (block 417 ").

In detail, the operator presses the key of the capital letter L after the "one-step backspace" key to determine the right edge of the line, followed by as many spaces as there are characters from which a desired print line is to be formed. The central unit 5 receives the printed character L and transfers it to a predetermined cell of the memory 42 in the manner described above. The command following the command CDP , by means of which the character L is recorded in this way, is a jump command to another cell of the memory 42 in which a command CFR is recorded. With the help of this command, the central unit 5 compares the character L with the possible command characters of the printing system.

When this character is recognized, the central unit 5 counts the spaces after the character L with the aid of successive operations controlled by a series of commands TRC with the aid of a further jump command. A constant expressing the space increased by one unit is transmitted each time. If a special value, for example 00000000, has been selected for this constant, the final constant corresponds to the number of characters entered for this print line at the bottom of the count.

With the aid of a further command TRC , the central unit 5 transfers this number to a predetermined cell of the memory 42, as a result of which the length of the line remains recorded in the memory 42.

If the operator has further commands, for example for centering titles, for underlining etc., it re-enters the one-step backspace to which pressing the respective alphanumeric key follows. In a manner corresponding to that described above the code corresponding to this alphanumeric character is stored in a corresponding cell of the

chers 42 is recorded instead in the cell following that in which the address of the line is recorded is.

When writing the character L or the other alphanumeric characters assigned to the commands, the typewriter carriage catches up the space of the one-step backspace and is thus in the start of the line position.

Now the operator enters the characters of a line of the text to be recorded on the keypad 270 (FIG. 14), which is then printed on the sheet next to the address of the block in which this line is to be recorded and advanced by four steps. These characters are now transferred serially in the manner described above into a first register 42 '(FIG. 2) of the memory 42 which is reserved for this transfer (block 419 according to FIG. 21). At the end of the line, the operator presses the line feed carriage return button, as a result of which the carriage returns to the initial position. In addition, the associated code is recognized by the central unit 5 with the aid of a command CDC which, as usual, brings the central unit 5 into a next working state with the aid of a conditional jump command.

In this working state, the central unit 5 ensures the transfer of the line recorded in the register 42 '(FIG. 2) to the second register 42 "of the memory 42 and the completion of the data block contained therein with the function characters and the start of the search for the block of the band to be 310, in which the finished block finally recorded. More specifically transfers the central processing unit 5 by means of the TRA command in the first three characters of the block a COP command for track selection, the address of the next free block and the label corresponding to tape 310 for determining the order of the blocks in the following processing operations, for example for successively writing the different lines of a given text the command TRA for any block without change de s second character of the command can be used which determines the address of the cell from which the three function characters to be transmitted must be taken. Since the data blocks are then also recorded in the same cells of the memory 42, the third character of the command TRA is also always the same.

By means of a further instruction TRA executed afterwards, the central unit 5 then transmits the number of print characters which the block that has been recorded in the memory 42 can contain to the fourth cell of the data block. The central unit 5 then uses a next command TRA to transfer the currently entered number of characters to the fifth cell of each data block. This number is counted by the central unit 5 in the same way as the number of spaces described above. In this case, however, the command to initiate counting is given by the sign "carriage return with line transport".

The central processing unit 5 then transmits to the sixth cell of the block the code of the operation to be carried out on the line (centering, underlining, etc.). Finally, the central unit 5 calculates in any known manner the parity symbol resulting from the entire data block and transfers it to the seventh cell of the block itself. The operations just described are shown in abbreviated form in block 420 (FIG. 21)

Simultaneously with the completion of the block just described, the central unit 5 uses a selection command COP to bring the control device 10 of the tape memory 7 into the state for reading the tape 310

ίο (block 358 according to FIG. 18). In this way, the control device 10 causes the search in the memory 7; after the address of the block in which the print line previously entered on the keypad 270 is to be recorded in the manner described above. While the control device 10 is searching for this address, the operator enters the second print line on the keypad 270 , which is transferred to the register 42 '(FIG. 2) of the memory 42 in the manner already described.

The central unit 5 thus simultaneously with the completion of the block and corresponding to the first print line, the recording of the block corresponding to the second print line in the register 42 ′ and the search on the tape 310 for the block in which the block recorded in the register 42 ″ and The block corresponding to the first print line is to be recorded by causing an interruption in the completion of the data block on a case-by-case basis The central unit 5 then interrupts the completion of the data block recorded in the register 42 ″, which is in progress, in order to receive the character coming from one of the two control units 9 and 10. The central unit 5 then resumes the completion in progress.
In detail, the time that the control unit changes

• to 10 needed to get on the tape 310 after the block search in which the content of the register 42 ″ of the central unit 5 is to be recorded, accordingly the location of the block on the tape. This time can be at most approximately equal to the average time that the operator needs to enter the next line on keypad 270. Be it notes that controller 10, as previously described, is reading the addresses of those on the tape 310 takes recorded blocks in sequence,

so until it recognizes the address received from the central unit 5. Hence the one to read the addresses required maximum time depends on the feed speed of the tape and its length. if When the operator has finished entering the second print line, he presses the "carriage return" key again with line transport «. As a result, the central processing unit 5 carries out the transmission of the completed, the first print line in the register 42 "of the memory 42 corresponding data blocks in the tape memory 7 and

eo the transfer of the second print line from the register 42 'of the memory 42 to the register 42 ". The central processing unit 5 then returns to the recording state represented by the blocks 417 and 418 according to FIG. 21. The operator can now enter the The third print line begins, as a result of which the operations described above are repeated These operations are symbolically represented by block 421 (FIG. 21).

When the operator finally led entering the text to an end, it shall inform the central processing unit 5, the end of the text with this purpose it operates after printing the last address, the one-Rücktastc and then the key for the capital letter E on the keypad 270 (logical decision 423). The central unit 5 then recognizes the code assigned to this key and consequently uses a command TRA to transfer the first three characters of the block assigned to the last print line into the cells of the memory 42 in which the 65th, 66th and 67th characters of the table block are recorded are.

As described above, after the operator has entered the label REGI on the keypad 270 , the table block has been recorded in a register of the memory 42 , as a result of which the indicator is thus updated and again the address of the first contains free and recordable blocks (block 424 of FIG. 21), so that when a subsequent text is to be recorded, the central unit 5 again supplies the address of this block in the manner described above. The second and third characters of the command TRA are always the same regardless of the table block recorded in the memory 42.

Since the table blocks are always recorded in the same cells of the memory 42 , the third character of the command TRA, which represents the address to which the content of the cell identified by the second character is to be transferred, is always the same and therefore for everyone Table block valid. Accordingly, the second character of the command always remains unchanged, since the addresses of the free blocks are always recorded in the same cells of the memory 42.

It is therefore clear that the central unit 5 has the address of the first free and recordable Blocks supplies, which controls the recording of a text line by line, the address of the in each data block next data block and the code of the print line recorded in this block when they are printed the type of operation to be carried out and the value of the indicator is updated after each recording.

It should also be noted that if the operator sees a typo while printing a line, he presses the one-step backspace key. The command character assigned to this key is recognized by the central unit 5, the interruption associated with this command causing the central unit to prevent the multiplication of the addresses in the manner described, as a result of which the character entered thereafter replaces the one previously recorded in the memory 42 Sign occurs.

Finally, if the operator intends to underline one or more words on a line of print, he presses the one-step backspace key and then the key corresponding to the letter S after printing the address corresponding to that line. She then records the text of the line and, when reaching the word to be underlined, presses the underline key instead of the space bar. Then she records the word or words to be underlined. At the end of the word she presses the underline key again instead of the space bar. The codes corresponding to the underline key are thereby recorded in the cells of the memory 42 so that they identify the beginning and the end of the words to be underlined.

After the operator has made all corrections or changes to the content of the text and the appropriate error corrections, he can order the printing of the processed text in "fair copy". In order to do this, she actuates the start key of the control keypad 8, what, as described above, the printing of the label JOB? The operator then enters the label EDfTein on the keypad 270 (FIG. 14), through

ίο the central unit 5 is recognized. As a result, a group of commands called "print" commands are transferred from tape memory 7 to core memory 42. These operations are illustrated schematically by block 460 (FIG. 24). After the EDIT label, the operator enters on keypad 27C the label corresponding to the address of the beginning line of the first line of text to be printed. This operation is symbolized by block 460 ' (Fig. 24).

The first command of the group of print commands is a command COP directly to the control unit 11 of the control keypad 8. In this command COP , the second character is formed from eight bits with the level 1, this command, as described above,

2 ~> causes the indicator lamp of the keypad 8 to light up. In this way, the operator is made aware that he must change the print sheet. Now she inserts a "fair copy" sheet over the roller of the typewriter and presses the break key. The interruption brought about in this way causes the lamp to go out and also causes the central unit 5 to execute a jump command to a memory cell assigned to the keypad 8. In this cell there is a COP instruction to choose from

y> recorded directly to the control device 10 of the tape storage device 7. The selection command COP loads the address entered on the keypad 270 into a predetermined cell of the memory 42 and brings the control device 10 into the address reading state. If the address recorded in this way in the memory 42 is recognized (block 462), the data block thus determined is transferred from the tape 310 into a predetermined group of cells in the memory 42 (block 463).

With the aid of a command CFR , the central unit 5 reads the sixth character of the block transferred to the memory 42, which character specifies the particular operation to be carried out on the line (logical decision 464). If the sixth character is zero, the central unit 5 carries out the so-called "alignment" of the line in a manner which will be described in more detail below (block 465). Then, with the aid of successive commands CAP, the characters are fed to the control device 9 of the typewriter 6 (block 466), which, in the manner already described, ensures that the actual line is printed.

If the sixth character of the block is not zero, the central unit 5 compares this character with the possible to perform the different on the line

bo-generating operations assigned and in predetermined Cells of memory 42 along with the group of print commands recorded characters (block 467). If the operation to be performed is centering or underlining the characters of the line,

b5, the central unit 5 carries out these functions (blocks 467 'and 467 "). After these processing operations, the characters are transferred to the control unit 9 of the typewriter 6 with the aid of successive commands CAP atm

fed to be printed.

At the end of each line, the central unit 5 checks whether the next block contains the end-of-text character E (block 469). If this character is not recognized, the central unit 5 determines via the memory 42 whether or not the printed line is the last on the page (block 475). If it is not the last line, the central processing unit 5 repeats the same operations, as described, from block 461 for the next data block, the address of which is identified by the first three characters of the preceding block, so that the central processing unit 5 in turn the Printing of all lines of the recorded page.

It should be noted that the cells of the memory 42 in which the first three characters of each block are recorded are always the same, since all blocks are consecutive in those indicated by the preceding Block occupied same cells are recorded. This is how the addressing operation is performed each block in FIG. 8 always with the same commands.

On the other hand, when the last line of the page has been printed, the memory 42 reports the end-of-page status to the central processing unit 5 (logical decision 475). The central unit 5 puts itself into a waiting state (block 468) and, with the aid of a command COP, causes the display lamp to light up again directly to the control unit 11 of the keypad 8. In this way, the operator is made aware that he must change the sheet. The central unit 5 also loads the address of the first line of the new page into the memory 42 (block 460 "). After the sheet has been replaced, the operator presses the interrupt button again, as a result of which the operations for printing the new page are repeated.

Finally, when the central unit 5 recognizes the end-of-text character E (logical decision 469), it brings about the halting of the typewriter 6, as a result of which the system returns to the halted or idle state (block 476).

As described above, each data block contains function characters related to the length of the print line to align the lines. More precisely, the fourth character, hereinafter referred to as NI , indicates the number of characters that the block can contain, while the fifth character indicates the number NE of characters currently contained in the block. When a data block is transferred to the central processing unit 5 (block 463 in FIG. 24) and its sixth character is zero (logical decision 464). the central unit 5 compares with the aid of a command CFR

u35 fourth üTlu lüThic

ucS DiOCKS initcifiändci the central unit 5 starting from the seventh character of the block with the aid of a command CDC, whether the character of the data block is not a single space (logical decision 471). If this character is not a single space, ie if it is a print character or if it is followed by a further space key (bit E = 0), the central unit 5 executes a jump command to a cell of the memory 42 in which a command TRA is recorded by means of which it transfers the checked character into a predetermined cell of the memory 42 (block 472).

If the character is a space, the central unit 5, after the space has been transferred, executes a jump command to a memory cell in which a further command TRA is recorded. With the aid of this latter command, a further space is transferred into the memory cell following the cell into which the first space has been transferred (block 473). The characters that complete the data block are then transferred into the following cells, as has been described with reference to block 472. After the transmission of the data has ended, the central unit 5 transmits the function characters to the corresponding cells. In detail, the character NE is transmitted incremented by one unit (block 474).

With the help of these operations, the central processing unit has the data block from the first register of memory 42 into a second register of memory 42 transferred, but with the addition of a further space after the first space. To this The print line has been widened by a space.

The central unit 5 then again compares the characters Nl and NE with one another (block 470). If these characters are not the same, it transfers the block from the second back to the first register, inserting another space in the position following the second recognized space, which is the first individual space. The central unit 5 repeats this process until the character NE is equal to the character NI . When this occurs, the line is printed with the right edge in alignment (block 466).

For example, if the storage capacity of a data block is sixty characters (Nl = 60) and it contains fifty-seven characters (NE = 57), the CPU 5 carries out the alignment in three steps, as shown in the table below, in which : ND is the difference between Λ7 and NE, S \ ... SS is the number of spaces between the first and the second word of the line or between the second and the third word, etc.

(Logical decision 470 of Figure 25). If these characters are the same or equal, the block is commanded to be printed from the seventh character, as a result of which the function characters are not printed (block 466). This is achieved with the help of the commands COP directed to the control device 9 of the typewriter 6, which bring the typewriter 6 into the receiving state, and with the help of commands CAP , which transfer the characters from the memory 42 to the control device 9 of the typewriter 6. The second character of the command CAP specifies the address in the memory 42 corresponding to the seventh character of each block.

If the comparison between the fourth and fifth characters of the block is negative (bit E = 0), checked

step Λ7 NE ND 51 52 S3 54 55 0 60 57 3 1 1 1 1 1 1 60 58 2 2 1 1 1 1 2 60 59 1 2 2 1 1 1 3 60 60 0 2 7th ? 1 1

If, after inserting a space after all spaces in the print line, the

Difference ND still deviates from 0, the central unit 5 increases the comparison elements with the space between the words in such a way that the two successive spaces are now identified. In this way, it inserts a space again between the words making up the line '> by repeating the same operations as explained in FIG. 25 have been described. As a result, with the aid of these operations, each line is printed with the right edge edge aligned with a predetermined position.

For example, if at the end of the length of the line has not been reached after the addition of two spaces to the space between the words of a sentence, in which the text ends well before the end ι ^r> of the row, the process of aligning is set.

As described above, the end-of-line position can be changed by changing the character NI . By appropriately changing the character Nl , for example, a space can be left in a text for inserting a figure, or a text can be printed in a large number of columns parallel to one another, etc.

According to yet another variant of the invention, the various programs of the printing system can be selected by the operator by only acting on the control keypad 8. In this case neither will the label JOB? nor the various labels characterizing the corresponding programs (REGI, MODI , etc.) are printed by the typewriter 6.

According to yet another variant of the automatic printing system, the function characters described above, such as the characters J5 "L" (line length), "S" (underlining), "E" (end of text) etc. can be used to facilitate their use by the operator to be changed.

Table A below shows a brief example of how the system works with the most important operations described above. In detail, Table A shows the recording of a short text under the control of the REGI command group. Table B shows this text in "fair copy".

After printing the label / 0.S ?, which is achieved by pressing the start key of the keypad 8, the operator enters the label REGI on the keypad 270 of the typewriter 6, which generates the automatic printing of the label MAC6 , which represents the address provided by the indicator of the first free and recordable data block.

The carriage then moves four steps forward, whereupon the operator presses the "C" key after pressing the carriage return key to indicate that the entered print line should then be centered. After the operator has entered the print line on the keypad 270, he presses the key for carriage return with line transport, which simultaneously causes the carriage to return to the beginning of the line, the printing of the address MACI and the subsequent advance of the carriage by four steps

The operator then enters the other print lines that are recorded in the blocks determined by the addresses MAC1 to MACC. ω

In the MACD line, the operator presses the one-step backspace key and the E key to display the end of the text.

Table A.

REGI

MA C6

MACl

MACZ

MACB

MACC

MACD

NEARLY

MACS

REGI

MS C \

MSCl

M5C3

MSCA

JOB!

MODES

JOB! EDIT

General validity of the system

This selection of program steps is neither complete nor definitive.

From a work standpoint, we are essentially interested in the programs.

E.

Completely still definitely.

It is particularly noted that when considering the use of word processing the planning department defines new programs.

IMACS MSCX MSCA MACB

MA C6

The operator then reads through the text and finds that he has written the word "definitive" instead of "definitely" in the line M ACS. To make the correction, she presses the start key again so that the label JOB? printed out again and now the label FAST is entered.

When the car has returned to the beginning, the operator presses the "one-step backspace" key four times and then enters the MACS address on the keypad. Then she uses the break key to start pressing the first word of the line, whereupon she presses the break key again so that the second word is printed, and so on Instead of pressing the break key, the operator enters the word "definitely", which is consequently recorded in place of the wrong word.

If the operator wishes to insert a paragraph in the text that has just been recorded, he presses the start key, which starts the printing of the HtikcitS JOB? generated. Däfäüf you enter under the label REGI , which generates the printing of the address MSCl. Then the operator enters the lines of insertion from MSCI to MSCA . Then she presses the interrupt key again and gives JOB? After the label. the MODI label. This causes the carriage to return to the beginning with toe transport, whereupon the operator enters the letter / followed by the addresses M4CS, M5Cl, MSC3 and MACB . The MACS address is the address of the line after which you want to insert the new paragraph. M5Cl and M5C3 are the addresses of the first and the last line of the paragraph to be inserted. MACB is the address of the line from which he wishes to resume the recorded text. Then the operator presses the sub again

break button and after the label has been printed JOB? the EDIT label followed by the address Λ / 4Γ6 corresponding to the first line of the text.

Table B.

Finally, the operator changes the sheet and commands by pressing the break button again is pressed, the printing of the »fair copy text shown in Table B.

General validity of the system

This selection of program steps is neither complete nor definitive.
It is particularly noted that at
Considering the application of word processing the planning department new programs
set.

From a work standpoint, we are essentially interested in the programs.

The heading has now been printed centered; the remaining lines are z. B. to a total of 45 characters to align. The first line of the text is already aligned. In the second line adds the central unit 5 insert two spaces in the two spaces between the words, whereupon the alignment process is finished. Eight spaces (additional spaces) are inserted in the third line, namely four in the first space and one in each of the remaining four spaces, while in on the fourth line just insert a space in the first space, and so on for the remaining lines.

For this purpose 1 1 sheet of drawing

Claims (4)

Patent claims: 1. Word processing system with a device for entering the text line by line, each line of text having a line length that does not exceed a desired, predetermined line length assigned to it, a memory for storing the entered text on a recording medium, a device for automatic line exclusion after input a corresponding command signal for the line exclusion by comparing the actual length of each entered line with the specified line length and, if they do not match, is brought to the specified length word by means of corresponding word space expansion, and a device for line-by-line printing of the stored text in excluded form, characterized in that, that the input device (6, 8) has a manually operable device (L) for inputting the predetermined line length, which corresponds to the total number of thickness elements for each to be expressed in excluded form Line corresponds to; that the recording medium (310) is subdivided into a series of memory blocks (B1, B2, etc.), each of which can store an input line of text and, in addition, a memory location for storing the specified Jo line length, represented by a number, of the line stored in the block and contains a further memory location in which the counting device (TRQ determined by one of the thickness elements of the characters of a text line) can be stored, a device (470) responding to the command signal for the line exclusion for comparing the two in the two additional memory locations of each memory block, and a device which responds if the two numbers do not match, with which empty thick elements can be added to word spaces distributed along the entire line by relocating the relevant line in a free register in the memory and this re-storage process is repeated with the addition of further empty thickness elements until the total number of thickness elements of the line counted by the counter (TRQ) corresponds to the specified line length. 2. System according to claim 1, characterized in that the line to be adjusted is transferred from the corresponding memory block (7) to free registers of the core memory (42) and that the device responsive to the comparison device (470) when the numbers do not match Search device (CDC, 471, 472) for searching the following space between words by sequentially indexing (472) the line stored in the free register> o star (42); an inserting device (TRA, 473) for inserting a further empty thick element code in addition to the determined inter-word code whenever a inter-word code is determined, and an incrementing device (474) for incrementing the number (NLi) by a units position which indicates the actual line length of that line, which is stored each time a blank thickness element code is inserted by the insertion device, the comparison device (470) disabling the search device (CDC, 471) and the insertion device (TRA, 473) if the numbers (NI, NE) of the line length match. 3. System according to claim 2, characterized by a conditioning device which becomes effective upon completion of a first sequential indexing of the line stored in the registers of the core memory (42) by the search device (CDC, 471) in order to search for individual inter-word codes, and, if the line length numbers still do not match, condition the searcher to perform a second indexing of the line to search for adjacent word space pairs. 4. System according to claim 3, characterized by a device for shutting down the device which responds to the comparison device when the numbers do not match when the second indexing of the search device (CDC, 471; TRA, 472) is ended if the numbers (NI, NE) correspond to the line length are still different.