DE2262755B2 - Digital compensation device - Google Patents

Description

for the compensation voltage (Uk) of a. Such a compensation device is the

the consistency of the meter contents marked German interpretation document 1448 920, class 42 d,

The resulting output signal (k) can be found on the digital 25 10/00. Pre-published in niciit

gk-ichsschalt (DV) is determined and that as An.neldu ig P 22 60441.7 is also for a

Current or voltage source a direct current compensation device of the aforementioned

or DC voltage source is used, Aus Art is a digital comparison circuit for the content

output voltage or output current via one of the counter and an additional counter for continuous

from a carry pulse (ü) of the highest so running count of the output pulses of a clock

kade of the clock pulse counter (Z 2) controlled generator is provided as well as an interrupter switch

switch (Sl) in the cycle of the counting time of the Taktim- for the compensation voltage, its closing duration

pulse counter (Z 2) is pole-changing and the zero of one the match of the counter contents

amplifier (NV) a marking output signal of the digital

Switching rectifier (54) is downstream. 35 equivalent circuit is determined.

2. Digital compensation device according to An The invention was based on the object of a claim 1, characterized in that before the digital Kompensationsein input of the null amplifier (NV) described above, a switch direction the advantages that an alternating current or (S3 ), the beginning of which the closing period is delayed by a few alternating voltage supply the transducer provides clock pulses compared to the beginning of the counting of the clock 40 and the compensator, with the advantages of a pulse counter (Z 2) and whose direct current or direct voltage supply is delayed from the transfer pulse of the high-one .

1st decade of the clock pulse counter (Z 2) controlled This goal is described in the introduction

is. Facility thereby achieved), ciaß according to the invention

3. Digital compensation device nor application, as known per se, a digital comparative claim 2, characterized in that the circuit for the contents of the counter and a to-close duration of the switch (S 3) is equal to a complete counter is provided for the continuous counting of the number multiples of the period of the network change impulses of a clock generator, voltage is. and that the closing time of a breaker switch

4. Digital compensation device according to An 50 for the compensation voltage of one of the claims 1 or one of the following, thereby marking agreement of the counter contents, that the start of the closing time of the input signal of the digital comparison circuit breaker switch (S 2) for the compensation is correct is and that as a current or voltage source voltage by a few clock pulses compared to which a direct current or direct voltage source is used, Start of counting of the clock pulse counter is delayed. 55 their output voltage or output current

5. Digital compensation device according to one of a carry pulse of the highest claim 1 or one of the following, characterized by the clock pulse counter controlled switch indicates that the output of the clock pulse in the clock of the counting time of the clock pulse counter (Z2) a pre-clock counter (VZ ) can be switched downstream and the NuU amplifier is one in the same tet. 60 Clock controlled reversing rectifier connected downstream

6. Digital compensation device according to the on is.

claim 1 or one of the following, thereby with hike the measures according to the invention wer-

indicates that the control of the switch allows the advantages of an alternating current supply, ihsbe-

(Sl ... S 4) controlled by a logic circuit, the freedom from thermal and contact voltage

is the carry-over as input variables and the possibility of error-free switchover

pulse (ü) of the highest decade of the clock pulse counter of the measuring device on several measured

lers (Z 2), the carry pulse (v) of the pre-clockmer with the advantages of a direct current supply delayed (VZ) and the equality of the counter contents. These are in particular in the inde-

3 4

supplied dependence of the circuit of phase errors and in the 53 a Nullwrstärker NV pre simple suppression of power frequency option is switched on. At the output terminals of the zero-interference interference in the compensation circuit. The amplifier is connected to a second pole-changing switch 54. Its clocked rectification of the output terminals in the zero-gain amplifier are via a low-pass filter TP with the differential voltage having the advantage that any voltage-frequency zero drift of the zero-point amplifier with respect to the converter SPF connected. The pole-changing switch 54, which is the same as the compensation device, is operated synchronously with the pole-changing switch 51, so it can be. The drift voltages are in fact that it acts as a contact rectifier. The output voltages converted from a low-pass filter of the voltage-frequency converter 5PF before the voltage-frequency converter go back] - io are to be connected to the forward and reverse inputs of a th. As a zero amplifier can be connected from this pulse counter Zl. The counter input of a reason a relatively cheap operational amplifier Ver clock pulse counter Z 2 is to find the output of a clock reversing generator connected to a pulse train with

In a preferred exemplary embodiment, the earth repetition frequency / 0 supplies the decade outputs Find liei before the zero amplifier output a switch 15 the counters Z1 and Z2 are with comparison inputs

ter, the start of the duration of which is connected by a few clock pulses of a digital comparison circuit DV,

compared to the start of counting of the clock pulse counter An output of the comparison circuit DV, the one

is delayed and its closing date from the consistency of the counter contents zl and ζ 2

carry pulse of the highest decade of Taktimpulszäh- feels marking pulse k, is sized to the input is controlled Suitably, the locking time "o a switching control logic Lo connected. An over-

of the switch equal to an integer multiple of the momentary pulse ii arrives via a connecting line

the period of the AC mains voltage selected the highest decade of the Tiiktimpuls counter Z 2

The start of the closing duration of a second input of the switching control logic Lo is also advantageous. Interrupter switch for the compensation span- Another input of the switching control logic is delayed by a few clock pulses compared to the counting as transmission pulse ν of a pre- clock counter VZ at the start of the clock pulse counter. Led to this. One output of the switching control logic controls the purpose in one embodiment of the invention - at the same time the two pole-changing switches 51 and 54. the control of the switch S 2 or 53.

The control of the various switches is conveniently controlled by a logic via the switching control, which is used as an input logic Lo every time the clock pulse counter Z 2 input variables the carry pulse of the highest de- of the clock pulses of the clock pulse generator TG kade of the clock pulse counter, the carry pulse of z2 to its counter end value _MflJt is incremented and Vortaktzählers and the equality of the Ziihlerinhalte ü outputs a carry pulse, changing the polarity of the labeling output pulse of the digital encryption 35 supply voltage or the supply current, the same circuitry receives. In FIG. 2 a is the time course of the thereby

The invention is illustrated on the basis of two figures, alternating feed currents IS ' and / 5 ".

explained here. posed. Due to the finite transmission band

F i g. 1 shows an embodiment of the invention wide of the current transformers TR 1 and TR 2 and because of

as a block diagram. 40 of the cable and winding capacities solves every poly

In Fig. 2, several diagrams are shown together for short-term transient settling processes,

represents the voltage forms at selected switching as shown in FIG. 2 a and in FIG. 2 b also for

points of the embodiment according to FIG. 1 the measuring voltage Um is shown. Vm provides

let know. The last diagram is a circuit diagram of the sum of the output voltage

diagram. 45 voltages of the DMSl and DMSl transducers

In the embodiment of FIG. 1, two are shown. On the basis of cable capacitances and the transducer DM51, DMS1 , the internal resistance of the transducer is, like those consisting of bridge circuits, the feed of which is shown in FIG - Vm no longer steep. As a comparison with the converter TR 1 with currents / 5 * are fed. The 50 F i g. 2 results, the zero rate is also in its measuring diagonal of the measuring transducer DM51 and the phase position with respect to the supply currents / 6 different strain gauges 2 are connected in series. The ones on the diagonals. The sum voltage lying after a decay time of the transient processes len is denoted by Um. however, the amplitude of the voltage Vm strictly This sum voltage is opposite a switched Kompcnsations- the sum of the upset of the Meßgrößenaufspannung Uk, the contractor on a grain 55, and the feed stream pioportional.
compensation resistance R drops. The compensation via the switching control logic Lo is the switch S 2 resistance /? is connected to the secondary winding of a second current transformer TR1 via a changeover switch S 2 to the secondary winding of the resistor R ' , in which the clock pulse counter Z 2 can be connected, through which a current / 5 "flows. A content like the counter ZI has and thus the second contact of the switch 52 is on a: 60 digital comparison circuit DV with a pulse k resistor i? ', which alternately reports the coincidence of the counter contents to the switching control with the resistor R in the secondary circuit logic Lo via the switch. The arithmetic The mean value VIc of the converter TR1 can be switched on. The compensation span primary windings of the current converters TR 1 and TRl voltage Uk obtained in this way, the time course of which is again shown in FIG directly proportional to the momen direct current source. In the primary windings the tan counter contents zl of the counter Zl related to the Str om / 5. The difference between the voltages Um and the maximum counter content zl _{max of} the clock pulse Uk is transmitted to a counter switch Z2 via lines Ll and Ll.

5 6

In Fig. 2d the time course of the voltage is switched. This is in the preferred embodiment

voltage Vk ' shown, which in the switching pauses of the example of the invention by the pre-clock counting

Switch 52 at resistor R ' drops. It is effected by a German VZ , which is in front of the output of the clock pulse

Lich can be seen that the transient processes within the counter Zl is switched. The advance cycle counter VZ is

run half of these switching pauses and thus the down 5 together with the clock pulse counter Zl from the over-

can no longer affect the same result. moment pulse ü of the highest decade of this counter

The interrupter switch 53, the set of the switching to zero and counted by the control logic within Taklimpulsen Lo at the same moment as the formwork of time At to its final value zV _{m "s.} Is ter 52 about the time At in relation to the transfer time of the counter content ζ V _ftm reached, then moved from Vorpunkten the supply current durchgeschal- io clock counter VZ a pulse ν is tet to the switching control logic is given over an entire query clock Lo and then the switch 5 2 switched and the clock pulse counter Zl for reading

I of counting pulses from the clock generator TG

TA = zl _mnx - given. In a simplified way, the im-

^f0 15 pulse μ also derived from the clock pulse counter Zl

as soon as the highest

until the next carry pulse ü of the clock pulse-valued bit was set. The pulse ν is then switched through to the counter Zl. The zero amplifier NV, produced without a Vortaktzähler when the Taktvordessen is input of the switch 53 receives DEM pulse counter Zl to its final value zl _{m "x} counted by the in F i g. 2 e reproduced difference span 20 is and then a zero-setting carry pulse voltage Δ U, which also delivers free of influences.
Phase error and transients is. The switching of the switch delayed by A t

In Fig. 2f, the switch-on and switch-off times of the 52 has the decisive advantage that transient

Switches 51 ... 54 in a switching time diagram, processes and phase delays have completely subsided.

compiled. It can be seen from this that the 25 are gene, if with the compensation process

Switch 52 delayed by At = ti - / 0 compared to when the query date TA is started,

the switching times iO, / 3, i6, etc. of the storage · "? - Preferably, the digital compensation device can

stromes / 5 is actuated and used on the resistance R through- put on a digital scale.

For this purpose 2 sheets of drawings

Claims (1)

marking output pulse (Λ) of the digital claims 1. Digital compensation device with von 5 indicates that it is connected to a single power or voltage source in a digital scale. is turned jointly fed measurement transducers and Compensator to generate one of the analog Output voltage of the transducers counter-connected compensation voltage and OK The invention relates to a digital communication frequency converter for converting the pensaüonseinrichtuivg with a single current difference between the analog output voltage or voltage source and the compensation voltage in a free-size transducer and compensator to generate a pulse sequence proportional to the frequency and with a 15 one of the analog output voltage of the measured variable counter for the inputs, characterized by the fact that, as known per se, a digital voltage and a zero amplifier with a downstream comparison circuit (DV) for the Contents of the tetem Spaanungs frequency converter to the Ifinwand counter (Zl) and an additional counter (Z2) development of the difference between the analog output for continuous counting of the output pulses ao voltage and the compensation voltage in a clock generator (TG) is provided and that frequenzp roportional pulse train and with a closing time of an interrupter switch (52) counter for the pulses.