DE2261000C3 - PCM exchange for switching PCM words through - Google Patents

Description

The invention relates to a PCM-Vermitt- -Jungssielie for switching through PCM words V ^ fön input-side to output-side PCM Leis started with input-side VoÜspeicherr zvx storage of PCM words together with the outward time channel and FCM routing addresses. , "Wherein the addresses are referred to by a controller isgewählt _v%, and the reading in and out of the 'llCM words cyclically carried out.

L ■;. · A switching center for the transmission of PCM

- ^ conveying from the input side to the output side

; "For example, IPCM lines are from (« he Swedish

_s : jpehen Patsatschrift 227 453 known, according to which digital signals are given in the form of PCM words from a number of input-side PCM lines by addressing certain output-side PCM lines. The switching network for transmission required in conventional technology has been replaced by electronic memories and registers, with each channel that arrives at the memory on the PCM line in the input being assigned a line in an address memory. Characteristic for

ίο this well-known exchange is that they have one Contains switching memory from a number of matrices equal to the number of input-side PCM lines. Consequently a matrix is assigned to each input-side PCM line in the memory, which has a number of

j 5 types of storage element equal to the number on the output side PCM lines multiplied by the number Contains channels in each PCM line. The switching memory is created by a central step switching cycle at the same time and channel by channel in all

ao PCM lines on the output side read out sequentially. This known exchange is suitable for a certain view of PCM lines. if however, if the number of PCM lines is increased, the fact that the switching memory becomes an option

s «5 "'•' ix. * path in the memory is not fully utilized, too unnecessary effort.

in the! magazine "information telephony switching technology", 1969, No. 1, pp. 48 to 50, in particular Figure 12, is the principle of adapting a time division multiplex switching arrangement to the central one Calculator shown, after which the interpretation of an Informa.ion only takes place if the time is specified in a memory with the specification in a clock matches. As soon as a comparator determines the agreement, the wonnation is read out A simultaneous decoding for the purpose of forwarding the information, i * n desired time segment over an addressable output-side PCM line takes place not doing it

The invention is based on the object of creating a PCM exchange in which an optimal utilization of the memory space of the memories contained in the exchange is achieved.
This task is carried out with a PCM network

place of the type described above solved, which is characterized according to the invention by a key register for sequential and cyclic E. ^ euguii «» the time channel address, where t in per one mg-side Comparator provided for the time channel in the event of coincidence between "Jer of the time clock address generated by the timer and that of the corresponding PCM word on the output-side PCM Leituag / eiticanaiaäresse a VergieichsMguai cs ^ cugi, iifru by a decoder for each input-side time channel with one output for each PCM line on the output side. activated by the comparison signal is transmitted, the output-side PCM line address to the time-assigned decoder is, whereby the PCM word zn of the assigned output-side time channel address to the selected output-side PCM line is switched through.

The FCM communication part according to the invention is non-blocking, d. H. a route through the

intermediary is not required while at the same time an optimal utilization of memory space is achieved, resulting in a high processing capacity for telephone traffic results.

The invention is explained in detail with reference to the drawing. In the Drawing shows

Fig. A circuit diagram of a PCM exchange according to the invention,

2 shows a circuit diagram of an input side Elements assigned to FCM line, in compliance with the elements in the area dashed in Fig. 1, and "

Sh

to OCA 32 of the corresponding register arrangements. If the value of the clock register and the value of a Kaaaladdressenregister coincide, a signal occurs at the output of the comparator. This output is connected to an input of a number of / JM> gates, which are symbolized in FIG. 1 by the B.ock AND. The outputs of the information register SW1 and the link address register OLAi are also shared with the Ajsu block

Fig. 3 is a schematic diagram for a number of the Fig. 2 connected. When activating Jes A jsgangs / i blocks which form part of the exchange according to the comparator COMPl gives the block AN υ cue Fig 1. Information from the registers SW I and OLA 1 to

In Fig- I are anko- ■ - ·· -xnü outgoing links decoder / 'ECI. In the latter, the address of the exchange>. paves. With »Link« desired outgoing links for each channel

will hereinafter be referred to e ^r -dung which decodes 15, for which the comparator is activated,

with the mediation. »Is round and one whereby each channel corresponds to the corresponding number of time division PCM channels according to the desired output link 1. η is transmitted. Kanr.iem principle transmits. ^{In the} present case, the stepping cycle contains

assumed that η = - 204b left with the minimization five binary positions iiJ counts nachemanc-.

longsstelle are connected, and that each link has the values 00000, 00001, 000iO. illio, iiiii,

$ -> contains time division multiplex channels. M each incoming 00000 This ^v be 'SRTE the vergiei-

Link is connected to a terminal or connection PCM 1 to COMP with the values of the Kanaladressenrtgi- PCMn , in which the incoming star OCA is compared, that a part of each Keg ^ ier-PCM word is converted in parallel arrangement 31 to Bn forms (a total of j "Ke lsie · der as by the registers PCM1 to PCMn sym- ₂₅ for each arrangement). Do a number of! bits bolized. When all eight bits of a PCM word are received in the clock register according to ^sr "" V vcichie, they are passed on to the register arrangements in an outgoing link - ° - -> - - · oil to Bn , one of which each ankc .i- dene binary values are counted. Since the channel is assigned to the link. ^{The register arrangements} are subdivided for a ^b " ^tim . Mth J £ π fm pen B1 to Sn are all the same and contain 30 clock registers CLOCK inwrier« channels 8 £ ™ κιΐ £ feweils a number before, link d ^ ssenregistern OLA I through the switching stations. Except for the OLA 32 i Ahl Kaaladessenregister, in every arrangement B1 to ; Bη imrn.r only m

Output A compares COMPl to «'ΛΗ'Αactivates the channel address register OC / 1 ws

feweils a number before, Link d ^ ssege to OLA 32, a number of channel address registers OCA 1 to OCA32, where the number of channel

adressenregisterOC.41 b ^ s OCA 32 is activated, since the Kanaiadreg with the number of channels in a link, and: ine an 35 OCA 32 for each time position of the clock register ^ .s £ number of information registers SW1 to SW 32 for the register arrangement different Addresses he storage of PCM words, from the registers F i 2 shows further ^, nzelheite: n de; in M ^

PC ^ l to PCWn added. The link address and channel addresses. .rmation is used to manufacture Fldhl it Help i Mkie M

F i g. 2 shows further details of the ir.
dashed blocks, assigned ~ - "" ^an1 "

and Mnaiaareswuuu, m, ™ v ".. _ut u. i" - ". ^ Link, for example the link of the remote control circuit with the help of a marker M ₄ ° a PCM-Tennmal of a known type in a known construction (cf. "Ericsson Tech- nology by LM Ericsson" 30 Channel FM nics ", No. 2, 1963, pp. 164 and 165) in the register single, ZAK 30/32" (cf. especially Fig. 2.3d "se .ge'ügV According to the example, each contains Linkadres publication). The ^{T. ermin} ? ¹ "Ä's ^ S _m Snregister eleven bit positions so that 2" = 2048 comparable register SH, for J ^ '^ g ^ Kha "schiedeiie address words in u.esem Register gespei- ₄₅ a Schntt weitergeschaltetw.r ^ At S, This means that the corresponding outgoing links of the exchange are assigned to each of the 2048 ia of the shift register SH. Each Ka sponding channels zugeoremete and η the RegBter naladressenregister in the units B 1 to Bn corresponds PCW stored ^CM l ^ J ^^ l ^ _MVIn hflt in Ausführungsreispiel fun * bit positions, so entsorechenden incoming * η channel "go ^ e that i ,. Register T> = 32 different bit positions 50 registers ^SWl . ^ JZ? ^1st ^ OLa 32 and in which can be saved, in accordance with LmV-dr-ssenregisters OLA 1 bi , OLA ijz and springs of the 32 time multip.ex channels in a connected channel address register s err OC /! b> , OCA »ha. ^

«Τ r_i. ia: _ ""!, "", ^. on-lan pr; M- \ X / lok ^pr >! uprHr> n tvlnrkierer Γ

"m'lnformatiönsregister 5 ^ 1 to SW32 in the entry left

sequence in which they assume the PCM arrangement 55 coming pl.m-a

men, with each channel an informa- ^T: - '"""'

ion register is assigned.

To surprise (kr i'C MW-irt-i / uu · η,: ·. ■■ - ^ e η Links and Kan,., :: - iiemaLi.!, ■ I rüi.r. , · .; · An iaktregister ClJ) Cr _; ., rfl-.id; · · - "Λ // ¹ r: a logic circuit / 1 *" i 'mk · "\ a · ... .er I in each Regisieranor-i
Fig. 1 iclicinatic ; c ■■:
is au ^c eineiTi for
to Bn common amen ν
gang m. '-inem F ^: .in.u; i! i:
until COM? al verl'unci.
output of the output · <; dt ':

Link m .4

n ^ it:.: nunj; m: ·
in the. corresponding to ^

■ ■

_(nff ,

correct value is written, activated- connected to the EXCLUSIVE-OR gate the outputs of the other ver are in the same way if the activation signal or comparator is obtained activated the same channel in the same signaJ.

remaining links are assigned. ¹ As a result, Fig-3 explains the structure of the block AND fVi & control logic in the block ASD, which this activated 5 .flach FJ g. 1. In this figure, SW and OLA designate outputs A is assigned, and allows the values of one of the information registers 5Wlibis SW'31 J £> between. ^ corresponding Linkadreswilregisters OLA and an associated ^ LinkadressenregislerfÖJüiribis Informätionsregisters SW to äen'.entsprechendeh De- OLA 32 in einsr of the units Bl to Bn Jn'Fig, I. lure decl to DEC 32 (see "F: g.," l) " The outputs of each register SW and OLA bind with the latter are, depending on the decoded link, an input of a number of AND gates OG1 or address & se, connected to OG 2. The second input of each of these PCM words fcii the desired outgoing link AND gate is above a common connection. If then the stepping mechanism or the clocking at output A of the comparator COMP. The encoder advances by one step and the value activation of this output iass & n aiie AND gate 00001 assumes, all PCM hosts are read from 15 OG1 and OG 2 in all positions of the binary values OCA 32 stored for the channel address register OCA 1 to register SW and OLA the value 0 0001 etc. It follows from this that these values go to the 8 plus 11 one-pass depending on the clock of the clock register CLOCK of the decoder DEC . The latter keeps all outgoing links ί ... η completely syn- chronized in a manner known per se, for example, chronologically from the same channel address, thus creating diode matrices and containing a number of outputs. equal to the number of outgoing links, in this case the comparator COMF1 to COMP22 consists of case 2048. Depending on the decoded known logic circuits, for example EXCLU address, which is determined by the binary value from the register SrV-OR-GaUer, which is connected to one input with the OLA is determined, the binary value of the register output of the clock register positions and on the other 95 SW to the desired outgoing link m dem input with the output of the positions in the channel is transmitted that channel for dsn, v / ie are connected above in additional address register . Described at the output of a connection with FIG. 1, coincidence with an AND circuit, the inputs of which exist with each of the clock registers.

For this purpose 3 sheets of drawings

Claims (2)

Patent claims: 1. PCM exchange for switching PCM words through from input-side to output-side PCM lines with input-side »VoHspeichera for storing PCM words together with the output-side time channel and PCM line addresses, v / whether the addresses mentioned are selected by a controller and the PCM words are read in and out cyclically, characterized by a clock register (CLOCK) for sequential and cyclical generation of the time channels, one per input 7- ^; .ial provided comparator (COMP) in the event of coincidence between the 7 generated by the clock generator (CLOCK); ■ channel address and the corresponding PC word on the PCM line on the output side to g. A comparison signal is generated by a decoder (DEC) for each input-side time channel with an output for each output-side PCM line that is activated by the comparison signal PCM word is switched through to the assigned output-side time channel address on the selected output-side PCM Leituag 2. Exchange according to spoke 1, characterized in that each comparator (COMP) in jirdvr time phase in which the PCM word is sounded through, to execute an EXCLUSrV-OR-OperatJon between the value of the clock register uad the wide of a channel address register (OCA) is suitable so that a comparison signal appears at the output of the comparator when the two values are equal, with a logic circuit (AND) being provided, at one input of which the equal signal appears and the contents of a link address register (OLA) pass, which is assigned to the channel address register, as well as the contents of an information register (SWO, which contains the PCM word which is assigned to the decoder (DEC of each associated time channel