DE2260368A1 - CLAMP HOLD VOLTAGE GENERATOR FOR IMPULSE DISCHARGE DISPLAY PANEL - Google Patents

Description

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OWENS-ILLINOIS, INC.

Toledo. Ohio 43601 / USA December 7, 1972

"Clamp holding voltage generator for pulse discharge

Display panel "

The present invention relates to a withstand voltage generator and a feed system for gas discharge display panels with inherent memory, the withstand voltage generators the operating power for such gas discharge arrangements (as in US-PS 3,499,167 and / or US-PS 3,559,190), wherein the cross conductor arrangements, i.e., the row and column conductors are dielectrically isolated from the discharge medium not to be in conductive contact therewith, and wherein the load on the generator is essentially capacitive in nature is.

Because of the non-linearity of the impedance given to the generator is supplied by the panel, and because of the impulsive nature of the discharges in the panel (i.e. the load current has a pulse-like character), distortion in the withstand voltage waveform can affect the operating characteristics of the Affect the device to such an extent that its

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Memory function is distorted and disturbed.

The present invention relates to a square wave withstand voltage generator high performance for gas discharge display panels, which has less distortion in the waveform of the withstand voltage applied to the panel will have. According to the invention is a pair of transistor switching amplifiers connected in series to a voltage supply source in a clamping circuit, the connection point between the two transistor amplifiers with the Conductor arrangements of the panel are connected via some addressing and / or multiplex network. Any such Amplifier is provided with clamping diode networks in order to to avoid complete conduction or saturation of the transistors. In this way the output signal can dem Input signal follow over a wide range of pulse widths and frequencies. The power loss in the output transistors is kept small and a large number of discharge points can be driven by the generator.

The above-described and other objects, advantages, and features of the invention are provided in light of US Pat following detailed description in connection with the drawing more clearly.

It shows:

Fig. 1 is a block drawing of the gas discharge panel, at

to which the invention has been applied, Fig. 2 is a simplified block diagram to explain the

Principles of the Invention and Fig. 3 is a circuit diagram showing the details of the invention embodied holding voltage generator explained.

The gas discharge panel in FIG. 1 is essentially of the type explained in US Pat. No. 3,499,167 and is made by formed a pair of support plates 11 and 12, on which line

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lleiteranordnurigen and column conductor arrangements 14 are arranged, wherein the conductor arrangements are provided with dielectric or insulating coatings 15 and 16 so that no direct current passes from the conductors over.den dielectric coating to the gaseous medium, ie the matrix crossing points, which are determined by the crossing conductor arrangements are non-conductive coupled to the gaseous discharge medium in the panel. The respective plates are connected at a distance from each other by a sealing spacer 17 to each other, so that a thin gas discharge chamber is formed, may be disposed in a Ifeon-argon gas mixture (preferably 99.9 i ° neon and 0.1 fo argon) as described in I ¹ R-PS 2,019,723. Other gas discharge media can be contained in the panel in the same way, but the improvement achieved by the gas mixture mentioned above allows the panel to be operated in the 30-50 kHz range without it being destroyed by thermal shock, while at the same time being good Luminous efficiency and good storage conditions. To lower the operating voltage level, the dielectric or insulating layers can be treated with a lead coating (not shown).

The individual conductors in the row conductor matrix 13 are preferably operated by a row conductor selection matrix 20, and the column conductors are preferably operated by a column conductor selection matrix 21, such selection matrices not forming part of the present invention, however be formed by diode resistor selection matrices can be operated in multiplex mode as required to be or not. However, instead of a selection matrix operating on a multiplex basis, special pulse circuits can be used can be used to select individual row and column conductors. The selection matrices 20 and 21 receive inputs from a signal source not shown, which a Computer, keypad, tape reader, or other

-4 -

3098 27/03 37

Data source can be.

A pair of holding voltage sources 30 and 31 are provided to generate holding potentials with opposite phase or opposite To provide polarity to the row conductor arrangement 13 and the column conductor arrangement H in the panel 10.

Since in each case one half of the holding potential that is fed to the panel is applied to the row conductors and the other half of the holding potential is applied to the column conductor, note that the holding voltage generators 30 and 31 have a common point or a common terminal G (which does not necessarily have to be dielectric earth), so that in the arrangement shown, the potentials generated in or by the row conductor selection matrix 20 on the Float potential of the holding voltage source 30 or relate to it. In a similar way are the potentials for Ignition and influencing of the discharge conditions, which are generated in the column conductor selection device 21, in series with the current voltage from the holding voltage generator and have this as a reference point. In addition, both holding voltage generators 30 and 31 receive control logic inputs from a source 32 which may be a computer or other signal source if desired. It can So at times it may be desirable to delete the panel, with one of the signals that one of the holding voltage generators and 31 are supplied, simply omitted during a certain time interval, so as to result in total erasure to allow any information on the panel, or ea may be desired to change the withstand voltage rate by changing the To change the holding voltage rate from the control network 32.

In the block diagram of Fig. 2, there is a withstand voltage generator shown, the invention essentially by a pair of transistor amplifier circuits 33 and 34 with Potential clamp is formed, its connection point

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with the panel row or column conductor selection matrix for feeding in holding voltage potentials to the corresponding Row or column conductors are connected on the panel. Each transistor booster circuit 33 and 34 is provided with control signal coupling means 37 and 38 connected thereto, which control circuit 32 from the high-voltage circuits isolate and at the same time allow positive monitoring of the mutual switching of the transistors.

In Fig. 3, a withstand voltage generator for one of the conductor arrangements is shown in detail, it being noted that that the conductors in the array can be divided or grouped with a withstand voltage generator for each Part or each group of conductors on the display panel shown in Fig. 1. The control input for the control circuit 37 is powered by a pair of so-called "pull up" signal voltage pulses formed with the time relation shown in the waveform diagram to the pair of "pull up" voltage pulses.

The collector of the npn transistor Q ^ is through a collector resistor 50. Connected to a low voltage control source, and its emitter is connected to a low voltage ground (which is not the same as at terminal G_) via a resistor 51 tied together. A separate signal is fed to the base of the npn transistor Q, the collector of which is carried out in a similar manner through a resistor 52 to the low voltage power supply and the emitter of which is connected to the low-voltage ground via an emitter resistor 54. The collector of the transistor Q .. is directly connected to the base of the pnp transistor Qp connected, the emitter of which is connected to via a resistor 55 the low-voltage supply and its collector via the primary winding of a transformer T. to the low-voltage ground connected is. A resistor 56 is the primary winding of the transformer T., connected in parallel to this one

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deliver controlled recovery.

Similarly, an output signal is taken from the collector of the transistor Q ^ 'and fed to the base of the pnp transistor Q., the emitter of which through the resistor 58 with the low voltage supply and its collector through the primary winding of the transformer T ₂ with the low voltage -Ground is connected. Resistor 59 is connected in parallel across the primary of transformer T ₂ to provide controlled recovery therefor. The polarity relationship between the primary and the secondary winding of the transformers T ₁ and T ₂ behaves as indicated by the dots.

The lower end of the secondary winding of the transformer T ₁ is connected to a common point 70 at the lower end of the secondary winding of the transformer T ₂ , both ends being connected to the emitter electrode of a transistor Q ^ which is the switching and load transistor. However, the upper end of the secondary winding of the transformer T _{2 is} connected via a diode D ₁ to the base electrode of the transistor Q ₁ - and via the clamping diode D ₂ to the collector electrode of the transistor Q 1 -. The upper end of the secondary winding of the transformer T ₁ is connected to the base electrode of the transistor Qc via the diode D 1. A low resistance 60 is connected between the base and emitter electrodes of transistor Q ₁ and a current loop 61 is provided to provide a measuring point for current flow to the collector along with a heat sink (not shown). The collector of transistor Q ^ is then connected to the bias voltage source _{T (of approximately 150 V) through a diode D A,}

CC T ^-

which prevents the transistor Q ^ from being switched on in an inverse operation. The bypass diode D, - has the purpose of providing a return path for the charging currents to the panel when the generator is reversed. When these diodes D, -, D.

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would not exist "or if this blocking and bridging were not provided, the charging of the panel or the load could bring the transistor Q ₁ to breakdown (spike Q 1 - on).

Me diodes D. and Dp clamp transistor Q, - and form a clamp circuit. Accordingly, these diode circuits put the switching transistor Q ₁ - in the conductive state, so that strong conduction or a complete saturation operation of this transistor is avoided. The rise and fall times of the square-wave voltage generated at the output are therefore much sharper, and a quick response to control signals is thereby achieved. The transistors Q ₁ and Q ₂ supply high base current pulses to the transistor Q ₁ - via the transformer T ₁ , which saturate this transistor "during the period in which the discharge takes place. The transistors Q * and Q ^ offer via the transformer Tp the base of transistor Qc- be controlled via the diode D .. is that goes through the collectors when the circuit is saturated and the aims of the transistor Q ₁ -. disable when this occurs once , current is drawn through the diode Dp and D ₁ in order to provide only the base modulation which is required _{to keep transistor Q 5} out of saturation, but which always enables it to supply the current required by the collector.

The diode D, is provided to provide a high impedance for the Secondary winding of the transformer to form Tp, and so on to prevent the secondary winding from transformer T. short-circuits the signals from the secondary winding of the transformer Tp, i.e. the diode D, isolates the base control, so that the pulse on the secondary winding of the transformer Tg at the base of the transistor Qc- is effective.

The fact that in the transistor Q ₁ - the deep saturation is prevented by the use of the diode described above

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Clamping circuit, the effect of the charge storage in transistor Q ^, which is detrimental to the waveform on the panel, is reduced. In addition, the sensitivity and responsiveness to input signals at the bases of the transistors Q _{1 and Q 1 are} significantly improved.

Me lower half of the circuit, ie the so-called "pull down" half, through the transistors Q ₁ ', Q?'> Q * '>Q.' is essentially identical to the mode of operation of the control circuit 37. In this case - since transformers T ₁ and T _{2 are} not required - the diode D, is superfluous. That is, the transistor Q ₂ inherently represents a high impedance for the output of transistor Q., so that the output signal of the transistor Q1 is applied directly to the base of the transistor Qc- '. It should be noted that both transistors Q ₂ ¹ and Q, ^{1 use} the same collector resistor, which corresponds to resistor 60 in the upper ("pull op") circuit.

The circuit described results in the flexibility of the output signal by allowing it to follow the input signal faithfully, results in a reduced power loss and approximates the ideal square waveform in a much better approximation than before. In addition, the circuit allows several discharge points to be operated by a single generator. The output square wave voltage of this holding voltage generator closely follows the combined _{input voltages applied to the bases of transistors Q 1} , Q, and Q ₁ ', Q, ¹ over a wide range of pulse widths and frequencies. The disclosed clamping circuit is designed so that the output transistors are saturated for only part of the period, but are unsaturated for the remainder of the time. This pulling out of saturation is _{accomplished by resistor Rg 0} which pulls the charge from the base of transistor Qs- while all of the secondary current from T _{2 is} through the

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Diode Dp flows. The essence of the invention consists in the Use of a modified clamp circuit to deeply saturate the output transistor of a holding voltage generator to avoid the purpose of creating a rectangle output voltage to a large capacitive load, as shown by a gas discharge panel of the US Pat. No. 3,499 described type is formed.

It will be understood that many changes and adaptations of the invention will be apparent to those skilled in the art, and the scope of the following claims is intended to cover such obvious modifications and changes.

PATENT CLAIMS - 10 -

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Claims (6)

PATENT CLAIMS: 1. Rectangular holding voltage supply arrangement for a gas discharge display panel with row-line conductor arrangements, whose matrix crosspoints are non-conductive coupled to a gas discharge medium in the panel, characterized by a Pair of square-wave withstand voltage generators, one for the row conductor arrangement and one for the column conductor arrangement, each withstand voltage generator having a pair in series switched alternately conductive and or respectively non-conductive transistor amplifier, means having an intermediate point connect between the transistor amplifiers with the conductors in a ladder arrangement for each transistor amplifier a diode circuit to keep the transistor amplifiers unsaturated, if not for peak charge and discharge currents required and contains control means connected to the input circuits of the transistor amplifiers in order to alternately to control their master conditions. 2. Arrangement according to claim 1, characterized in that each diode circuit in the circuit between the collector and the base of the transistor includes diodes for conducting peak charge or discharge currents to the panel. 3. Arrangement according to claim 2, characterized in that the diodes are a pair of reverse connected diodes with a connection point therebetween, the base of the Transistor amplifier with one end of one of these diodes is connected to receive a control voltage and that other end of this diode is connected to receive the other control signal. 4. Arrangement according to one of claims 1 to 3, characterized characterized in that the control means for a pair of transistors includes a pair of input transistors for reception logical signals as well as a transformer pair - 11 - 309827/0337 with primary windings connected to the input transistors are, secondary windings, a common output for feeding a control signal into the transistor amplifier, and with effective diodes in the secondary winding circuit to form a blocking resistor for one of the secondary windings. 5. Arrangement for feeding in square-wave holding potentials in conductor arrangements arranged transversely to one another in a gas discharge display panel acting as a capacitive load, wherein the crossing points of the conductor arrangements spatially define a plurality of discharge points in the panel, with a high DC voltage source having a pair of output terminals, a first pair of alternately conductive ones Transistor arrays connected in series to a source of high DC voltage and their connection point is connected to one of the conductor arrangements, a second pair of alternately conductive transistor arrangements, which are connected in series to the source of high voltage and their connection point to the other conductor arrangement is connected, and with control means for controlling the alternating conduction and blocking conditions of the transistors at selected times, such that square-wave holding voltage potentials successively connected to the conductor arrangements in order to supply them with a charging current feed as well as to the reference potentials common to the sources in order to discharge the conductor arrangements, the control means for each transistor a separate control circuit for controlling the duration of each square wave as well as Means for connecting each control circuit to receive a low level logic voltage from a source, thereby characterized in that each alternately conductive transistor arrangement by at least one transistor circuit with Potential clamping is formed. 6. Arrangement according to claim 5, characterized in that - 12 - 3 09827/0337 each transistor arrangement comprises at least one transistor amplifier, wherein between the collector and the The base of each transistor amplifier is a diode clamp circuit connected. 309827/0337 Empty soap