DE2247929A1 - FIXED STORAGE SIMULATOR - Google Patents

Description

Our reference: H 942

SOCIETE INDUSTRIAL HONEYWELL BULL 94, Avenue Gambetta
Paris XXe / France

Read only memory simulator

The invention relates to an arrangement which makes it possible to store microinstructions in the absence of or instead of a read-only memory to simulate in a program-controlled computer system.

Such an arrangement is suitable for setting the computer systems and for checking the microprograms forming microinstruction groups before the formation of the read-only memory.

According to the invention, a read-only memory simulator, which instead of the read-only memory between the addressing ' ration matrix circuits and the microinstruction output circuits of the read-only memory is to be connected, whereby a microinstruction to be simulated from several actual Microinstruction bits, one or more parity bits forming a key for the microinstruction bits and one Address key bit, identified by

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-2-. . 22A7929

at least one microinstruction bit generator, the bits of which are transmitted to the output on the one hand and on the other hand selectively one or more parity key generators , each parity bit of which is fed to the output is supplied, and by a key generator with two complementary outputs, which is connected to the output of the addressing matrix. and an address key which corresponds to the n-1 address bits seen across this matrix, where the nth bit the bit with the least significant value of the address, the address key generator is one of the bits at the output which is assigned to the outputs of the bits dos simulated microinstruction, while the complementary Bit is fed to the output which is assigned to the outputs of the bits of a second simulated microinstruction is.

AusfUhrungsbeispiele the invention are in the drawing shown. Show in it:

1 shows the circuit diagram of a read-only memory simulator according to the invention with a generator for two microinstructions and

Fig.2 shows the circuit diagram of another embodiment of a Read-only memory simulator according to the invention with a generator for four microinstructions »

The simulator 1 shown in Figure 1 is used instead of the Read-only memory connected, i.e. between the output circuits 2 of the addressing matrix and the output circuit 3 of memory where the microinstruction is chosen by the least significant address bit

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This simulator is intended to be used in the circuits of a program-controlled computing device to enter micro-commands, each consisting of 20 bits, which on 16 actual microinstruction bits, two parity key blts for each group of β bits (octet), an address key bit and a reserve bit are distributed.

The simulator therefore contains a hand-operated microinstruction generator, which consists of 2 χ 16 switches 4 and 4a, which are divided into two groups of eight 5 and 6 and allow the setting of two microinstructions, one of which is an even address and the other have the following odd address.

The bits of each group of eight of the simulator are fed directly to the output terminals on the one hand and to one on the other Parity key device 7 »whose parity bit is one further output terminal is supplied, which is assigned to the terminals of the bits of the relevant group of eight.

The simulator also contains an address parity key generator 8, which outputs a parity bit PA and a complementary bit Ρ3Γ, which are fed to the output. This generator is connected to the addressing matrix and calculates an address key that corresponds to the n-1 address bits, with the nth bit with the lowest value making the selection between the two micro-commands at the output of the simulator, namely either the micro-command at output 9 the even address., to which the bit PA is assigned, which has the digit value 1 if the address is even, or the microinstruction at output 9a with the odd address to which the bit VK is assigned.

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Thus, if the address is even, the n-th bit has the numerical value O ₁ while the bit PA has the value 1; then the microinstruction at output 9 with the even address is selected. If the address is odd, the n-th bit has the digit value 1 and the bit PA has the digit value 0, while the bit PT has the digit value 1, so that the output 9a with the odd address is then selected.

The microinstruction generator can be a punched tape scanner into which a coded punched tape is input.

Since the punched tape only contains 8 bits per sequence, a register 11 for a group of eight is required so two groups of eight can be set at the same time. In this case the same microinstruction becomes the two Outputs 9 and 9a supplied, and the delivery of the micro-commands takes place by sequential reading of the tape.

A changeover switch 12 enables the passage of the two from by applying a bit of the value 1 to two AND gates 13 Punched tape originating microinstruction groups of eight, while the application of the complementary bit to AND gate 14 die connected to the outputs of switches 4, the passage of the groups of eight manually set Disables microinstructions, or vice versa, depending on the position of switch 12.

In the embodiment of Figure 2, the simulator allows 1a the setting of four microinstructions. In this case the 16 switches 4 are connected to three registers on the one hand, namely with two registers 15a for the microinstructions with an odd address and with a register 15 associated with with switches 4 it is possible to set two micro-commands with an even address.

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The micro instruction bits are applied to 16 gate circuits, controlled by the (n-1) th address bit preceding the least significant bit, and on Gate circuits 17 which are controlled by the bit complementary thereto; this enables the selection of a microinstruction with an odd address and a microinstruction with an even address from the four set microinstructions.

The rest of the circuit and how it works is the.

same as in the case of Fig.1, and the choice between the both microinstructions are carried out by the nth address bit-;

Of course, the invention is not limited to the illustrated and described exemplary embodiments, but rather it various changes can be made. In particular, the number of registers for setting of microinstructions depending on the number of switches used be different and other address bits can also be used for the selection of the microinstructions.

Claims

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Claims (5)

Claims 1J read-only memory simulator that replaces the read-only memory between the addressing pmstrix circuits and to be connected to the microinstruction output circuits of the read-only memory, wherein a microinstruction to be simulated from several actual microinstruction bits, one or more, forming a key for the microinstruction bits Parity bits and an address key bit, characterized by at least one microinstruction bit generator, whose bits are transmitted to the output on the one hand, and selectively one or more on the other hand Parity key generators are supplied, each parity bit of which is supplied to the output, and by a Key generator with two complementary outputs connected to the output of the addressing matrix and computes an address key corresponding to the n-1 address bits seen across that matrix, where the nth bit is the least significant bit of the address, the address key generator is one of the Bits to the output associated with the outputs of the bits of the simulated microinstruction, while the complementary bit is fed to the output, which is the outputs of the bits of a second simulated microinstruction assigned. 2. Simulator according to claim 1, characterized in that the microinstruction generator sets two microinstructions from where one has an even address and the other has an odd address, and that the generator has a Switch group is formed, which consists of as many switches as there are bits in the actual microinstructions are. 3098U / 1130 3. Simulator according to claim 1, characterized in that the generator is a punched tape scanner, which reads the micro-commands contained on the punched tape after reading 4. Simulator according to claim 3, characterized in that each microinstruction is fed to the two outputs, namely both the output for the microinstructions. even address and the output for the microinstructions with an odd address » 5. Simulator according to claims 3 and 4, characterized in that that controlled by a switch AND gates in the Switches and the punched tape scanner coming micro-instruction circuits are inserted to one or the other to lock these circles. 6 »Simulator according to claim 1, characterized in that the Generator sets four microinstructions, two of which have an even address and two of which have an odd address, and that in the circuit to transmit the set Microinstruction bits to the output gate circuits are inserted from the (n-1) th address bit or the associated complementary bits can be controlled so that they contain a microinstruction with an even address and a microinstruction with Select an odd address. .7. Simulator according to Claim 6, characterized in that the Generator a switch group with one switch for each bit of a microinstruction and three registers for recording the bit group set by the switch group. 309814/1130