DE2246008C3 - Digital data processing device for determining the optimal operating time of a drill head - Google Patents

Description

in which

C = cost per unit length of the manufactured

Boreholes,

B = drilling head costs,

7 = travel time for the drill head change,

D = drilling time,

R = device cost / hours,

F = Bohrtiafe,

with storage registers, arithmetic unit program control unit and printing unit, characterized in that the storage registers (20,22, 24, 26, 28) contacts have that, for the values of B, T. R by hand, for the value D by a timer (32 44) and for the value F by a drilling depth indicator (38) it is possible to set that the decoding outputs (Tl-31) of a counter (140) of the program control device each with the contact set of the memory registers assigned to a digit (decoding outputs 74-78, 710-714, 716-719, 721-24, 726- 729, Fig. 2) or with a command input of the arithmetic unit (decoding outputs 71, 72, 77, 713, 79, 720, 715, 725, 730, Fig. 3) or the pressure value (decoding output 731), the counting cycle being able to be started by an oscillator (44, 94) in presettable calculation intervals and being terminated at the end of the program.

2. Device according to claim 1, characterized in that the equivalent outputs (62) of the Contact sets of all digits of all registers are interconnected and with a binary / decimal converter (90), the digits being encoded in the 8,4,2,1 code in the memory registers are stored.

3. Device according to claim 2, characterized in that the command inputs of the arithmetic unit and the outputs of the binary / decimal converter (90) are connected to relays (68a - o) whose contacts control inputs (XO-XZ, YO- V7) of the arithmetic unit .

4. Device according to claim 1, characterized in that a device (168) is provided, which increases the counting intervals of the counter (140) for the multiplication and division instructions.

5. Device according to claim I, characterized in that the operation according to the first operation command can be carried out after entering a second operation command, which the second operand follows.

6. Device according to claim 1, characterized in that a device (F i g. 5) for comparison the result of two consecutive calculations and for the delivery of an advertisement, if the result of a calculation exceeds that of the immediately preceding calculation, is provided.

10

ΙΪ

5 ^r >

<, o

7. Device according to claim 1, characterized in that the computing unit (14) has a Output signal temporarily storing storage device (Fig.5) is connected, the with the last decoding output signal (731) of the program control device (18) the result the last calculation by the arithmetic unit (14) takes up

8. Device according to claim 1, characterized in that a calculation of a manual switch (119) is controllable

9. Device according to claim 1, characterized in that a calculation of a manual reset switch (126) is terminable

10. Device according to claim 1, characterized in that the computing unit (14) on the Enter a first operand followed by a first operation command and the subsequent one Entering a second operand performs the requested operation on the two operands

25 The invention relates to a digital data processing device for determining the optimum operating time of a drill head according to the equation

(T + D) R

in which

C = cost per unit length of the drilled hole produced

B = drilling head costs,

7 = travel time for the drill head change,

D = drilling time,

R = device cost / hours,

F = drilling depth

with storage register, arithmetic unit, program control device and printer.

Oil wells are known to be drilled with the help of a rotating drill head, which is at the lower end a string of drill pipe sections is arranged. The latter are made by one on the earth's surface mounted drilling rig or carried by a coastal drilling platform. The drill head is with a Number of cones mounted on the drill point, each of which is made of diamond or one other appropriate material existing teeth is occupied. When the drill head is fed into the Further drill pipe sections typically each about 9 m in length are added to the drill string added. The entire arrangement is from the derrick at constant speed at constant applied force in rotation.

During the drilling process, the drill head closes, for example as a result of wear on the teeth or Damage to the cones, so that the rate of penetration of the drill head into the earth is gradual decreases. With advanced tooth wear, the penetration, i.e. H. Drilling speed finally a point at which the work efficiency is so low that the drill head must be replaced got to. Fin wear of the taper bearings can be gradual

Cause difficulties. In the event of a cone bearing failure the cone can also fall into the borehole. This presents a particular difficulty because the Cone cannot be destroyed by simply "drilling through", but rather from the borehole must be extracted, which is extremely costly and time consuming

In any case, the drill head must in the way from the Borehole are extracted so that the drill string is dismantled section by section. Then will the drill string provided with a new drill head and lowered to the bottom of the borehole, whereupon the Drilling process is resumed.

In the case of a deep borehole, retrieving the bit and reassembling the Drill string for ten hours or more. Of course, do the drilling work during this Time no progress, while the hourly cost of maintaining and operating the drill rig continue to accumulate. For example, a typical drill head costs about $ 200 and has a service life of ten hours; the maintenance and operating costs for the rig during this However, the time span can be S 2000 or more.

From the foregoing it can be seen that the cost per unit length for one with a new Drill head drilled borehole as a result of the cost of the drill head and during the insertion time The necessary equipment costs are initially quite high. With an increase in the number of holes drilled with the drill head Units of length it is then found that the average cost per unit of length decreases, albeit the drill head wears out and its drilling speed decreases. Finally the drilling speed compared to the drilling head costs and the Einführbzw. However, travel time is so low that the average cost per unit length increases again. For the optimal utilization of the drill head, it is necessary that he at the or at least about the time is replaced, at which the average cost per unit length of its minimum value again begin to rise. As a result, a carefully balanced decision must be made as to when a drill head is to be taken out and replaced, at a minimum cost per unit length of the to ensure produced borehole.

Unfortunately, now common practices for determining when to remove a drill head are pretty unsatisfactory. Essentially, the drilling worker must rely on his experience and the special drill head used, the geological formations etc. in which the drilling is carried out, and of course take into account the length units actually drilled per hour. The experience of the drill worker supports himself, inter alia. on calculations based on the actual circumstances and the actual cost of drilling per unit length, but such calculations are seldom fast enough available to serve as reference values on a "real-time" basis.

In addition, the job of the drill worker in determining when the Drill head is to be removed, made considerably more difficult that no readily recognizable An / calibrate for the change in drilling speed as a function of time is available based on this experienced drill workers already have the optimal time to pull out and change a drill bit.

d. H. could determine the point in time at which the drilling costs per unit length begin to rise.

Some time ago it was now recognized that the cost of a specific drill head and the hourly costs for the maintenance and operation of the drilling rig in connection with the approximate inputs and Extension time for changing a drill head and the number of length units actually drilled can and have been able to ensure a meaningful estimate of the optimal operating life of the drill head various methods for evaluating this information have been proposed. Such a method is used for example a mechanical analog computer for developing a curve, which the following

is ratio represents:

K + T

Therein mean:

K is the "preparation time" including the retraction and extension time for changing the drill head plus an equivalent time based on the 2 ^r i drill head costs;

T the drilling time and

F is the number of units of length drilled (e.g. in feet).

jo The values determined using the above formula are provided on a continuous reference basis as a special chart which the drill operator periodically can check to determine when a drill head should be withdrawn.

v; However, in addition to the need for a special diagram, this arrangement has various disadvantages and it shows certain inconveniences when setting up the device and interpreting the results. In addition, the use of the known device is not always advantageous because of insufficient reliability. Although the aforementioned method has been known for a number of years, it is - as far as this can be determined - not used very often.

4 ^r ) Various other methods have been proposed to optimize bit utilization using more complex formulas, but these methods do not provide particularly useful indications of the average cost per unit length

so of the completed borehole and / or are available to the drill operator on a "real time" or "on-line" basis Drilling location not appropriately applicable.

From DT-OS 21 21 984 a process computer for controlling processes, for example in industrial

v, len procedures known. The computer contains a registration device, functional devices, a memory and a data control unit which is connected to the memory device, the register devices and the functional devices

W) Functional devices cause functional processes which can be arithmetic or otherwise and applied to values contained in the Register devices and / or are stored in the memory devices. The register device

In ^{the known computer, h r} > contains a large number of registers, some of which are directly accessible from facilities outside the computer, with the functional facilities also having a large number of

Have functionalities. This known process computer isi designed in such a way that it is possible to create various instructions and instructions to be carried out Operations to be fed in at the same time, so that there is the possibility of several> Sources of information to read a program into the process computer.

From US-PS 33 19 055 an electronic computer device for determining the cheapest Variant for dividing a roll of fabric in any length into predetermined or standardized length sections-Ic, so that a minimal remainder is left, known.

The computer means includes a plurality of storage registers and input means for entering the register information regarding the total length, ge of the web of fabric and to read in data regarding the length of each required strip. the The device includes an adder and means to put the outputs of the registers in parallel with the To connect adding device, further a pro- _> n program control device connected to the registers and a variety of electronic Counters to successively select combinations from the registers and these from the registers to be transmitted to the adding device. The arithmetic unit-> -, unit also contains a program control device to to control data processing.

From the DT-OS 20 13 758 a digital program control arrangement for operating variables of the engine systems, in particular of internal combustion engines _{ll and vehicle test facilities is known. The arrangement comprises at least one measuring sensor for detecting the actual value and setpoint of the regulated operating variable and a servomotor, which is controlled as a function of the differences between the actual values and the specified j, setpoints and coupled to an actuator that influences the operating variable. With the help of this known arrangement, the object is to be achieved of influencing the operation of a machine or machine system by adjusting one or more setting elements in such a way that one or more operating variables, despite the occurrence of disturbance influences, assume predetermined setpoints with the smallest possible deviation and Maintain constant time, or follow specified time functions of 4, setpoints as precisely as possible with as little loss of time as possible. This requires the following steps:

1. Measurement of the actual values of the operating variables, - _{) (} |

2. Recording of the setpoints of the operating parameters.

3. Determination of the tendency and size of the deviations and, if necessary, the speed of change and / or time integral or a time mean value thereof,

4. Determination of the time functions for assigning values to the manipulated variables with the aim of achieving the best possible result Realization of the standard task and

5. Activate the actuators according to the results from 4. _M)

With the aid of the known digital program control arrangement, the object is to be achieved of significantly improving the response behavior of a control loop, in particular with regard to the accuracy _b5 or with regard to the influence of interference factors. This object is achieved in the known case in that the logic functions of the control are carried out within a stored-programmed, the actual value and setpoint value of each controlled operating variable as a parameter receiving digital computer system through its command sequence, so that the servomotor of each control loop through the computer system in the sense of Approach of the actual value to the setpoint value can be switched on and off successively, with both the unit duration and the downtime duration of the servomotor each being calculated by the computer system depending on the instantaneous size of the differences between the actual values and setpoint values, taking additional influencing variables into account, or at If the actual deviation falls below a specified setpoint, the duty cycle of the servomotor is kept constant at a minimum value.

After all, it is from the magazine »J. Martin, Design of Real Time Computer System, New York 1967 known a digital data processing device to use to determine the optimal operation of a system. The evaluation of the data takes place intermittently at fixed time intervals. In a digital data processing system, the intermittent operation is therefore also necessary to reduce the conversion time of the analog-to-digital converter and the Take into account computing time for evaluating a formula.

The object on which the invention is based is to provide a digital data processing device Type defined at the beginning for the special purpose of optimizing the tool life of the drill and optimizing the drilling line to create, which on the one hand is comparatively simple in structure and a digital display of the Provides computation results and their storage device is checked and serviced in particular at any time and individual storage elements can be replaced by new storage elements even by a non-specialist can be. A data processing device that meets these requirements can therefore Use particularly advantageous for drilling work, as these are very common in very remote areas must be carried out in which a data processing specialist is difficult to grasp.

Based on the digital data processing device of the initially defined type, this object is achieved in that the storage registers having contacts for the values as T, R by hand, for the value of D from a timer and the value F of a Bohrtiefen- Indicators can be set so that the decoding outputs of a counter of the program control device are each connected to the contact set of the memory register assigned to a digit or to an instruction input of the arithmetic unit or the pressure value, the counting cycle being started by an oscillator at preset calculation intervals and being terminated at the end of the program.

The combination of these features results in a comparatively simple digital one Data processing device in which the storage registers consist of sets of contacts, so that these can be checked for their functionality extremely easily, but additionally the possibility is given to adapt the calculation intervals to the respective circumstances.

The digital data processing device according to the invention provides very extensive information. For example, drill heads are of various types

for use in different geological formations. It is particularly the use of a drill head in a formation for which it is unsuitable, from the economic Disadvantageous point of view. Therefore, if such a formation is encountered during the "> drilling process, the average cost per unit length may increase, possibly long before the The drill head is worn out. When using the digital data processing device according to the invention i < The drilling worker is immediately informed that there is no optimal economic utilization of the drill head.

Particularly advantageous developments and refinements of the invention result from claims ι -, 2 to 10.

In the following the invention will be explained using an exemplary embodiment with reference to the drawings explained in more detail. It shows

1 shows an overall block diagram for illustration purposes chung the essential features of a special purpose digital data processor according to the invention,

2 shows a detailed circuit of the input storage registers,

F i g. 3 a detailed circuit of the arithmetic unit _> ϊ together with assigned logical input and external control circuits,

4 shows a detailed circuit of the program control device.

F i g. 5 a circuit of the logic output circuit _{J (l} circuit for the arithmetic unit,

6 shows a detailed circuit of the printing unit control,

Fig. 7 is a schematic representation of various, Wave forms occurring in the system to illustrate various features of the working method the plant.

The in F i g. 1 generally indicated at 10 has an input register section generally designated 12, a computing unit 14, ₄ <> an input multiplexer 16 and a program control unit indicated generally at 18.

The input register section 12 has two externally controllable memory registers 20 and 22 for recording the total drilling time or the respective drilling depth 4, as well as three manually operable storage registers 24, 26 and 28 for the fixed values of equipment cost, drill head cost, and travel time. Register 20 is via a control gate 30 with a 0.1 hour clock 32 in the program control device 18 -, < > Connected to record actual drilling time in units of six minutes. The total depth register 22 is connected via a control gate 34 to a drilling depth recorder 38, which is preferably with the conventional borehole depth measuring device provided on the drilling device a convenient device for converting their motion into a series of electrical ones Impulses, for example in the form of one impulse per foot (about 0.3 m) depth of the borehole, are bo

The equipment cost register 24, the drill head cost register 26 and the travel time register 28 are manually adjustable devices which, at the beginning of an operation, store the constant values of the equipment costs (dollars per hour), the drill head costs _b s (in dollars) and the estimated travel time in hours based on an estimate by the drill worker based on the expected length of the drill string at the time at which the drill head is to be extracted.

With regard to equation (2) above, it can be seen that a sequence of arithmetic operations, such as addition, multiplication, division, with the in the Input register stages 20 to 28 contained data must be carried out. These data are used for appropriate time under the control of a work sequence unit provided in the program control unit 18 40 supplied to the arithmetic unit 14 through the input multiplexer 16. The unit 40 Control signals supplied activate the multiplexer 16 for coupling the relevant register stages to the Arithmetic unit and also to supply arithmetic operation command signals for the arithmetic unit 14 in a manner yet to be explained.

In addition to the 0.1-hour clock generator 32 and the work sequence unit 40, the logic control unit 18 a clock generator 42 for advancing the work sequence unit via its program cycle and a 60 Hz clock 44 which operates the 0.1 hour clock 32. The latter contains a number of Divider stages that divide the 60 Hz pulse train into a series of six minute intervals Convert impulses. The clock 44 also operates a calculation interval selector 46 which is also is a frequency divider, which in certain time intervals of e.g. 15 minutes or 30 Minutes or one hour each actuation signals for the work sequence unit 40 emits. The voter 46 also controls a computation time signal generator 48, which during a computation period of time Control gates 30 and 34 deactivated in order to change the values stored in the register stages 20 and 22 To prevent information during the arithmetic operation. The logic control unit 18 also has a clock oscillator 50 for controlling the internal processes of the arithmetic unit 14.

The device according to FIG. 1 also has a printer 52, which is sent to the Output of the arithmetic unit 14 is coupled. Both the printer 52 and the conversion unit 54 are controlled by the work sequencer 40 to keep a result of each successive calculation according to equation (2). A time detector 56 may also be provided for optimal time of use which responds to successive solutions of equation (2) and determines the point in time which the average cost per unit length of the drilled hole will begin to increase. the Detection of this condition can be used to activate an alarm device or to deliver another, Easily recognizable indication for the drill worker that the drill head has been removed and used should be replaced.

The F i g. 2 to 6 show functional and arrangement features of a in more detailed block diagram form preferred embodiment of the device according to FIG. 1, while FIG. 7 shows typical operating signal forms are shown. There are numerous design details to facilitate illustration and description omitted and various logical functions grouped together in connection with functional collecting blocks are described. The actual circuitry of each of these blocks is general with reference to common, commercially available, integrated logic elements for performing the specified functions. The through this

Function blocks shown actual sound arrangements do not constitute part of the invention per se, which is why in the interests of a clearer and Brief description of the essential overall structure and overall function to their explanation "> is waived.

The device according to FIGS. 2 to 6 is a commercially available one consisting of integrated circuits Computing unit of the type EAS-100 from Electronic Arrays, Inc., Mountain View, California / V. St. A., built around. These according to large-scale integration processes Device constructed from metal oxide semiconductor elements has a sixteen-digit capacity Internal processing Addition, subtraction, multiplication and division processes eight-digit input r, to process values. The output files are encoded in binary 8421 decimal code for each of the eight exit points delivered. A "1-of-8" decoder output identifies the relevant digit or position. The output data circulates continuously until a new arithmetic operation is carried out. at A corresponding modification of the logic control circuit can also be used by other, comparable arithmetic units from integrated circuits or a specially designed data processor with medium and small integrated units can be used.

An EP-101 type from Suwa Seiko Company is used as the output printer. This device prints a line containing 2i symbols by means of a rotating printing drum that moves 21 to jo Transversely spaced distributed circumferential rows of symbols carries. Separate print hammers bring the print drum or roller in contact with a strip of paper when a desired symbol is in the print position is aligned. As in the case of the arithmetic unit, j ~ here too, with a corresponding modification of the logic control circuit, different ones if necessary Printout devices are used.

In Fig. 2, the total drilling time register 20, the Total depth register 22, the device cost register 24. the wellhead cost register 26 and travel time register 28 are shown, each of which is a four-digit decimal number to save and an 8421 binary encryption key Able to provide a decimal representation of each digit. Each register thus consists of four levels, namely one each Level for each digit. In register 20, stages 20a-20c / store a maximum time representation of 999.9 hours. The register stages 22a-22c / store a maximum drilling depth of 9999 feet, levels 24a-24c / store a representation of equipment cost - .0 of up to $ 9999 per hour, levels 26a -26c / save a drill head cost representation of up to $ 9999, while levels 28a -28c / have a maximum estimated travel time of up to 999.9 hours to save. -, 5

Register driver stages 58 and 60, respectively, are assigned to each register 20 and 22, which are exemplary for a expedient device for confirming registers 20 and 22 depending on one from the outside injected signal. Devices of this type, which are provided as multi-digit registers, are commercially available available.

A preferred device of this type is the decade counter manufactured by the Durant Manufacturing Company of Milwaukee, WiscV USA under the designation Unipulser Series 49,000. Of course, other, equivalent, commercially available devices can also be used. As is functionally shown for the counter stage 20a, each stage 20.1-20c / and 22a-22c / has four inner contact sets each, which can be closed in the correct scheme to generate the binary-encrypted 8421 decimal code when the register is dependent on input signals to the Driver stages 58 and 60 switched through. One contact of each contact pair is connected to a line 62a-62c / a four-core cable 62, while the other contacts of each contact pair are connected together to a single input. In the counter stage 20.7, this input is formed by the 7V signal that is generated in the logic program control unit 18 by actuating the work sequence unit 40 (FIG. I). As will be explained in more detail, the input signal Ta is always high, except when the information contained in a counter stage is to be "read out", so that the four contact pairs have high signal levels or open circuits on all four lines 62a-62c / of the cable 62 deliver. When the counter stage 20a is to be "read", the 74 signal drops and the signal pattern on the four lines of the cable 62 is determined by the closing pattern of the contact pairs. In the illustrated arrangement, the pairs of contacts 8 and 2 are open so that the signals on lines 62a and 62c remain high. Contact pairs 4 and 1 are closed so that the low value of the 7 "<i signal appears on lines 626 and 62c /.

Since all the output signals of register stage 20a are high regardless of the stored count, provided that signal Ta is not low, stages 20 £>, 20c and 20c / can be connected together to lines 62a-62c / in the manner shown. The stage 20 £> is then "read" by the signal 7s from the work sequence unit 40. Similarly, stages 20c and 20c / are read by the signals Tt and Ts », respectively.

The total depth register 22 corresponds to the register 20. The contact pairs of the stages 22a-22c / are in turn connected together to the relevant lines 62a-62c /. The stages 22a-22c / are "read" by signals Γ26-T29 from the unit 40.

Functionally, the output signal properties of the device cost register 24, des Boring head cost register 26 and travel time register 28 are identical to those of registers 20 and 22. Each counter stage of registers 24-28 provides over the appropriate set of contact pairs on the lines 62a -62c / a binary-coded 8421 decimal output signal. when it is actuated by the "read out" signa-Ie from the unit 40. In the case of the Embodiment steps 24a-24c / are carried out by the Signals_7i6-7i9, the stages 26a-26c / by the signals 7 ^ -724 and_the stages 28a-28c / by the signals 7io— Γι 2 and 7m »read«.

In contrast to registers 20 and 22, registers 24-28 are only used to store preset values Values of constant expressions and factors as distinct from variables, which are always up to date must be brought. The registers 24-28 can therefore be set manually and not automatically. While numerous devices of this type are available, the preferred devices are through Thumbwheel adjustable switches, for example those from Digitran Company, Pasadena, CaIVUSA, Switch manufactured under the name Digiswitch or Miniswitch.

When looking at all registers 20-28, the result is

it can be seen that when one of the register stages is assigned an associated 7 "signal from the work sequencer 40 is actuated, a binary encrypted resp. ßCD8421 signaling scheme occurs.

The data supplied via lines 62a-62c / are coupled via lines 63a-63c / to associated AND gates 61a-61c /, which are triggered by a CLK 4 signal to be described later. The ßCD signal patterns on lines 63 serve as operands for the calculations required to solve equation (2), which are carried out for arithmetic unit 14 (FIG. 3) as a function of signals from logic control unit 18 (FIG. 4) be performed.

As mentioned, the system is built around the computing unit; the operating command and the data input formats are determined to a certain extent by the particular computing unit used. According to FIG. 3, the EA S 100 device accepts numeric input signals in decimal format, one digit each, starting with the most significant or highest digit. All data entry, retrieval and internal processing are controlled by a master clock 64 operating at 200 kHz. Each symbol is entered as a function of two signals X _n , V _n that appear at inputs Xo- Xi and Yo-Yi . Under the control of the clock 64, the arithmetic unit 14 scans the Y and V inputs at high speed by applying signals to the X inputs in sequence and mapping any V input signals present to the scanned -Y input.

This arrangement is suitable for the delivery of the input data by means of a cross-point matrix 65 with eight columns Vo- Yi and four rows Xa-Xi controlling switches 66a-66 / set. In the embodiment shown, switches 66a-667 'are shown as pairs of contacts controlled by associated relay coils 68a-68 /, but a transistor matrix or the like could of course be used instead.

As mentioned, the inputs are scanned by applying signals to the X inputs in sequence. By actuating one of the relay coils 68a-68y in a manner to be described below, a circuit is therefore closed via selected X and V inputs, as a result of which a symbol is input into the arithmetic unit 14.

The operating commands for addition, multiplication, division and summation as well as for entering decimal points or decimal points are supplied in the same way as the numerical symbols. In this way, five additional crossing points are set by five switches 66k-66 (0) , which are controlled by assigned solenoids 6Sk- 68 (0), which the functions "decimal point input", "add", "multiply", "divide" or . »Summation (=)« are assigned. Although the arithmetic unit 14 can also perform a subtraction, such a subtraction is not required for the solution of equation (2), so that no crossing point needs to be provided for it. As in the FaI! of the numerical data, the sequential actuation of the X "inputs and the activation of one of the relay coils 68a-68 (0) result in the closing of the circuit selected between the X and V inputs with the input of the desired operating command.

Since the data and command signals are entered individually one after the other, a must first be entered The first operand must be entered, that of the required arithmetic command and then a second Operand is followed. However, since each operand is entered in individual symbols, the previously entered operation does not take place sooner.

Ki den until a subsequent operation command is entered. Otherwise the system could not "recognize" that all digits of the operand have been entered. The input of a calculation command through one of the contact pairs 66 (1) to 66 (n) consequently has the consequence that

i) the arithmetic function is temporarily stored and this function is only carried out when at least one subsequent numeric digit has been entered by means of one of the contact pairs 66a-66j, followed by a further arithmetic command.

By entering to the Summierkommandos means of the contact pair 66 (o), the latch registers are effectively cleared in the computing unit 14, and a multiplex output indication of the result of the previous calculation in 8421-sscd-shape

2> a set of outputs labeled ßl, ß2, S4, ß8 are supplied. For each ßCD output scheme, an output signal is also provided on one of the selection lines PQ- PI in order to determine the position of the ßCD digit in an eight-bit configuration

Identify 3d rendering sequence. A similar ad is ensured by a PD output signal for setting a decimal point in a display.

The output signals of the arithmetic unit are identified by a series of joint numbers 70

j, output clutch stages coupled, the respective SCD signals with Sß1, Sß2, Sß4 and Sß8, the position signals with SPO-SP7 and the Decimal point signals are labeled SPD.

There are also three additional input functions

α »provided for the arithmetic unit 14, namely a register clearing function, an input free function and a decimal point setting function. The actuation signals for these functions are transmitted to the unit 14 at the relevant inputs 72, 74 and 76

4 ·, magnetic coils 84, 86 and 88 controlled switches 87, 80 or 82 delivered.

The respective solenoids 68a-68j are actuated by a BCD- decimal converter 90, which is based on previously in connection with FIG. 2 described

-, in the above manner, receives the binary-coded decimal signals via lines 63a-63c / from the input register unit 12. The converter 90 can be constructed in any way. For example, integrated circuit units are commercially available, such as the βCD decimal decoder manufactured by Signetics, Inc., Sunnydale, CaIVUSA under the designation Model No. 8251. The input signals appearing on the lines 6Zs- 63c / can be supplied by input gate circuits contained in the converter 90 which operate under the control of a key signal CLK 4 which is supplied via a signal path 92 and is to be described in greater detail below. Every time the key signal CLK 4 appears on the line 92, the 8421-ßCD signals on the input lines 62 are converted into a "1-out-of-10" signal, which is sent to one of the ten "with the relevant magnetic coils 68a — 68 / connected outputs appears.

The program control for the operation of the arithmetic unit 14 and for the data input via the matrix 65 is carried out by the logic control unit 18 according to FIG. 4. As before in connection with FIG. 1, the control unit has a 60 Hz clock generator 44, a calculation interval selector 46, a six-minute clock generator 32, a sequence unit 40 and an associated clock generator 42 .

The operation of the selector 46 and the six minute clock is based on a 60 Hz reference voltage source, since the power supply for the entire system can be used for this purpose, so that a lowering of the considerably higher frequency of the reference signals used elsewhere in the system is avoided.

The selector 46 consists of a low frequency clock which is constructed in any known or desired manner using commercially available frequency components and other logic elements and which generates output pulses at intervals of 60, 30, 15 and 6 minutes. The 60-, 30- and 15-minute interval pulses are used selectively to initiate calculation sequences in a manner to be described below. The 6-minute interval pulse switches the drilling time register 20 on via the AND gate 30 (FIG. 2). A 5-second interval pulse is also supplied to establish a start-up delay for the printout device, which will be explained later.

The clock 94 has a reset input that all internal clock circuits in the one Counting "zero" is able to reset the corresponding state when the reset input signal is low and the system is live. The reset is used every time the system is switched on, d. H. when the system is energized to ensure that the clock 94 continues to operate a count "zero" begins.

The reset is carried out by a circuit with an RC delay network 96, which is connected between the power source and ground, and two converters 98 and 99 connected in series. The time constant of the toilet network 96 is chosen so long that after switching on the The system stabilizes the operation of all circuitry before the input to converter 98 goes so high that the converter output goes low. This means, of course, that the output signal lying on a line 100! of converter 99 remains low throughout the initial stabilization period and clock 94 remains reset during this period of time. After the capacitor contained in the /? C network has charged so much that the output signal of the converter 98 can drop, the output signal of the converter 99 increases, whereby the clock 94 is enabled, depending on pulses from the 60 Hz Clock 44 to be able to advance.

The switching of the clock 94 during the actual drilling process is controlled by an on / off switch 102 . In the OFF position, the switch 102 connects a line 106 to ground, while this is connected to the power source via a resistor 104 in the ON position. Line 106 is connected to a hold input of clock 94 which operates a gate circuit which couples the 60-H7 input signal to the internal logic circuitry.

The switch 102 also supplies an active signal on a line 106 labeled OPER which activates the AND gates 30 and 34 (FIG. 2)! or switches through. As long as the switch 102 is not in the ON position, neither the clock nor the registers 20 and 22 can advance but keep their previous count. In operation, the drill operator turns switch 102 ON when drilling is taking place and OFF when drilling is interrupted. If desired, this can also be done automatically. The further counting of the drilling time and the drilled depth can therefore only take place when the drilling work is in progress.

According to FIG. 4, the calculation interval is selected by a three-position switch 108 which supplies the 60-30- and 15-minute interval pulses as input signals to an OR gate 110 , the output of which is a "set" input signal for a start flip -Flop 112 forms its ONE output via a line 114 for actuation of the various devices of the printer.

2 (i kers 52 and also to activate an AND gate 116 is switched. The other input signal for the AND gate 116 is formed by the five second interval pulse from the low frequency clock 94. The AND gate 116 thus works for five seconds This sets or initiates a computation cycle flip-flop 118 which initiates the actual computation cycle in a manner to be described below.

A second input to OR gate 110

in is supplied by a manual start switch 119 in order to enable a separate initiation of a calculation cycle independently of the hourly, half-hourly or quarter-hourly actuation.

The reset of the start flip-flop 112 takes place

j-, via line 120 by the main reset signal (MRT) generated by an OR gate 122. The gate 112 receives as input signals a program end signal (PEND) on a line 124 and a manual reset signal from a manual reset

4 (i switch 126. The M /? 7 "signal is also applied to an OR gate 128 , the second input signal of which is provided by the OR gate 110. The OR gate 128 generates a further reset signal on a line 130 ( MRTA), which resets the calculation cycle flip-flop 118 and thereby ensures that this flip-flop is reset at the beginning of a calculation cycle.

The remainder of the circuit according to FIG. 4 comprises the work sequence unit 40 and the associated clock generator 42, the task of which is to initiate and control the data and operating command input signals for the arithmetic unit 14 and also to initiate and control the data printout at the end of each computation process steer.

In connection with these functions, it should be noted that when the master clock 64 is the Computing unit operates at a frequency of 20OkHz, an interval of less than 16 milliseconds is necessary to enter a symbol or the

ho perform addition function. The maximum time spans for multiplication and division are 80 and 120 milliseconds, respectively. Each for the calculation The required data input and addition interval is therefore set to around 16 milliseconds. To the

h ^r, simplification of the circuit configuration, both the multiplication are as well defined the Divisionsintervallc to 120 milliseconds.
With regard to equation (2), it can be seen that

the basic operating program requires the following steps:

Enter the elapsed time (four digits plus decimal point).

Entering the addition command,

Enter the estimated travel time (four digits plus decimal point),

Enter the multiplication command,

Enter the device costs (four digits), enter the addition command,

Enter the drilling head costs (four digits),

Enter the division command,

Enter the total drilling depth (four digits),

Input of the summation command.

Assuming a separate program interval for each digit (and the decimal point) of the data input sequence and for each operation command, it can be seen that at least 27 program steps are required to solve equation (2) _ <o.

As will be explained in more detail, it is also necessary at the beginning of each calculation interval to clear the arithmetic unit and to set a decimal point reference value for adaptation to the y · decimal points of the total drilling time and the estimated travel time. In addition, a program interval is provided for printing out the calculation result and, finally, a program idle state is required in order to prevent the arithmetic unit from being operated between successive calculations. As a result, a total of 31 program intervals or states are required, which are defined by the clock generator 42 in conjunction with the sequence unit 40.

The clock generator 42 comprises a main pulse generator 132 and a main logic timer unit 134 on. The pulse generator 132 generates a pulse train from a number of pulses of about 34 Microsecond duration and with a repetition rate of about 1.65 microseconds. The pulse generator 132 can be constructed in any way, e.g. B. using two in a closed loop switched monostable multivibrators, one of which has an operating frequency equal to the duration of the Clock pulse and the other has an operating frequency equal to the repetition frequency of the pulse train.

The output of the pulse generator 132 is input to the unit 134 as an input. The latter is essentially a decade counter with an additionally assigned logic circuit for generating different output pulses in a specific time ratio for each working cycle. This relationship can best be seen from Fig. 7, in which the signal form (a) indicates the main clock pulse series (MCLK) and the signal forms (b) - (e) the so-called CLK 4, DCLK, TCLK or Display CLK B 9 waveforms.

The waveform (a) shows 10 MCLK pulses corresponding to one duty cycle of the logic main timing unit 134. The CLK 4 waveform shown in line (b) of FIG. 7 begins with the trailing edge of the fourth MCLK- pulse and ends at the leading edge of the eighth MCLK pulse. As mentioned, this signal determines the multiplex readout interval for _h ^r> register 20-28 as a result of activation of the aND Gatter61 <7-61c /.

The DCLK signal according to line (c) of FIG. 7 consists of four pulses which run synchronously with the fifth to eighth MCLK pulses in each cycle. These pulses are used to actuate a data output shift register (still to be explained) during the printing process.

The TCL / C signal shown in line (d) of FIG. 7 represents a single pulse which occurs synchronously with the ninth MCLK pulse in each duty cycle, ie (approximately) every 16.5 milliseconds. The 7ULK pulse is mainly used to switch the work sequence unit 40 from one program status to the other and actuates a printout program sequence unit to be explained below.

Finally, the CLKB 9 signal shown in line (e) of FIG. 7 is a single pulse which occurs synchronously with the tenth Λ / CLK pulse in each cycle. The β9 clock pulse can be viewed as a delayed version of the TCLK pulse and performs certain reset functions in conjunction with the sequencer 40 as well as certain program advancement functions in conjunction with the print sequencer, as will be explained in more detail below.

With particular reference to work sequencer 40, it should be noted that for the computation of a Solving equation (2), thirty-one separate program states are required.

The program states are represented by signal outputs or output signals To - T32, which are represented by an "1-out-of-32" decoder 136 can be supplied. The selected state is indicated, for example, by a high signal identified at only one of the 32 outputs, while the remaining 31 outputs are identified as low stay, or vice versa. The operation of the decoder 136 is controlled by a binary signal scheme, provided by a 25 binary counter 140 over five lines 138a-138e.

The decoder 136 and counter 140 are constructed in any conventional or desired manner, however, preferably consist of commercially available integrated circuit elements. For example For example, the decoder 136 may consist of two "1-of-16" decoders of the Fairchild 9311 type, while the counter 140 can be formed from a four-bit binary counter (type Fairchild 9316) and a / K flip-flop (Fairchild 9000) can be interconnected in a manner known to those skilled in the art to form a 25-meter.

For logical reasons, the counter 140 has increment, reset and activation inputs, from those of the former, when an activation input signal is present, the counter through its 32 binary states able to switch through. In the presence of a reset input, the counter 140 becomes independent returned to its zero state by the other input signals.

The increment input signal is formed by the aforementioned TCL / C input signal, where the Counter responds to the trailing edge of the incremental pulse to effect a step change. As mentioned, the TCLAM pulse occurs every ten main clock pulses once each with a repetition frequency of about 16.5 milliseconds. As long as the activation signal is present, the binary counter 140 thus switches at intervals of approximately 16 milliseconds from one Binary state to the next, during that represented by the 7V outputs of decoder 136 Program status advances at the same speed.

While the counter 140 is running through its duty cycle, the various operations controlled by the program states To - ! "^ Are performed. Table 1 below shows the operations associated with each program state.

Table 1

Program status

T ₀ Ti T ₂

T ₂₄
T ₂ S
T _2b T ₂₁
7 " ₂₈
7 " ₂ 9
7mm

surgery

Program retirement
Clear arithmetic unit Clear input registers of the arithmetic unit; Set decimal point for two decimal places
Reserve - No program function Enter expiry time - Enter expiration time in hundreds - Enter expiry time with tens - Enter expiration time in units - Enter expiry time decimal point - Decimal place (0.1)

Enter addition command Enter travel time - hundred digits Enter travel time - Enter ten-digit travel time - Enter one-digit travel time - Decimal point Enter travel time - tenths digit enter multiplication command Enter device costs - thousand digit

Enter device costs - hundreds digit

Enter device costs - Enter tens of device costs - units digit Enter addition command Enter drilling head costs - thousand digit

Enter drill head costs - base

Enter drill head costs - tens digit

Enter drill head costs - Enter division command in units Enter drill bits - Thousands Enter drilling depth - Enter hundreds digit drilling depth - Tens digit Enter drilling depth - units digit Enter the summation signal (=). Initiate the sequence of expressions

There are various points to consider in connection with Table I. First, the 7b state is referred to as the idle state. This is the state in which the decoder 136 is when no computation is in progress. The zero state is reached when the binary counter 140 advances from a count of 31 in response to the next TCLK pulse. Another important point is that the computation sequence described above requires only 31 program states, including the idle and expression sequence states. In the case of a decoder with thirty-two switching states, there is therefore a reserve state, which is defined as state Ti .

Furthermore, it should be noted that because of the sequential input of the data for the arithmetic unit 14, an arithmetic command is only issued when the following arithmetic command is already available at time Γ15 instead of open

in a similar way, the _{multiplication entered at state T) 5} only takes place at program state T20 , while the division command entered at Γ25 is only effective at time Tso.

The ones to carry out the multiplication and

The time required for dividing operations is much greater than that for data entry and addition operations. Nevertheless, the data entry during the program intervals T20 and T10 only requires the regular 16.5 milliseconds. As will be explained in more detail, the command input intervals which relate to the “input of the addition” command or the input of the summing command assigned to the program states T20 and Tm therefore have a duration of 16.5 milliseconds during the beginning of the

>) Program intervals T21 and Ts \ are delayed in order to be able to carry out the arithmetic operations of multiplication and division. The command input intervals Tx and Γ30 are designated with T ₂₀ M and T »«.
Both the modified program intervals Γ20Λ / and TnM and the actual calculation intervals T20 and 7 ″ io are determined by means of the activation control circuit for the binary counter 140 to be described.
As mentioned before, according to FIG

Γ) Sampling of the stages of the register arrangement 12 by various »7V signals, which can be supplied by the output signals of the decoder 136 coupled via corresponding converters. In practice, however, the Fairchild 9311 decoders preferred for the construction of the decoder unit 136 supply the output signals in negative form, ie in the form of a low value for the relevant selected state and in the form of high values for all unselected states. These signals are used for the immediate sampling of the

■ r> register levels used.

The operation command signals assigned to the program states specified in Table 1 above become also supplied directly by the output signals of the decoder 136. More precisely, they are

Ίο Magnet coils 68 / c— 68 (0) coupled to the relevant AND gates 142, 144, 146, 148 and 150, for which the activation inputs are supplied by the main logic timer unit 134 by the CLAT 4 signal. The activation input signal for the UN D-GaI-

Yi ter 142 is provided by an OR gate 152 which receives as its input signals the signals Tl and Π3 from the decoder 136th Table 1 shows that these signals are the input commands for the decimal points of the total drilling time or the

ω) represent the estimated driving time.

The enable input to AND gate 144 is provided by OR gate 154 which receives as its input signals 79 and T ₂ m , respectively. From Table 1 it can be seen that these signals

(y-j correspond to the input of the addition operation command.

In a similar manner, the activation inputs for the AND gates 146, 148 and 150 by the

Signals Γ15, Γ25 and Γ30 are supplied which, according to Table 1, correspond to the input signals for the multiplication, division and summing processes.

The initial activation-setting processes, which take place during the program intervals Π and T2 , are carried out by two AND gates 156 and 158, both of which, as in the case of AND gates 142-150, are carried out by the CLK4 signal from the main logic Timer unit 134 are activated, the AND gate 156 receiving its control input signal from an OR gate 160 , which in turn receives both the program status signal Ti and a manual reset signal from switch 126 (FIG. 4). When the AND gate 156 is actuated, the magnetic coil 84 and the associated switch 78 are actuated in order to deliver the “free” instruction for the arithmetic unit 14.

The control signal for AND gate 158 is provided by program status signal T2 . When the AND gate 158 is activated, the magnetic coils 86 and 88 and the associated switches 80 and 82 are actuated in order to deliver the free input and decimal point setting commands for the arithmetic unit 14. In addition, the AND gate 158 actuates the solenoid 68c through a diode 162 to close the crossing point 66c. As mentioned, this generates the numerical input signal “2” for the arithmetic unit 14. In conjunction with the decimal point setting input signal from switch 82, the output format for the arithmetic unit, ie two decimal places, is determined in this way.

In the following, the generation of the extended program intervals Γ20 is now based on FIG and Γ30 as well as the normal long intervals 7 "20M and r30M.

The activation input signal for the binary counter 140 is supplied by the ONE output signal of an activation flip-flop 164 , the actuating input signal of which is supplied by an OR gate 166. The first input signal for the OR gate 166 is formed by the START signal from the computation cycle flip-flop 118. The second input signal is supplied from the output of the monostable multivibrator 168 which is delayed by 120 milliseconds and which, after triggering, generates a short output pulse of 120 milliseconds and which is triggered or triggered via a delay circuit 172 by the output signal of an OR gate 170. The inputs to OR gate 170 are provided by program status signals 7-20 and 7-30.

The reset input signal for the activation flip-flop 164 is provided by the output signal of an OR gate 174 which receives as its inputs the multivibrator trigger signal from the delay circuit 172 and the output signal of another OR gate 176 to be described later.

The task of the activation flip-flop 164 and the multivibrator 168 is to determine the duration of the intervals 720 and Γ30. As mentioned, these are the intervals during which the multiplication and division operations actually take place and those of the normal. Length can be extended from 16.5 milliseconds to around 120 milliseconds. At the beginning of the interval Γ20 or T30, the OR gate 170 and the delay circuit 172 operate to supply a reset signal for activating the flip-flop 164 via the OR gate 174. When the flip-flop 164 is reset, the binary counter 140 is deactivated, so that it only responds to further TCZ-A pulses when the activation flip-flop has been brought back into the set state.

At the point in time at which the activation flip-flop 164 is reset, the multivibrator 158 is triggered in order to initiate the 120 millisecond long interval. At the end of this period of time, an output pulse is supplied to the control input of the activation flip-flop 164 via the OR gate 166. This in turn reactivates the binary counter 140, so that the next signal TCLK switches the decoder 136 either to the state Γ21 or to the state Γ31.

The instruction entry operations that take place during the program intervals do not require the lengthened or extended time interval which, as mentioned, is required for the division and multiplication operations. The necessary command input signals T2QM and T30M are generated by an interval flip-flop 178 which receives the output signal of the delay circuit 172 as its set input signal and the TCL / C signal from the logic unit 134 as its reset input signal. The ONE output signal of the flip-flop 178 forms a control input signal for two AND gates 180 and 182, which receive the signals 7 "2O and Γ30 as the second input signal. The AND gate 178 becomes immediately after the start of the intervals Γ20 and 7 "30 is triggered by the output signal of the delay circuit 172, whereby the AND gates 180 and 182 are activated, one of which operates depending on which of the signals 7" 20 or Γ30 is present , 5 milliseconds after the beginning of the interval Γ20 or Γ30 - the flip-flop 178 is reset and the AND gates 180 and 182 are deactivated. As a result, the signals Γ20Μ and T30M - with the exception of the extended intervals 720 and Γ30 - are essentially the same Duration like the other program intervals.

The expression state 7 ~ 31 differs from the previously described program states in that the operation of the arithmetic unit is terminated and it is only necessary to supply the result of the calculation in the previously described manner in the binary encrypted (BCD) 8421 multiplex output format. During the interval Γ31, the multiplex data are temporarily stored by the arithmetic unit as static values that are compatible with that of the printing device used. A printout program is then carried out during which the data is actually printed out.

A suitable device is used for the temporary storage of the calculation result a shift register in which the output signal of the arithmetic unit 14 is in the form required for the printout Order is saved.

The data stored in the shift register are then displayed in individual symbols with a the speed of the printing device adapted to the operating speed of the printing device fed. Save during the interval 7 ~ 31! the Shift register also reads the drilling depth data from input register 22 to be used along with the To print out calculation results.

F i g. 5 illustrates a convenient slide

gis / cran arrangement with fifteen four-bit shift gisic units, for example of the Fairchild model 9300. To simplify the description and illustration, the individual stages are designated SR 15 - SR 15. The shift register stages SR 1 - SR 15 have three control inputs, that is to say parallel input inputs labeled PE 1 - PE 15, clock inputs labeled CP \ - CP 15 and Ilauptrückstelleinängc labeled MR. Each shift register SR 1-15 also has four parallel data input inputs through which all four-bit positions are set when both the PE and CP input signals are present at the same time. The shift register stages SR: 1 - 14 each provide an in-line output signal from the respective fourth bit position to a set input of the subsequent stage, while the stage SR 15 their output signals in with Dl, D2, D 4. D8 designated parallel form via associated output lines 184a -184d gives up. The latter are also connected to a four-input OR gate 186 which emits a D-zero output signal via a converter 188 , the task of which is to indicate that the output signal of the shift register stage SR 15 is zero. Thus, when all of the inputs to OR gate 186 are low, the output of converter 188 is high. Conversely, if one of the inputs to OR gate 186 is high, the latter operates and the output of converter 188 is low. The D zero signal is used to control a logic zero suppression circuit to be described.

The parallel input signals for the shift register stage SRi. SR2 and SR4-9 are supplied by the signals SBh SB 2. SB 4 and SB 8 from the output coupling stages 70 (FIG. 3) of the arithmetic unit. The parallel input signal for the shift register stage SR 3 is, like F i g. 5 indicated, hardwired to represent the decimal point symbol code word. The parallel input signals for the stages SR 10 and SR 11 are also defined to form “zero” inputs; the latter form gaps in the printout format in a manner to be explained below. Finally, the parallel inputs for the shift register stages SR12- SRiS are supplied via lines 63a-63d from the input register 12 (FIG. 2) in order to supply a drilling depth reference value to be included in the printed result.

The control of the data input and transmission to the shift register stages SR 1 - 15 is performed by a in Figure 6 is shown a logical shift register control unit 190 in the form of a number of AND and OR gates such an arrangement that they P. necessary Cp and. Generate £ signals for the shift register stages. For this purpose, a shift pulse signal SHP is generated by an AND gate 192 as the input signal. The latter receives the DCLK signal at its inputs from a main logic timer unit 134 ( FIG. 4) and a D shift signal , which is still produced in a manner described by the expression control circuit.

The shift register control unit 190 also receives as an input signal the data position signals SPO-SP7 from the output coupling stages 70 of the arithmetic unit, the program interval signals 726-729 and Γ31 from the decoder 136 (FIG. 4) and the signal CLK B 9 from the main Timer unit 134.

The functional structure of the logical unit 190

is evident from the logical equation that characterizes their operation. For simplification, the output signals PE 1 - / '. /; ". 15 and Q1-O15 of the shift register control unit 190 are therefore listed in Table 2 below.

Table 2 P.E. 15th CpI - Cp 15 PE 1 - SPO 731 CpI = SHP 4 PE 1 = SPl 731 Cp2 = SHP 4 PE2 = 729 Cp 3 = SHP-I P. £ .3 = SP 2 • 731 Cp4 = SHP-I PE4 = SP 3 731 Cp 5 = SHP 4 PE5 = SP 4 731 Cp6 = SHP 4 P. £ .6 = SP 5 • 731 Cp7 = SHP- \ P.E.7 = SP6 ■ 731 C _p 8 = SHP-I PE8 = SP 7 • 731 Cp 9 = SHP 4 P.E.9 = 728 CpIO = SHP 4 PE 10 = 729 CpIl = SHP 4 PEll = 729 Cp 12 = SHP 4 P. E. 12 = 728 Cp 13 = SWP4 P. £ .13 = 727 Cp 14 = SHP 4 P. £ .14 = 726 Cp 15 = SWP4 P. E. 15 = - PEl - PE2 - CLK B9 729 - PE4 - PE5 - PE6 - PE7 - PE8 - PE9 728 · CLK B9 - 729 CLK B9 - 729 CLK B9 - 728 CLK B9 727 CLK B9 - 726 CLK B9

As mentioned, for the parallel input of

π data in one of the shift register stages, the signals CV and PE can be present at the same time. The logical expressions for the input signals Cp therefore contain an expression which reflects the simultaneous presence of the relevant input signals P £.

4 (i In the case of the expression for PE 1, it can be seen, for example, that the parallel input to the shift register stage SR 1 takes place during the program interval 731 when the digit signal SPO from the coupling stages 70 of the arithmetic unit 14 is present,

-n indicating that the outputs SP1, SP2, SP4 and SP8 appearing ßCD data the first time frame in the multiplex output cycle correspond. This is the most important digit in the calculation result. During the time frame SPO

The assigned digital data are entered into the shift register stage SR 1 within the program interval 731. Similarly, the shift register stages SR 2 and SR4 SR9 by the relevant time frame SPL SP 7 are activated, which occur during the program interval 731, in order to store the second to eighth digit position of the calculation output signal corresponding data.

The shift register stage SR 3 does not store part of the calculation, but rather that part the decimal point representing the output display The parallel input input for stage SÄ 3 can therefore be activated at any time; the selected point in time is during the program interval 729 at the point in time of the pulse CLK B 9.

b5 The shift register stages SR 10 and SA 11 are both arranged in such a way that, as mentioned, they store all zeros. As a result of the programming of the zero suppression logic circuit, the zeros in these will become

Positions are suppressed, ie a space is »printed out«, which separates the symbols representing the calculation digits from one another. The parallel input of the zero data into the shift register stages SR10 and SR 11 takes place during the ^r > pulse CLK B9 of the program intervals Γ28 and 7 ~29, as indicated by the logical expressions P. L ⁷ . 10 and P. Eil as well as O10 and C _t \\ is indicated in Table 2.

The reference data for the drilling depth part of the expression in FIG. 15 is obtained directly from the input register 22 in the aforementioned manner. Since the data output of the input register appears on the lines 63a-63d on a time-division basis, the shift register stages SR 12- SR 15 for recording the drilling depths i> are only activated during the relevant time intervals.

It can be seen from Table 1 that the time intervals for the four digits of the drilling depth data are defined by program intervals 7-26-7 "29, with the most important digit (ie the thousand digit) being defined by the interval 7-26. As in the case of the decimal point and the zero position data, which are stored in the shift register stages 3, 10 and 11 , the shift register stages SR 12-15 are actuated as a function of the pulses CLK B% occurring during the relevant intervals T. During the program interval Γ26 , therefore, the shift register stage SR 15 fed in, during the interval Γ27 feed into stage SR 14 etc.

In short, printing takes place by sequentially shifting the contents of each shift register stage by one stage in the downward direction and by actuating the printing device with one symbol each based on the data appearing in the shift register stage SR 15 at this point in time. The logic control unit r> for this process is shown in FIGS. 4 and 6 in connection with the signal forms (Q to (u) according to FIG. 7 are shown.

According to FIG. 4, the printing process is initiated at the end of the program interval Γ31 by a printing cycle to flip-flop 194 , which is set or triggered by an AND gate 196 , which has as its input signals the signal TCLK from the main timer unit 134 and the output signal Γ31 of decoder 136 receives. As mentioned and as g in rows (Q and (g) in accordance with F i. 7, the program interval 7 '31 starts at the trailing edge of the associated pulse TCLK. For this reason, the AND gate can until the next pulse TCLK, ie pulse occurring at the end of the program interval Γ31 . This state is shown in Fig. 7 in line.

The last-mentioned pulse TCLK switches the binary counter 140 and the decoder 136 from the state Γ31 to the state TO on, as shown in line (i) of FIG. 7 , thereby conditioning an AND gate 198 and also actuating an AND gate 196. This generates a pulse Γ31 TCLK , which triggers the print cycle flip-flop 194. The resulting signal SM at the ONE output continues to condition the AND gate 198. The immediately following pulse CLK B 9 (cf. line [k ] of FIG. 7) the AND gate 198 and supplies the reset signal both for the binary counter 140 and for the associated activation flip-flop 164, by which the counter 140 is prevented from switching on depending on further pulses TCLK, see above that the decoder 136 is kept in the 7b or idle state during the remainder of the operating cycle.

The signals PM and 7 "3I TCLK are also applied to the circuit of FIG. 6. More specifically, the signal Γ31 TCLK is applied as the one input to an OR gate 200 which is connected to the set input of an expression control flip -Flops 202. The zero output, labeled PRNT , of flip-flop 202 supplies a conditioning input signal for an AND gate 204, which in turn supplies the conditioning input for a further AND gate 206. The latter is connected to the setting input of a data shift flip -Flops 208 , the ONE output of which supplies the shift D. The reset input for the flip-flop 208 is provided by an AND gate 210 which is connected to the ONE output of the print control flip-flop 202 labeled PRNT AND gates 206 and 210 receive as control inputs the signal CLK B9 from master timing unit 134 ( Fig. 4).

As mentioned, the 7 ~ 31 TCLK signal triggers the print control flip-flop 202 which activates the UN D gate 210 and deactivates the AND gate 206. The next signal CLK B 9 therefore resets the shift control flip-flop 208 so that the D shift signal is held low.

The Γ31 TCLK signal is also applied as the one input to an OR gate 212 which is connected to the incremental input of a four-bit binary counter 214, which is preferably a device of the Fairchild No. 9316 or the like. acts. The counter 214 receives the signal PM from the print cycle flip-flop 194 (FIG. 4) as its activation input signal. Since both signals PM and T3 TCLK are present at the same time, the counter 214 is from its zero state, in which it was reset by the signal MRTA from the OR gate 128 according to FIG. 4 at the beginning of the printing of the calculation, to a count of One switched on. The resulting binary position consisting of four bits is input to an "1-out-of-15" decoder 216, for example of the Fairchild No. 3911 type, with an unoccupied output state, which selectively activates one of five output lines for controlling the printing device.

As noted, the printing apparatus operates to selectively engage transversely spaced printing hammers with symbols arranged in circumferential rows around a rotating printing drum. In the presence of a column signal, the print hammer is not yet actuated, but rather the print hammer logic control circuit is conditioned so that when the print drum is appropriately positioned to print the desired symbol, the print hammer is actuated .

The signal 731 TCLK also actuates, via an OR gate 217, a logical print control unit 218, the construction details of which do not in themselves constitute part of the invention, since in practice they are directly determined by the construction of the printing device. In the interests of simplicity of illustration and description, the details of control unit 218 are not illustrated.

In general, however, it can be said that as the printing drum rotates, a sequence of binary encrypted decimal reference signals is generated which indicate the drum position. These signals are connected to the lines 184a-184d

lying signals Dl, D2, D4 and D6 compared, which represent the symbol to be printed. When the print drum reference signals correspond to the respective signals D1, D2, D4 and D8, the print hammer selected by the column actuation signals from the decoder 216 is actuated and the desired symbol is printed out. The actuation of the print hammer is indicated by the presence of a trigger signal (TRIG) on line 220, which is followed by an “end dcs trigger” signal (EOT) on line 222 at the end of the printing process.

Since the column 1 output signal of the decoder 216 is selected by the signal 7 "31 TCLK and the logical print control unit 218 is also triggered, the printing device immediately begins to compare the position of the rotating print ram! With the data supplied by the shift register stage SR 15 , namely with the thousand digit of the drilling pitch reference value supplied by the input register stage 22. If a match is achieved, the trigger signal is generated and the symbol is printed out, and the ΕΟΓ signal is then generated.

In view of the above, it can be seen that the angular position of the printing drum at the time of the signal φ31 TCLK determines how quickly the printing drum reaches the position required to print out the desired symbol. In the case of the aforementioned Suwa Seiko EP 101 printing device, one rotation of the printing drum takes about 288 milliseconds; this thus represents the longest possible time span between the signal Γ31 TCLK and the trigger signal. During this interval, the binary counter 214 is not incremented because the signal Γ31 TCLK is not repeated, and the other incremental input signal supplied by the OR gate 212 for the Counter 214 is generated by an AND gate 224, which receives the signal PRNT \ om print control flip-flop 202 and also the D-shift signal from shift control flip-flop 208 as its input signals. The latter is equal to zero at this point in time, since the shift control flip-flop is reset and consequently the successive rCLK signals do not actuate the AND gate 224 to increment the counter 214.

After completion of the printing process for the first column, the ΕΟΓ signal resets the print control flip-flop 202. This deactivates AND gate 210 and activates AND gate 206 through AND gate 204. The next CLK S9 signal then triggers the shift control flip-flop 208 so that the D shift signal goes high. This is illustrated by the signal form (1) according to FIG. (The immediately preceding signal TCLK does not advance counter 214 because the D shift signal was still low at this point in time.)

If the D shift signal is now high, the AND gate 192 is conditioned so that the next pulses DCLK (cf. line / m / in FIG. 7) generate four pulses SHP which are sent to the logic shift register control unit 190 are applied and in line (s) of FIG. 7 are shown.

From the above table 2 it can be seen that all shift register stages SR 1-15 switch one after the other as a function of the four pulses SHP.

The data previously contained in the shift register stage SÄ 14 are transferred to the stage SR 15. They are also all in the stages

SRX-SR M forwarded to the next level.

From lines (f) and (m) of FIG. 7 it can be seen that a pulse TCLK occurs shortly after the last of the four pulses DCLK. This is applied to the AND gate 224, which is conditioned by the PRNT and D shift signals and emits a pulse via the OR gate 212 to advance the binary counter 214 from the "one" to the "two" state. This advances the decoder 216 to activate the column 2 output.

Simultaneously, the signal TCLK is input as one input to an AND gate 226 which receives the D shift signal from the shift control flip-flop 208 as its second input. When the D-shift signal is high, the TCLK signal causes AND gate 226 to operate to produce the XCLK signal on line 228. This signal is supplied via the OR gate 200 for resetting the print control flip-flop 202 and via the OR gate 217 for actuating the logical print control unit 218. The latter operates in exactly the same way as previously described for the actuation by the pulse φ31 TCLK, and therefore causes the data represented by the output signals of the shift register stage SR 15 to be printed out in the position of the second column. At this point in time, however, the data that appears represent the hundredth place of the drilling depth information.

A comparison of lines (f) and (J) of FIG. 7 shows that a signal CLK S9 immediately follows the signal TCLK by which the signal XCLK was generated. The CLK B9 signal is applied to AND gates 206 and 210, but the print control flip-flop 202 is reset and the AND gate 206 is deactivated. The AND gate 210 is, however, conditioned by the signal PRNT, and when the pulse CLK 59 arrives, the shift control flip-flop 208 is reset. The D shift signal therefore goes low and deactivates AND gate 192 so that the next train of pulses DCLK does not affect shift register control unit 190. The low D shift signal also deactivates AND gate 226, preventing the next signal TCLK from generating an XCLK S \ gna \ and also deactivating AND gate 224 so that the next signal TCLK neither generates a signal XCLK nor advances the binary counter 214. The reason for this is that the printing program has to be stopped for the maximum period of 288 milliseconds which the printing drum needs to reach the required position for printing out the symbol being processed at this point in time.

Once the second symbol has been printed, the EOT signal on line 222 is generated by the print control logic unit and the print control flip-flop 202 is again reset. The device then repeats the above-described operation for each of the remaining symbols with progressive shifting of the four bits into the fifteenth stage of the shift register, which is followed by printing out and re-triggering of the print control flip-flop by the ΕΟΓ signal.

After the data for the fifteenth column has been shifted into the shift register stage SR 15 as a function of the assigned pulses DCLK, the next pulse TCLK switches the counter 214 into the

fifteenth state, thereby activating the column 15 output of decoder 216. The pulse XCLK generated at the same time activates the print control unit and causes the last symbol to be printed out. The EOT signal then resets the print control flip-flop 202, whereby the AND gate 206 is conditioned and the subsequent pulse CLK B9 triggers the shift control flip-flop 208. Since the D shift signal then goes high, the next group of DCLK pulses advances the shift register again, but there is no further data to be printed at this point.

The TCLK pulse following the last-mentioned four DCL / C pulses generates an additional .YCL / C pulse and also switches the counter 214 to the "zero" state. The counter output signals, which are now all equal to zero, are switched via assigned converters 230a- 230d , the outputs of which are in turn connected to four inputs of an AND gate 232 having six inputs. The latter receives the signal PM and the pulse CLK B9 as further input signals.

When the counter 214 reaches the zero state, the immediately following pulse CLK S9 completes the conditioning for the AND gate 232, which then generates the described program end signal (PEND) on the line 124. This indicates the end of the computation cycle and the OR gates 122 and 128 generate the MRTA signal on line 130 to reset the print cycle flip-flop 194. The device then goes into the idle state in anticipation of the start pulse for the next cycle from the calculation interval selector switch 108 (FIG. 4).

As mentioned, the device according to FIG. 6 a device for suppressing zeros in Printout, both to delimit the drilling depth data and the calculation of the To ensure costs per unit of length, as well as to simplify the visual reading of the result. the Zero suppression is best understood by the fact that the expression is made up of fifteen Digits consists of the first four numbers - corresponding to a maximum of four digits in the reproduction the drilling depth - included, the next two digits are empty or spaces are, the next six Places up to six digits of the display of the cost per unit length can contain the next one Digit is a decimal point and the last two digits represent decimal digits. The zero suppression is therefore always necessary to determine the spaces in the fifth and sixth digits. at The first four digits are only suppressed by shifting the zeros to the left until another digit appears as a zero. Therefore, if the drilling depth to be printed is 909 feet, the zero will appear in the Thousands are suppressed, while the zero in the tens is not suppressed.

The zero suppression can also be done by moving right from the seventh digit to another Digit appears as a zero, whereupon zero suppression is no longer permitted.

For example, if the total drilling depth is 920 feet and the cost per foot at that depth is $ 5.75 the resulting expression would look like this;

920

5.75.

The zero suppression in accordance with the aforementioned requirements is ensured by a zero suppression logic circuit 123 which is designed in any way so that it satisfies the aforementioned requirements. The input signals are the four binary signals generated by the output signal of the counter 214 indicating the relevant position in the expression sequence and the D-zero signal from the shift register stage SR 15 (FIG. 5). If the D-zero signal occurs during one of the intervals in which a zero can be suppressed, an output signal for conditioning an AND gate 238 is generated on a line 236. When the trigger signal is generated by printout controller 218 and indicates that the print drum is in the appropriate position to print a zero, AND gate 238 generates a signal which is reversed by converter 240. The output signal from the latter is applied to the activation input of the decoder 216 and switches the latter off briefly in order to prevent the actuation of the print hammer for the relevant column. In this way the printing device does not operate when a zero is to be printed out, so that the column concerned is effectively skipped.

5 shows an additional display device in which the binary-coded decimal signals are applied from the coupling stages 70 of the arithmetic unit to a seven-segment decoder 242 which actuates an eight-digit display 244 made of light-emitting diodes. The relevant one of the eight digits or digits to be actuated is selected by the output coupler 70 by activating one of the signals SP0-SP7. The decoder 242 and display 244 operate in a conventional manner and further description is unnecessary.

Although the latter case the aforementioned expression only the result of the calculation and the Contains drilling depth, depending on the respective print capacity can obviously also be additional Data such as total drilling time. can be printed out.

As a result of the convenient data and command input to the arithmetic unit via a matrix of the in FIG. 3 The type shown can also have a direct arithmetic calculation option by arranging a Keypad for separate control of the matrix and function solenoid coils or a separate one Matrix can be provided with intersection points controllable by a keypad that correspond to the already existing Matrix 65 is connected in parallel. This allows the device on the one hand to carry out their pre-programmed functions described and on the other hand as a calculator for normal arithmetic Functions are used. Under these conditions the display could either be made by emitting light Indicator 244 provided by diodes, or by the printing device, or if desired done by both.

In addition 7 sheets of drawings

Claims (1)

Patent claims: 1. Digital data processing device for determining the optimal operating time of a Drill head according to the equation C = B + (T + D) R