DE2244943C3 - Input circuitry using a keyboard - Google Patents

Description

55

The invention relates to an input circuit arrangement as set out in the preamble of the claim 1 mentioned type & r

In a known input circuit arrangement using a keyboard for an electronic calculating machine (DT-AS 1099 766) are due to a manually generated start pulse clock signals are switched through to a binary counter which counts this clock signal © and emits a pulse when the zero position is reached, which, after running through a delay chain, blocks the gate circuit upstream of the counter again; the The runtime chain is one with the individual pushbutton switches Keyboard connected so that the running time depends on which key has just been pressed so that the Finally, the count reached characterizes the key pressed.

According to an older proposal corresponding to the preamble of claim 1 (DT-PS 21 11 519) is the number of between the key switches and the connection lines required for the integrated circuit are thereby reduced to a minimum, that from each key switch group a common line to one in the integrated circuit The coding matrix provided carries the clock signals staggered in time on its column lines is controlled. The coding matrix has many more, corresponding to the number of key groups formed Matrices upstream, each of these further matrices having a first immediately and a second above an inversion stage connected to the line coming from the relevant push button contact group Has control line. The control lines <hr additional Matrices are linked to their column lines in such a way that they are dependent on the clock signals only the column line assigned to a predetermined key is switched through to the coding matrix The row lines of the coding matrix then carry the binary coded characterizing the pressed key Signal. The additional matrices as well as the coding matrix must have the same number of key switches Have number of column lines.

The invention is based on an input circuit arrangement of the type mentioned in the preamble of claim 1 is also based on the task the number of terminals required on the integrated circuit as much as possible to keep it low.

This object is achieved by the features specified in the characterizing part of claim 1 solved

B <* i of the output circuit arrangement according to the invention a small number of that required between the key switches and the integrated circuit Connection lines achieved without the need for relatively complex coding matrices in the integrated Circuit are required.

Embodiments of the invention are given below described in more detail in connection with the figures. From the figures shows

F i g. 1 is a schematic block diagram of an inventive Circuit arrangement,

F i g. FIG. 2 is a simplified illustration showing the layout of the keys in the keyboard of the layout of FIG F i g. 1 illustrates

F i g. 3 is a timing diagram showing the relationship between the various in the arrangement of FIG. 1 used clock signal ™ vcrar.schsuikht

F i g. 4A and - "* time diagrams which illustrate the operation of the circuit arrangement according to the invention with the introduction of numeric keypad signals into the integrated circuit arrangement,
ΐ Fig.5 is a schematic BJock diagram of a

gp gg

Circuit arrangement for coupling key signals,

6A to 6C & vetaüsdjsulichen time charts g the operation of the arrangement of F i.,

7 is a schematic block diagram of a computer in which the Schahungsanordnung for

Coupling of the key signals from FIG. 5 applies comes

In the invention, as is known, integrated circuits with field effect transistors of the MOS type are used to receive the individual key signals. S flip-flops or registers are implemented within the integrated circuit by means of MOS transistors which are controlled by two-phase clock signals Φ \ and Φ _2. Four-phase or three-phase clock systems could also be used to control the writing and reading of information into the registers or from the registers; synchronously with. = m second clock signal Φ ₂ ι $ read out.

Most of the elektronii-'heü ■ —-ier work in series operation, with the now ^ risc. information is stored in the register ■ » > d üiui - -, in the invoice with the numerical information <hircb ^ ef ^r !., t serially supplied from the Ρ <». »·» ι «ι. The digit ^{clock signals y} T \, T2 ... Tie st ·, ¹ · - represent a time scale which shows the weights of the digits in the information circulating in series at the output terminal of the register, and which marks the limits of each word number { 16 digits in each word). The bit tacts signals t \, h, t? and u indicate the weights 8,4,2 and 1 in each digit.

G according to the preferred embodiment of the F i. 1, 2, 6 and 7, the digit clock signals Ti-T _{ib are used} to distinguish between different key signals. Furthermore, a combination of the clock signals Tie U Φι is used to create a reference time within each word time.

Fig. 1 shows a calculating machine with the keyboard KB, the manually operated numeric keys 0 to 9 for entering the numerical information in any order desired by the operator, and manually operated function keys χ, -τ-, = ... for entering the functional information having. The arithmetic unit is connected to the keyboard KB and other devices in order to carry out calculations such as adding, subtracting, multiplying and dividing with the entered numerical values in accordance with the selected function keys. Each key 0 to % X, +, ... is connected to an AND gate 4Ge, the other input of which is connected to one of the clock signals Ti-Ti ₆ discussed above. AUe outputs of those AND gates AGb that are assigned to the numeric keys are routed to a common line, and all outputs of the AND gates assigned to the function keys are routed to another common line. In this way, when one of the keys is selected, the selected key signal from the keyboard KB only forwarded during a corresponding assigned digit clock signal

The structure of the keyboard is described below with reference to FIGS. 2 described in more detail. Each individual key switch KS has an end part A, which is connected to one of the digit clock outputs Ti - T16, and another end part B, which is connected to a common line Do. The end parts B which are connected together are also connected via 'eiri ^ n' resistor R ' connected to a negative voltage source E. The circuit is designed so that the number keys 0 to 9, the received-Ziffernta' itsignale-tumor 7s in an order inverse to the occurrence of a Zifferntakt- _S; gnoif ₀ | ge is. since the reference time T _{) b} £ »is used wildly to mark the ore-up time. For example, the digit key 1, which causes the entry of the digit »1«, receives the .. digit clock signal Tu. And the digit key 2 receives the digit clock signal Ti ₃ . In a similar way, the number key 9 receives the number clock signal T ₅ . It will then be seen that when the numeric key is selected, the time interval elapsing between the key signal and the reference time corresponds to the numerical value indicated by the key

According to FIG. 1 , the keys provided in the keyboard KB have been subdivided into a numeric key division TK and a function key division FK . Both the numeric key and the function key department are connected to an OR gate OGi, the output mn of which is connected to a first RS-type flip-flop Qi in the integrated circuit IC . It should be pointed out that such a coupling between the keyboard KB and the integrated circuit IC is effected with only two connecting lines. The flip-flop Qi also receives the human digit _{clock signal Ti 6 as a} clear input signal and can be switched synchronously with the combination of Zritf.ignalen £ 4 Φι. It is therefore ζ. ό. brought into its set state at time T ₇ u Φ \ and then brought back to its released state at time Ti ₆ U Φι and thus remains in its set state for nine digit periods, which corresponds to digit key 7, as will become clear later. The purpose of the flip-flop ρ Qi is to help identify the various key signals and, for this purpose, carries its output signal to the three flip-flops Q ₂ . Qi and PFzu. These flip-flops Q ₂ . Q3 and PF are of the delay type.

The flip-flop Qi, which receives the set output signal of the flip-flop Qi as an input signal, has a delay. by which its set and delete operations are delayed by one digit period, and is used to control the input of the selected key signals in a main register X for storage. The flip-flop Q ₂ is set in consideration of the set state of Qi in the event dei clock signal combination T ₁₆ U Φχ and is only deleted after the disappearance of the key signal Due to this operation, the flip-flop Qi coming from the keyboard KB key signal is nui once in the register X input In general, the amount of time the operator depresses the same key is in a range of a few seconds to a few microseconds, while the calculating apparatus does the processing at a high speed in a few microseconds, that is, one word time. Under these circumstances, on the other hand, provision must be made that a reading-in operation of the same key signal is repeated.

The flip-flop PF is set when the clock signal · ^ combination T _{! 6} u Φι occurs, if the condition Qi Q ₂ occurs, with the result that the arithmetic operation signal Per is generated.

An AND element AG} receives the output signal 7 $ i via an inverter / and the output signal Qj and 'is used to distinguish the selected' key from the key selected by means of gate switching operations. The time interval Qj Qi, at which the AND gate AGj, is open, corresponds to the numerical value with which the selected digit key

In the embodiment of FIG. i will be

these time differences, which are related to the differentiation of the selected key from the unselected keys, converted into a series of binary-coded signals (4 bits in Fig. 1), with the help of an adder FA and an input buffer register XF, which consists of four Flip-flops XFi-XF * consists. The AND element AG3 receives the bit clock signal h as a third input signal, which is fed to a first input of the adder FA_nur datin when the condition Qi Qi is met. The. The adder FA also receives the binary-coded output signals from the buffer register XF at its second input a. In this way, the adder FA performs adding operations, the number of bit clock signals fi passed by the gate being counted so that the key signal coming over the common line is converted into a series of binary-coded signals of an encryption which corresponds to the selected key. In the example above, the AND gate AGj. if the digit key 7 is selected while the nine digit period ^ n is opened. In practice, the addition that is to be carried out during the two digit clock periods outside the nine digit periods is suppressed. In other words, the previous content of the buffer register XF must be discarded during the first digit clock penode, and the period of the last digit _{clock signal Ti 6} represents a period of time for the input of the numerical value "0". As a result, the period of time corresponds to the digit intervals allowed through the gate minus two digit intervals exactly the numerical value selected with the help of the numeric key.

The digit key signals carried on a common line are also fed via an AND element AG \ to a decision flip-flop FN of the A-S type, which brings about a decision as to whether the selected key signal from a digit key or a function key is valid. If the flip-flop FN is set, the input key signal is processed as numeric key information. The decision flip-flop FN receives the output signal of the AND element AGt and the clock signals PTh, Ta. And ran em output signal FNP. indicating that the input key signal is a numeric key signal.

The contents of the buffer register XF circulate along a circular path that contains an AND element AG * and the adder FA during the period in which the repeated addition of the bit clock signal U takes place and during the period in which the contents of the buffer register XF to the main register X are transferred. An AND gate AG ₅ between the registers XF and X receives the various signals FNP. P and Τ _Λ . Due to the distribution effect of the AND element AG, the binary-coded key signals assigned to a numeric key are fed to the storage register X and the function key signals are transmitted from the buffer register XF in parallel to a computer control unit CD , which status flip-flops FF _x . FF ₂ ssw. Safsfeisi. asd without circulation through the buffer register XF.

As discussed above, both the numeric key information and the function key information are converted into binary-coded signal series. The numeric key information indicates in its binary code directly the numerical value of the selected numeric key in order to avoid the need for a special coding circuit; however, assigned to a function key information Einärzeichen does not face the selected function, and for this reason FFI must be between the buffer register XF and Zustandsflipflop FFI, one! encoder designed for function information werdea
The procedure for entering numeric key information will be described more clearly with reference to FIGS. 4A and 4B; 4A shows the procedure for entering the information assigned to the numeric keypad 7

¹ -Weim.die. Digit key 7f is operated, the key signal is passed through the AND gate AGe during; the duration of the digit clock signal Ti , so that the fiipflop Q, at time T ₇ U Φ. is set

iS Thereafter, the flip-flop Qt is deleted at the time T _ib. If the key signal a, from the button 7 is still present, the flip-flop <? _t set again at the time Ti U Φι. While the digit clock signal Ti is fed to the flip-flop Qt , the flip-flop Qi is in his

ίο deleted state, and the AND gate AGi is activated for the purpose of controlling the flip-flop FN at the time Tr Φι. The initial signa! FNP participates in the transmission of the key information either to register X or to the computer control unit CD

The output signal of the flip-flop Qt sets the flip-flop Qi during the next digit rate 7βί «Φι. After the 'setting of the flip-flop Q \ , the clock pulses Φι are fed to the shift register XF in order to set its shift operation in motion and thus introduce new information into this according to the selected key (condition Qi Q ₂ Tu, Φι).

During the four-bit clock periods prior to the setting of flip-flop Qi remains, however, the AND gate AGa in the locked state due to the condition Q ₃ Q ₂ with the result that the previous contents of the buffer register XF werdea completely erased At this time, the buffer register XF is ready for Recording of the selected key signal.

Then, when the output signal of the flip-flop Qi appears, the AND gate AG4 is opened so that the circulating loop for the buffer register XF is open. and the bit clock signal is fi to one input b of the adder due to the logical conditions Qi Q3 for the AND gate AG3 supplied, since the above-mentioned conditions during the period of t ₈ U Φ \ be maintained until 7i6 U Φι, a total of eight bit signals U are the AND gate AG3 is supplied to the adder FA during the time intervals Tg-Tie. Accordingly, the EP signals ti are repeated as adding input signals to the respective one

- The contents of the last register position XF \ (all zeros at the beginning) of the buffer register XF are added during the period T ₉ - Ti ₆ . However, as has already been mentioned with reference to the input of signals by means of the digit key 0, the shift operation of the buffer register XF is only not carried out during the period T ₁₆ in order to prevent the addition of the bit signal it. As a result, the addition is carried out seven times, and the resulting binary-coded signal Olli is introduced into the buffer register XF and stored there. After the flip-flops Q ₂ and PF have been set at the time Ti ₆ U Φι , the logical conditions for the AND gate AG _{3 are} not

«5 is fulfilled, and thus the bit clock signals are no longer passed to the adder FA .

After the output signal P from the flip-flop PF occurs , the buffer register XF continues its

To move memory contents according to the clock pulses Φ. The AND gate AG ₅ is also open so that the memory content 0111 of the buffer register XF is introduced into the lowest position of the register A 'in the clock phase Ti in order to complete the read-in operation. The input operation assigned to the next digit key is carried out in the usual manner in such a way that the key signal is inserted into the second digit position of the main register while performing a shift operation to the left.

4B illustrates the mode of operation when the number key 0 is pressed. When the number key 0 is pressed, the key signal is transmitted synchronously with the number clock signal Tu in order to set the flip-flop Q \ and FN at the time T \ * ί * Φι. During the next digit clock period, Qy Qi applies. and the buffer register XF is cleared, and then the flip-flop Q _{1 is set} at the time TW U Φ- . Since the flip-flop Qj is set at time 7 "i6 U Φι, the logic condition Qi Qi is only met during the one digit clock period TU μ. At this time, however, the clock pulses Φ are not fed to the buffer register XF, so that the content 0000 remains in it. The AND _{gate 4G 5} is used to transfer the content 0000 from the buffer register XF to the main register X.

In the case of pressing the function key X to cause a multiplication, the binary-coded signals 0010 are introduced into the buffer register XF in the same way. These signals 0010 set the status flip-flop FFi via a suitable decoding circuit, which results in the routine for carrying out the multiplication. If the function key = is then pressed, the binary-coded signals 0100 are introduced in parallel into the buffer register XF and then transferred to the arithmetic control unit CD . The computing device then begins the multiplication.

The above example has a key input circuit for a computer. the sixteen digits Ti - synchronized T16: the same prin- 4P zip but is also applicable to a portable computing device, are used in which only nine digits for performing the various calculations. F i g. 5 shows a further embodiment. in which nine digit signals Tj - T9 are used, while the main register X has a capacity of eighteen digits the register X to distinguish. For example, a combination LTi shows the first digit and a combination LT \ the tenth digit.

The same reference numerals are used in FIG. 5 as in FIG. 1. The circuit of FIG. 5 will to the person skilled in the art on the basis of the preceding explanation of the circuit of FIG. 1 out of the Figure to be understandable. In this case, the iräeBinder Füirsssigsabteikisg aageord- * ° net

When the number key 6 is pressed manually as shown in FIG. 6, the key signal KN is supplied to the integrated circuit arrangement IC at the time LTj in order to set the flip-flop Q * at the time LT3 U Φι . ⁶ S At the same time das_Flipflop FN is set when the logic state Qz occurs in order to generate the signal FNP τα , which indicates that the selected key signal represents numerical information.

After a number period has elapsed, the set signal of the flip-flop Q * sets the flip-flop <?, at the time LTi ί * Φ \. When the flip-flop Q * is in the set state, the buffer register XF shifts its memory contents, but the previous contents are discarded due to the closed state of the AND gate AG * in the circulation path (logical condition Q * Qi Φ). Thereafter, the conditions | <? 4 + <? I) © 2 are established for the AND element AG ₃ , so that the adder FA can receive the bit clock signal u through the AND element AGj ; ibis the flip-flop Q ₁ at time LT * U Φι is set. In this way, the AND element AG ₃ supplies the adder FA with a total of six signals during the period from LT * to LT <>. It should be noted, however, that the bit clock signal tu which is supplied at the time LT * Λ is not arithmetically added to the lowest bit position XF \ of the buffer register, which has the consequence. that the most significant bit position XFiden stores the numerical value "1" because the AND element AG _t is blocked due to the conditions Q * Qi . During the next periods before the occurrence of the bit clock signal fi at the time LT ₅ fi, the AND element AG ₄ remains in locked state, and thus the storage contents of the buffer register XF are shifted and become? u 0001. In other words, under the conditions Q * Q \, new information is entered into the register XF instead of the previous contents. Since the addition of the bit clock signal / i is carried out repeatedly, namely six times during the digit clock intervals Ti - T). the binary-coded signals 0110 are introduced into the buffer register XF The memory contents 0Π0 are transferred from the buffer register XF to the main register X at the time LT ₉ t * Φι.

F i g. 6B illustrates the operation when the key signal 9 is introduced and FIG. 6C when the key signal 0 is introduced. In the case of FIG. 6C, the flip-flop Q * is set at the time LT ₇ u Φι , which means that the buffer register XF stores the binary-coded signals 0010. To use the key signi ·! To distinguish 0 from the key signal 2, the parallel output signals of the buffer register XF are inspected in order to examine whether the parallel output signals are 0010, and in the affirmative case the output signal XFP will appear. At the same time, the flip-flop FN supplies the signal FNPi. to stop the input of the clock signal Φι in the register XF . The signal FNPI not open the AND gate AGs, and thus the shift operation of the register XFnicht runs Accordingly, the binary-coded signal is "introduced in the register X 0000

The complete arrangement of the portable computer according to FIG. 7 with the key coupling device from FIG. 5 contains the keyboard KB, the large integrated circuit LSI, the memory unit, the arithmetic unit, the arithmetic control unit, etc. and solid-state playback devices Di-A - ζ. Β. Light-emitting diodes - contains In this arithmetic unit, which has a display device, the individual digit clock signals Tt-Tg are fed out separately from the large integrated circuit LSI via appropriate terminals in order to control the time division multiplex operation of the display device. In addition to the key signal coupling, the time difference associated with the generation of each key signal can be obtained from such terminals without the expense of terminals

709 629/185

to increase. In the drawings, symbols TRx-TRs denote time division transistors, and symbol 5I> denotes a segment drive circuit.

From the above discussion of the exemplary embodiments it is clear that, instead of the adder FA, a subtraction or a counting circuit could be used in such a way that the key signals supplied synchronously with the corresponding digit clock signals are converted into a series of binary-coded signals. In the case of a counter, it would unconditionally and repeatedly perform counting operations, regardless of the type of key signal, and only when the key signal appears would the respective contents of the counter be converted into a series of binary-coded signals.

In addition 7 sheets of drawings

* S «i-

Claims (5)

Patent claims: 1. Input circuit arrangement by means of a keyboard for a table or pocket calculator built up from integrated circuits, in which the keys of the keypad formed by function key switches and numeric key switches are combined into a group and for processing in the calculating machine the keys are each grouped by means of group distinctions Pair of corresponding keys of the two groups characterizing clock signals are identified, characterized in that the key switches with the Taktsipi ■■ len (Γι, ...) controlled AND gates (AGb) are v-bunuen and the combined signals d with the Key switches connected AND each of the one group control a decision flip-flop (FN) , and that the decision flip-flop (FN) signals identifying this key group and the UiN D elements (AGe) the pair of keys both addressed by the triggered clock signals (Γι, ...) Group identifying signals to d he supply the data processing means of the calculating machine. 2. Circuit arrangement according to claim 1, characterized in that a counting circuit (FA, XF), which is switched on when a clock signal is triggered by an actuated button, and one of the clock signals (T ₉ ) and possibly an additional clock signal ( T ^) controlled reference generator (flip-flop Q ₂ ) are provided, which supplies the counting circuit (FA ,, XF) Jn reference signal with a fixed clock phase (LT ₉ U Φ or Τίβ U Φι) as a stop signal. 3. A circuit arrangement according to claim 2, characterized in that the counting circuit comprises an adder (FA) which adds the received clock signals to a location of a connected to the adder (FA) buffer register (XF) 4. Circuit arrangement according to one of claims 2-3, characterized in that the integrated circuit (IQ one of the counting circuit (FA, XF) upstream gate circuit (AGj) aui-vsftist, which is during the time interval between the receipt of the key signal and the reference signal in open is a state 5. Circuit arrangement according to claim 1, characterized in that a main register (X) is connected to the counting circuit (FA. XF) in order to accept numerical information from the counting circuit (FA. XF) when it is present.