DE2241349C3 - Circuit arrangement for generating pulses of the same length, offset by 180 degrees - Google Patents

Description

It is known that in the case of foreign-controlled converters, the control pulses are saturation-controlled Generate auxiliary converter. However, this solution has the disadvantage that the oscillation frequency is highly dependent of input voltage fluctuations, component tolerances and the ambient temperature. Since also In the case of transistors, the scraping takes place more slowly than that due to their storage effect Switching on, a short circuit occurs in the primary load circuit with each switching process, the corresponding the remaining short-circuit resistance causes a current increase in the collector-emitter paths of the switching transistors and in the winding halves of the power transformer beyond the normal load current to Consequence.

Another disadvantage of saturation-controlled converters is that the gap required between the individual pulses in order to avoid short circuits due to the storage times of the transistors is caused by additional effort, e.g. B. di / dt throttles must be obtained.

The invention is based on the task of overcoming the disadvantages mentioned with simple ones Means a circuit arrangement for generating two pulses of the same length, offset by 180 ° within a period with infinitely variable setting, especially for controlling inverters and converters to create. This object is achieved in that a clock is provided which simultaneously controls a bistable and a monostable multivibrator and that the output of the monostable flip-flop controls a further bistable flip-flop and that also the outputs of the bistable Flip-flops are combined via a summing circuit, the output of which supplies the offset pulses.

In this way a constant voltage

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60 fluctuations, ambient temperature and component tolerances largely independent clock frequency gained. When the circuit arrangement according to the invention is used for converters, a gap corresponding to the storage time of the transistors can be selected and the output voltage can be set continuously.

According to a development of the invention, the summing circuit consists of logic elements, for. B. NAND members. This solution has the advantage that a corresponding circuit arrangement can be fully integrated is, but can also be produced using conventional technology.

If, instead of unipolar, bipolar pulses are required, as is particularly the case when controlling Transistors is the case, the summing circuit can be constructed from transformers.

A saving of components is achieved by following the monostable multivibrator bistable multivibrator dispensed with and the outputs of the first-mentioned bistable multivibrator and the monostable Flip-flop via link elements, z. B. NAND elements summarized.

The invention is explained with reference to the figures. It shows

F i g. 1 shows a basic circuit arrangement according to the invention,

F i g. 2 a modification according to FIG. 1 with transformers,

F i g. 3 is a timing diagram for FIG. 1,

F i g. 4 shows another basic circuit arrangement and

F i g. 5 the corresponding pulse diagram.

In the figures, A is a self-oscillating clock, e.g. B. an astable flip-flop, referred to. Bistable multivibrators have the reference symbols BK, BK 1 and BK 2. In addition, a monostable multivibrator M is used. Gating elements Gi, G2 or transformers Oi, Ü2 , for example, serve as the summing circuit. With regard to the pulse diagram and the inputs, the outputs of the bistable multivibrators are the ones shown in FIG. 2 shown summing circuit with transformers specially marked. Pi and P2 identify the two equally long pulses offset by 180 °.

According to the representation in the pulse diagrams, the exemplary embodiments are based on a circuit arrangement which, on the negative edge of the clock A, controls the bistable multivibrator BK 1 and releases the monostable multivibrator Maus. After the time i \ i, which corresponds to the output pulse duration of the monostable multivibrator, has elapsed, the bistable multivibrator BK 2 is activated according to the circuit arrangement shown in FIG. By combining the corresponding outputs 1/1 and 2/1 of the bistable multivibrators to the logic element G 1 and the outputs 1/2 and 2/2 to the logic element G2 , two pulses Pi of the same length, offset by 180 °, are generated within a period T2 , P2 won. The duration of these pulses corresponds to the duration Ti of the clock A minus the output pulse duration of the monostable multivibrator M.

The combination of the pulses according to the bistable multivibrator shown in FIG. I can take place not only via logic elements but, as shown in FIG. 2, also via transformers Oi, Ü2 . The corresponding connections are identified by the same reference symbols. While here

Circuit arrangement according to FIG. 1 unipolar pulses supplies, gives the circuit arrangement according to FIG. 2 bipolar impulses.

The basic circuit arrangement according to FIG. 4 and thus also the pulse diagram differ from those in FIG. 1 and 3 only due to the lack of the second bistable multivibrator BK 2.

For this purpose 2 sheets of drawings

Claims (4)

Patent claims: 1. Circuit arrangement for generating 2 pulses of equal length, offset by 180 ° within a period with stepless setting, in particular for controlling inverters and converters, characterized in that a clock generator (A) is provided which simultaneously has a bistable ( BK 1) and a monostable multivibrator (M) controls and that the output of the monostable multivibrator controls another bistable multivibrator (BK2) and that the outputs of the bistable multivibrators are combined via a summing circuit (G 1, G 2), the output of which the provides offset pulses (Pi, PT) 2. Circuit arrangement according to claim 1, characterized in that the summing circuit of logic elements (G 1, G 2), for. B. NAND members. 3. Circuit arrangement according to claim!, Characterized in that the summing circuit transformers (Ü 1, Ü2) are provided. 4. Circuit arrangement according to claim 1, characterized in that the outputs of the bistable multivibrator (BK) and the monostable multivibrator (M) are combined via logic elements (Gi, G2), for example NAND elements (F i g. 4). 30th