DE2237615A1 - TELEVISION RECEIVER WITH COMPUTING FUNCTION - Google Patents

Description

PAlKNl LAWYERS

dipping. H. LEINWEBER dipping. H. ZIMMERMANN DIPL..ING. A. Gf. ν. WEN € ERSKY

δ Mifaeheii 2, RosersSat 7, 2nd ed.

ToL-Acir. lelnpaf Munich ΟΙοίοη (horny) 2603939

Postscheidc-Konio: Munich 2204S

the31. July 1972

Unoor sign

Z / Va / Sd / POS-28574

MATSUSHITA ELECTRIC INDUSTRIAL CO. , LTD «,

Osaka / Japan. ■.

TV receiver with computing function

The invention relates to a television receiver which can display a calculation process on its picture tube in a large number of γοη rows ₉ which is carried out in a computing section belonging to the television receiver, ie in an electronic desktop computer (hereinafter referred to as ETC - electronic table calculator for the sake of brevity) .

With the ETC currently on the market, the calculated Result using fluorescent tubes, light-emitting diodes or luminous liquid crystal cells only in a single row being represented. With such an ETC it is therefore difficult to represent the calculation process »

It is therefore an object of the invention to carry out the calculation to reproduce a so-called multi-row display.

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Another object of the invention is to provide a simple data conversion device for representing the operation to create on a picture tube without combining the timer system of the ETC with that of the picture system.

Yet another object of the invention is to provide an apparatus for inserting a line between the lines to be processed To create numbers and the calculated result in the presentation in order to make the cooking process easier to understand.

It is also an object of the invention to provide a device in which appearing to the left of the decimal point Number each after three digits to create a space in order to read off the result in the same way as to facilitate three digits for numbers with commas nacii.

Another object of the invention is to provide a color control device for displaying the from Memory originating numbers in different colors than those of the other numbers in the Kechnung to make the representation clearer close.

In addition, it is an object of the invention to provide a television receiver to create, in which the television program and the kitchen process are displayed simultaneously on the picture tube.

Finally, it is the object of the invention to create a television receiver with a kitchen function in which the storage value is in the top row, the first row size, for example a summand, minuend, huitiplikand or dividend in the second row, the operator or the row, and the second xiochen size, for a summand, subtrahend, liiiltipliLatoi ¹ or divisor in the third row and the unequal iiesuiUit in the fourth row. - ί -

3 0 9 8 0 7/1212 UfO ORIGINAL

Further details, advantages and features of the invention can be found in the following description. On the drawing ^! the invention is illustrated by way of example, namely show

1 shows a block diagram of a television receiver with Iiechenfunktion according to the invention,

Fig. 2 is a block diagram of a data converter circuit;

3 comparative representations of the content. an operator register and the content displayed on the picture tube,

Fig. 4 is a block diagram of an image control circuit, Fig. 5 is a timing diagram of a line display circuit, 6 shows a JJ block circuit of a position control circuit,

FIG. 7 is a timing diagram for that shown in FIG Position control circuit,

Fig. 8 timing diagram of a character generator circuit and a parallel row register and the pattern of a number,

9 is a block diagram of a color control circuit;

10 shows the representation of the numbers required for a calculation on the picture tube and

Fi _u . 11 the step-by-step change in the display according to the progress of the calculation.

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Fig. 1 shows a designated by a dashed line _:

neten ETC, which has a control panel or input unit 1, a! Input control circuit 2, an arithmetic control circuit 3 and an operator control register 4. A data converter circuit 5 stores the content of the operator register 4 in time correspondence: with the ETC and outputs the data as a function of the synchronous signal of the television receiver for display on the picture tube j A character generator circuit 6 converts the outputs 36, 37t, 38; and 39 of the data converter circuit 5 into address signals, signals 31, 32 and 33 into a signal for selecting a row in which ^: a particular character is to be displayed, and signals, 34 and 35 from the input unit 1 of the ETC into address signals for operators and supplies an output signal 43 · An image control circuit 8 supplies position control signals 26, 27, 28 and 29 for the data converter circuit 5 and a color control circuit 9 correctly arranging the data on the picture tube in accordance with horizontal and vertical synchronizing signals 46 and 47, respectively and a stroke signal 42 is supplied to the color control circuit 9. A part 79 of an ordinary television receiver is denoted by a dashed line and comprises an antenna 56, a tuner 10, a video IF-Ver; stronger 11, a video detector 12, a first video amplifier * 13, a synchronous circuit 14 for supplying the horizontal and vertical synchronous signals 46 and 47 for the image control circuit 8,

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a color synchronizing circuit 15, a demodulator 16, a matrix circuit 17 and a picture tube 18, the bot, blue and green chrominance signals 48, 49 and 50, respectively, are fed from the matrix circuit 17. These chrominance signals can be used together with the Outputs 44 and 45 of the color control circuit 9 generate a color image on the picture tube 18, »

The circuit shown in Fig. 1 operates as follows. A number signal ton of the input unit 1 of the ETC 78 is transmitted through the input control circuit 2 and the arithmetic control circuit 3 processed, stored in the operator register 4, given as a signal 19 to the data converter circuit 5, one after the other from the lowest point downward in that in the data converter circuit 5 Register stored (as described in detail later), after the end of the storage, read out from the register as a function of the timer signal 30, then further through the character generation circuit 6, the Parallel-Pure ™ register 7, the coloring control circuit 9 and the matrix circuit 17 guided and finally shown on the picture tube 18. On the other hand, the operator is by directly supplying the signals and 35 from the input unit 1 to the character generation circuit 6. A second number store stored in register 7 Control signal is also shown in the same way as described above on the picture tube 18, the calculation process as far as with the first calculation variable as well as the operator and the second calculation variable, * the respectively -in the second resp. third row appear, is shown. If then the button for the equal sign in the input unit 1 is depressed is, the calculated result is fed into the register 7 and at the same time the bar signal 25 for the Image control circuit 8 supplied so that the stroke signal 42 to the

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Color control circuit 9 is given. Thus, the calculated quantities, the operator, the line and the calculated result are on the picture tube 18 shown. When a series of calculations is continuously performed, this display method becomes repeated.

Fig. 2 shows in detail the structure of the data converter circuit 5. This data converter circuit 5 receives the information from the ETC 78, which is continuously derived from the lowest position upwards, and writes it down from the highest position at the bottom of the memory pad, so that the desired information is displayed correctly on the picture tube 18. FIG. 2 shows a register selection circuit 57, a storage circuit 58 which consists of Registers SR1, SR2, SR3 and Sfi4, each for 4 χ η bits are suitable (if each row consists of η digits), and a register 59 for converting a series-to-parallel a part of the data corresponding to a digit (4 bits), a pulse counter 63 with a division ratio η: 1, a switching control circuit 64 for switching between writing and reading of the memory circuit 58, a timer drive circuit 60, NAIiD gate circuits NA1 .... NA9, a pulse counter 61 with a division ratio 4: 1 and a pulse counter 62 with division ratio (n-1): 1. The information signal 19 from the ETC 78 is through Control signals 20 and 21 and a busy signal 22 are controlled and entered into the registers of the memory circuit 58 in the order fed into the calculation. The Zeitgeba * signal given to the storage circuit 58 is that received by the NAND gate circuit NA1 NAND signal of the output of the switching control circuit 64 and the timer pulse signal 23 from the ETC 78. The timer pulse signal 23 is also sent to the pulse counter 62 with Division ratio (n-1): 1 rounded pulse counter 61 with divisional

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ratio 4: 1 given. Therefore, the MED gate NA1 opened every time 4 (n-1) timer pulses of signal 23 have been counted so that four timer pulses are given to the timer drive circuit 60. Be that way Time signals $ .. and φ ^ generated and a piece of information, which corresponds to a single position in the operator register 4 of the ETG 78, is written one after the other into the registers SR1 to SR4 of the memory circuit 58. As the information body to place in the register in a period of (n-1) places, the information from the top Place down to be saved. The NAND gate circuit; NA4 is opened by the output of the switching control circuit when the pulse counter counts with the division ratio η: In time pulses has, whereupon the NAID gatekeeping NAt is closed. When the HMD gate circuit M4 is open, the timing ' cross signals φ, and ^ ^ es storage circuit 58 with a timer pulse signal 30 synchronized for the television picture display.

Fig. 3 shows how the content of the operator register 4 of the ETC 78 is displayed on the picture tube of a television receiver. In this figure, (a) denotes the content of the operator register 4 of the ETC 78, (b) the content of the register SR1 of the memory circuit 58 and (c) the information displayed on the picture tube, the characters A1., ... An each denoting the Counting ; starting from the lowest position and ending at the top ^{: represent} position. If, for example, as shown in the lower part of FIG. 3, a number 123 is entered in the ETG 78; is the content of the operator register 4 of the ETC 78 "00 .... ..0123" ·, as shown in (a) ¹ . Correspondingly, the content of the ί location register SR1 of the memory circuit 58 is "3210 ....... 00", as shown at (b) ¹ , and the image display on the picture tube is - 8 -

3 09 807/12 12

hence "123" as illustrated ^{in (c) 1.} ■

Fig. 4 shows an example of the image control circuit 8 in j Fig. 1 in detail. According to this figure, an 8-bit counter 65 counts the horizontal synchronizing signal 46 and can determine the horizontal; Position of the representation on the picture tube by processing the respective outputs with appropriate logic circuits determine. The signals 26, 27, 28 and 29 determine the intervals of the display in this 4-row display. A signal 80 determines the position of the displayed on the picture tube Dash and a signal 81 serves as a timing signal for a Heihenwählerkreis 66, which determines the none in which certain Characters are to be arranged on the picture tube. A decimal point determines the euig circle 67 determines the position of the decimal point in the ETG 78 by means of a signal 24 and supplies the decimal point signal 41 for the shift register 7. A gate oscillator 68 is an oscillator that only works during the duration of the horizontal sync signal s is on, and the timer pulses from this oscillator determine the horizontal position of the image. A distance circle 69 determines a distance after every three digits to the left of the decimal point of the numbers shown. The details of the distance circle 69 will be described later. An 8-bit counter 70 counts by dividing a horizontal sweep period (1 II) timer pulses 75 obtained by eight bits of one digit. Each after eight bits of the timer pulses are counted 75 a load signal 40 is emitted, which is used to transfer the information one after the other, digit by digit, into the shift register 7 to be registered. A flip-flop circuit 72 determines the area of the representation of the stroke. There are also NAND circuits IiAI0 bin 1JA20, AND junctions AN1 to AN4 and inverter IjJ 1 to liJiO provided.

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Fig. 5 shows the timing of the various in the I.

Line-drawing circle appearing signals, where (a) the j Vertical synchronizer 47 of the television system, (b) the horizontal

Synchronization signal 46, (c) the output of the AND circuit AI4, (et) |

the output of the NAID circuit NA19, (e) the output of the IAID-J

Circuit IA20, (f) the output of the flip-flop circuit 72 and:

(g) the output of the IAID circuit NAt8, namely the dash i signal 42 ".

Fig. 6 shows in detail the structure of the distance circle .. 69, namely a pulse counter 76 with division ratio 3! 1, ; a delay circuit 77, a laid-circuit Ia21, an ^And circuit AN5, an inverter 1115, and for the 8-bit ^Zäh-: ler 70 specific timing signal 73, a clear signal 74, the one bit each representative of load signal 40 and a Signal 75 obtained by j masking the timer signal 73 every three digits. The distance circuit 69 operates as follows. ^: The pulse counter 76 with dividing ratio 3 ί 1 supplies an off every time it has counted three pulses of the load signal 40 ^; output signal to the delay circuit 77, the NAND circuit IA21: generates a pulse whose duration is equal to the delay time characteristic of the delay circuit 77, and the AND circuit AN5 masks the timer signal during the delay time. The temporal relationships between these above-mentioned signals are shown in Fig. 7, in which (a) the load signal 40, Cb) the output of the pulse counter 76 with division ratio 3: 1, (c) the output of the inverter 1115, (d) the Output of AND circuit Αίί5 and (e) represent a timer signal controlled as a function of output (d).

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Fig. 8 shows the timing chart of the input signals to the character generating circuit 6 and the parallel-to-row conversion register 7, wherein (a) one of the numerical information of the data converter circuit 5 carrying outputs 36, 37, 38 and 39, (b) which the pattern of a from the character generator circuit 6 in. Dependency of the output signals 36, 37ι 38 and 39 supplied number resulting output waveform, (c) the load signal 40, (d) the timer signal 30 and (e) denote a number pattern (5 x 7). For example, if a row has been determined as "001" and the input information for the character generator circuit 6 is "1", the outputs 51, 52, 53, 54 and 55 are 0, 0, 0, 1 or O. The position of the signals representing the numerical pattern on these relative timing signal 30 is indicated by the dashed lines between (d) and (e).

FIG. 9 shows an example of the color control circuit 9 in FIG. 1, which comprises NAND circuits NA22 to NA25 and inverters IN1 1 to IN14. A signal 43 as a point signal representing a number pattern is given to both the NAND circuit HA22 and the NAND circuit NA24. If the input information of the signal 43 is equal to the memory value, the MAMD circuit NA22 is opened by the signal 29. If the output of the NAND circuit NA22 is applied to the hot output circuit of the matrix circuit 17, for example, the memory value shown in the top row on the picture tube lights up in red. On the other hand, if the signal is different from the stored value, it passes through the NAiiD circuit NA24 and is fed to the NAriD circuit NA25 which forms the logical sum of the signal 43 and the bar signal. If the output 44, for example, the GrünauDgarig circuit of the matrix circuit 7 is set, the numbers that indicate the process will light up in green. -II-

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In Fig. 10, representation (a) shows the position of the the information displayed on the picture tube, with the stored value in the top or first row and the calculated value in the second Row, the operator and the calculated variable are given in the third row and the calculated result in the fourth row.

The illustration (b) shows an example of an actual one Calculation on the picture tube of a television receiver.

Fig. 11 shows as an example the individual steps of the entire process of an actual calculation on the picture tube of a television receiver, wherein (i) the step of Representing the calculation variable "12", (ii) the step of adding the operator "x", (iii) the step of adding the Bottom size "4", (iv) the step of pressing the button down for the equal sign, (v) the step of storing the calculated result "48" in the memory circuit and (vi), (vii), (viii) and (ix) the steps of performing the calculation "24-48 =". If the number of the calculated result or the stored value is a negative value, the algebraic one stands Sign "-" in front of it.

As described above, the invention provides various advantages, such as the ability to check a Calculation process during the calculation, the display of the contents of the memory register from moment to moment, the clarification of the calculation process and the calculated result through use of multicolored representations, the representation of a dash D2W. of lines in the arithmetic process, the provision of spaces between the third and fourth digit as well as the representation There was information on the picture tube of Fernoriipfänder in 'overlay with the television program.

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Claims (9)

- 12 patent claims: 1. TV receiver with Eechenfunktion, characterized by a computing device (3) for performing a computing process on the basis of input data, by a memory device (5, 58) for storing the sequence of the by the computing device performed calculation process, by a device (6) for reading the content of the storage device and converting this content into character signals, by means (10-16) for receiving television signals and demodulating the Video signal and through a picture tube (18) for displaying images by receiving the character signals with or without video signals superimposed on them. 2. Television receiver according to claim 1, characterized in that a device (8) is further provided which a first sync signal received by the computing device (3) and a second sync signal associated with the television signal receives and one based on either the first sync signal in the case of writing or the second sync signal in the case of reading out the drive pulse received to the memory device (5). 3. Television receiver according to claim 2, characterized in that a register (58) with 4 χ η as the memory device bits is provided, where η denotes the number of digits, and also a counter (61, 62, 63) for supplying a timer pulse every time it has counted 4x (n-1) pulses of the first sync signal, and means (60) for generating! of drive pulses as a function of these timer pulses, the register, the counter and the device for generating /mir.iob, '3 pulses together form the drive device, 30 9 807/171? - 13 - BATH ORIGINAL and that the calculated information obtained by the arithmetic unit (3), which begins at the lowest point, is included with ^; starting with the top position in the register. 4. Television receiver according to claim 1, characterized in that a device (65 or 70) for counting Pulses of the horizontal sync signal belonging to the television signal is provided and that the numbers representing the calculation process by reading out the stored information of the memory means, when the counted value reaches a predetermined value, with the one left blank between them are arranged at a suitable distance on the picture tube (18). 5. Television receiver according to claim 3, characterized in that that the memory device (58) consists of at least three registers (SR1, SR2, SB3 ...) each with 4 χ η bits, those for storing the calculation quantities and the advised Result due to the optionally the individual registers respectively supplied computing information are suitable, and that the arithmetic process can be represented by reading the contents of these registers on the picture tube (18). 6. Television receiver according to claim 5, characterized by means (65) for counting the pulses of the a horizontal sync signal associated with a television signal and by means (NA18) for generating a bar signal; (42), when the counted value reaches a predetermined value ^ that is the representation of a line between the calculation quantities, and the calculated result on the picture tube (18). - 14 309807/1212 7. Television receiver according to claim 2, characterized in that to create spaces between each the third and fourth digits of each number displayed on the picture tube (18) a device (76) for counting each three digits of a number from bottom to top when reading the number from the memory device and one device (AIi5) to hide a to the memory device for the purpose of Reading are provided depending on the output of the counter given drive pulse. 8. television receiver according to claim 1, characterized dadurca, that the picture tube (18) is a color picture tube and that furthermore a device (8, 9) for the representation of the calculation process is provided in several colors and in a plurality of rows on the color picture tube. 9. Television receiver according to claim 5, characterized in that for storing the memory value, the first arithmetic variable, of the operator with the second fiechen size and the calculated result four registers (SR1, SR2, SR3, SR4) are provided and that the stored information for display in four rows in the order mentioned on the picture tube (18) can be read. 309807/1? 12 Lee side