DE2252556A1 - DEVICE FOR GENERATING A VIDEO SIGNAL FOR INPUT INTO A SCANNED VIEWER - Google Patents

Description

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ο i-raiMiiiii a. M. 1
Park street 13

GEC-ELLIOTT AUTOMATION LIMITED, Borehamwood, Hertfordshire,

England

Apparatus for generating a video signal for input into a raster-scanned display device

The invention relates to a device for generating a video signal for input into a raster-scanned display device for the purpose of displaying at least one graphic symbol.

A raster-scanned viewing device is, for example, a cathode ray tube, which deflects according to a television raster or is scanned. However, other types of raster-scanned display devices are also known. As examples can called light-emitting diodes, which are electronically scanned, or a screen scanned by a laser beam,

The invention is based on the object of a novel device for generating video signals for input into a raster-scanned display device.

The device described at the beginning is characterized according to the invention by an input memory for holding or

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Storing digitally represented input parameters of at least one graphic symbol, a digital data processing device to process these parameters for the purpose of generating a digitally represented output signal that corresponds to the Identifies video signal, and means for converting the digitally represented output signal into the video signal.

The graphic symbols can be line symbols (for example straight or curved lines) or symbols trade in a considerable area of land.

Line symbols are used, for example, to represent alphanumeric Characters used. Line symbols can also be used to represent other information, for example the flight path of an aircraft or the position of the horizon in relation to the position of an aircraft.

The digital data processing device preferably contains a video memory which is designed such that it contains information holds or stores, which identify a part of the video signal, the at least one line deflection of the raster corresponds to calculating means for performing calculations on the parameters with respect to each successive one Line deflection of the grid for the purpose of generating the information for loading the video memory and a readout device for Reading out the information from the video memory upon completion of the calculations relating to a line deflection for the purpose of generation that part of the digitally represented output signal which corresponds to the line deflection.

The input memory is expediently designed in such a way that it stores the parameters of a plurality of graphic symbols, and the computing device is set up in such a way that it carries out the calculations on the parameters of each of the graphic symbols in succession for each line deflection of the grid. In this way, according to the time division multiplex method, the computing device is based on the various symbols

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• - 3-

bole split in time. This is associated with savings in terms of equipment. _y

In a particular embodiment of the invention, the video memory is configured such that it stores the information that the portion of the video signal flags, corresponding to a single line scan of the raster, and the entire apparatus is set up in such ₉ that the computing device, the calculations with respect to a Performs line deflection during the return period that immediately precedes this line deflection.

In another particular embodiment of the invention, the video memory is designed to hold information stores that identifies that part of the video signal which corresponds to two line deflections of the raster, and the entire The device is set up in such a way that the arithmetic unit carries out the calculations with regard to a line deflection while the executes the immediately preceding line deflection identifying information is read from the video memory. This has the advantage that the Time is much longer. As a result, when the time division multiplex method is used, a larger number of graphic Symbols are processed.

In a preferred arrangement according to the invention contains the Data processing device a; device for storing a number defining the location of a portion of one of the symbols within a line deflection of the grid; and a device to carry out a predetermined algorithm, according to the parameters, to determine the number for a subsequent Bring line deflection of the grid to a suitable value.

The invention also comprises a display device arrangement with a raster-scanned display device and with a device designed according to the invention for generating a video signal for

Input into the display device,

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A viewing device arrangement with an exemplary embodiment of a device designed according to the invention is illustrated with reference to figures described. Show it:

1 shows a schematic block diagram of a display device arrangement,

2 is an enlarged schematic view of part of the image displayed by the arrangement;

3a and 3b when connected together accordingly 3c, a schematic block diagram of part of the display device arrangement,

Fig. Aa is a schematic illustration which explains in the manner in which a video signal is stored in the display device arrangement,

Fig. 4b is a graphic representation of part of the video signal according to Figs. 4a and

5 shows a schematic block diagram of a modified display device arrangement.

The display device arrangement shown in FIG. 1 contains a directly connected (on-line) digital computer 1 from the output of which digital data are fed to a vector generator 3 and a loop generator 4 via a connection 2. the Generators 3 and 4 generate corresponding video output signals, which are combined in a mixer 5 and used for brightness modulation Serving input of a cathode ray tube 6 are fed. The cathode ray tube 6 is supported by deflection circuits 7 controlled according to a television grid for distraction. Furthermore, the deflection circuits 7 lead to the vector generator 3 and the circle generator 4 to line and image synchronization signals.

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The raster pattern on the screen of the cathode ray tube 6 contains 625 lines with an aspect ratio of the picture area of 4: 3. Furthermore, the interlaced or field method is used for the raster pattern. Of the lines, 576 are for definition available in the vertical (Y) direction. The corresponding definition in the horizontal (X) direction includes approximately 700 video elements per line deflection. This corresponds to a Video frequency of 14 MHz.

Each picture frame can thus be thought of as being composed of 700 * 576 video elements, each with an aspect ratio of about 1: 1. In the following description, the unit length in the vertical direction becomes the distance between adjacent lines of the same field and below the unit length in the horizontal direction the width of one Video element understood. The vertical unit is therefore twice that of the horizontal unit.

The vector generator 3 is constructed in such a way that it generates a video signal which the cathode ray tube 6 on the screen causes one or more straight lines, here called vectors. In the embodiment described, can the vectors are only recorded on a limited vector writing area of the screen which is only 512 of comprises the 700 elements of each line deflection and only 512 lines in the vertical direction.

In Fig. 2, a small portion of a frame of the grid (both the even and the odd fields) is shown with, two vectors P and Q shown on a greatly enlarged scale. Each vector is constructed from a series of illuminated sections of the grid lines. The illuminated sections of a vector, for example the vector P, are in horizontal Direction by a fixed amount of 2 tan θ between one Line deflection and the next offset in the same field, where θ is the angle between the vector and the vertical and uses the horizontal spacer unit introduced above

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will. Furthermore, in the odd field or field, the illuminated portions are horizontal for a given vector Direction offset by a distance of tan θ with respect to the even field.

The video signal from generator 3 is divided into three defined brightness or elucidation levels that provide full relief

2 1

lung, -τ enlightenment and 4 enlightenment. For vectors, which assume an angle θ of more than 45 ° with respect to the vertical, for example the vector P, is the result of the illumination levels in each row of the grid as follows, using the unit of distance defined above:

X illumination for ^ tan Θ,

4 illumination for i tan Θ,

full illumination for tan Θ,

4 Illumination for ~ tan θ and

i enlightenment

for ^ tan Θ.

This continuous increase and decrease in the level of brightness ensures that the vector is practically non-stepped to the eye Image presents. This is especially important for near-horizontal lines. You can also see that for vectors like e.g. for the vector P the total horizontal width of the vector tan θ is proportional, which ensures that the total brightness of the vector is independent of the angle θ.

For vectors which have an angle θ of less than 45 ° with respect to the vertical, for example for the vector Q, one cannot follow the pattern described above for the brightness levels, since otherwise tan θ would be less than 1 and thus the duration of full illumination; would be smaller than a video element. Such vectors must therefore be in a special Way to be treated as will be described below.

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From Fig. 3 it can be seen that the vector generator 3 has a Random access memory M1 with a capacity of 16 words, all of which are 49 bits in length. The random access memory serves as an input-side data memory. The memory is constructed from integrated circuit memory elements, for example from memory elements of the type SN 7489 by Texas Instruments Limited.

Data with up to 16 vectors can be stored in the memory M1 will. A word of the memory space is allocated to each vector.

During the field retrace times of the raster, for each vector the following data can be sent via port 2 from the Computer 1 can be written into memory M1:

X ₀ : the X coordinate of the starting point of the vector, measured at the beginning of the vector writing surface;

Y: the number of the line deflection in which the starting point of the vector occurs (whereby only the lines of a partial image are counted from the upper end of the vector writing area) ;

the number, the-line deflection, in which the endpoint occurs, counted as

tan θ: as defined above.

of the vector occurs, counted as for Y; and

As you can see, the parameters of any one can be selected of the 16 vectors change without affecting the other vectors, namely by the fact that the appropriate Word of the memory M1 is addressed and the modified parameters are written.

Each word of memory M1 is in a number of data memories for the assigned vector as follows:

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(51) Eight bits as storage for X _Q.

(52) Eight bits as storage for Y _Q.
. (S3) Eight bits as storage for Y ₁ .

(54) Thirteen bits to store the numeric value by tan Θ.

(55) A bit to store the sign of tan Θ.

(56) A bit to indicate whether the amount of the component of tan θ is less than 1 or not.

(57) Thirteen bits to store X, the X coordinate of the vector in the line deflection currently taking place.

(SS) Four bits as the next address memory to the address of the next word to be processed in the memory M1, which offers the possibility that the words to be processed are processed in the memory M1 in any desired sequence can.

(S9) A vector bit which is set to the value 1 when the line deflection Y is reached and which is set to the value 0 when the line deflection Y _{1 is} reached.

(S10) Two shading bits, the purpose of which will be explained later.

During the field return of the raster and reading of data into the memory M1 via the connection 2, a sorting logic circuit 11 compares the value of tanQ to be written into the memory S4 of the data memory VSi with the other values of tan already in the memory Sh θ and modifies the content of the next address memory S8 of the data memory M1 in such a way that the next address memory S8 contains the address of that word which has the next lowest value of tan Q of each word. This makes it possible to process the vectors in the data memory M1 in an order with decreasing tan Q. The reason for this will be explained later.

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When writing each value of tan θ into the data memory M1 becomes the amount of the integral part of a comparator circuit 12 compared with 1, which sets the only bit in memory S6 of data memory M1 to 1 if the amount is less than 1.

The output from the partial memory S1 controls a data selection circuit 13 which supplies a binary output signal T with eight bits. When the output of the memory S6 is 1, which means that the integral component of tan θ is less than 1, the data selection circuit 13 outputs an output T = 1. If, on the other hand, the output is 0, the data selection circuit 13 delivers an output signal T = tan Θ, which is derived from the memory S4 of the data memory M1.

After a period of time allotted for data to be read in via port 2 has elapsed, but still during field retrace, the value X _Q in memory S1 of each word is written into memory S7 for the current * X of the same word Via a data selection circuit 14 and a binary adder 15. For the even fields or fields of the raster, the adder 15 only adds a 0 to the value of X _Q. In the case of the odd partial images of the raster, however, the adder counts ί tan θ to the value of X _Q before the result is written into the X memory S7 wdj.rd. The value of tan θ is obtained via a data selection circuit 16 from the memory S4 for tan θ of the data memory M1. As a result, the. _ Fig. 2 described shift of tan Q between odd and even fields achieved.

The vector generator 3 also contains a random access memory M2 with a capacity of 512 words, each of which has six bits B1 to B6. The memory M2 serves as a video memory which contains the information characterizing a line deflection of the video signal. ¹ This memory is made up of integrated circuit memory elements, for example memory elements of the type SN 74200 from Texas Instruments

^Limited 309818/1071 '

Each of the ί? 12 words in the memory M2 corresponds to one of the 512 video elements in the vector writing area of a line deflection of the grid. Initially, all bits of the memory M2 are set to 0. One in any given bit position of a given word occurring 1 means that the start or end point of one of the three brightness levels, namely

1 2

^ r illumination, ^ illumination and full illumination, on the video element occurs that corresponds to the word in question. It follows from this:

Bit video level

B1 = 1

B2 = 1
B3 - 1
Bh = 1

B5 = 1
B6 = 1

Illumination ON

5 Illumination ON
full illumination ON

4 Illumination OFF

Illumination OFF

full illumination OFF

The memory M2 thus stores a complete line deflection of the video signal in the form of the start and end point of the three individual brightness levels.

In Fig. 4a a part of the memory M2 is shown schematically, which stores the video signal for the line deflection section A-A shown in FIG. 4b shows the corresponding Video signal.

It is possible for two or more vectors to overlap during a line deflection, so that during this line deflection cover their illuminated sections / This possibility is allowed with the proviso that when reading from the Memory M2 a predetermined brightness level is not switched off until an equal number of switch-ons and switches-offs have been read out for this level and that the higher brightness level suppresses the lower one.

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The video signal at any line deflection is from _t to the input parameters of the memory M1 is calculated and written into the video memory M2, during a period of time between leaving the vector write area of the immediately preceding line deflection and re-entering the vector writing surface of the current line deflection. This period comprises the line flyback (12 microseconds) between these two line sweeps and a portion of each of the two sweeps.

The calculation of the video signal is carried out by a video memory loader control circuit 17 and a deflection counter 19 controlled. The counter 19 receives line and frame synchronization signals from deflection circuits 7 (Fig. 1) to provide an 8-bit output Y equal to the number of lines of the current field of the raster that equal to any given moment have been executed.

The calculation is carried out for each of the words (vectors) in the memory M1 in succession, specifically in an order which is determined by the next address memory S8 from the words.

The calculation of each word (vector) proceeds as follows, provided that tan θ is negative, as it is for vector P. in Fig. 2 is the case.

(At the beginning of the calculations, the content of the memory M2 0 set).

Step 1).

The control circuit 17 reads the vector bit from the memory S9 of the word and at the same time compares the value of Y from the deflection counter 19 with the values of Y _Q and Y ^ in the memory M1. If the vector bit is 1, the calculation continues with step (2). If the vector bit is 0 but YY is ₀ , the calculation continues with stage (2) and at the same time

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the vector bit is set to 1. If Y = Y ₁ , the calculation is continued, but the vector bit is reset to 0. If none of the above conditions is met (i.e. if the vector bit is 0 and Y is not equal to Y), the vector does not occur in the current line deflection, so that the calculation is interrupted and the next vector in the data memory is switched on, as determined by the next address memory S8 of the current vector. The calculation for the next vector begins again with stage (1).

Level 2).

(a) The content of the memory S7 for the current X des Word is read into a 9-bit accumulator A2 via a data selection circuit 21.

(b) The content of the X memory S7 is also fed to a 10-bit digital adder 22 via the data selection circuit 21, by adding T / 2 and reading the result into a 10-bit accumulator A1. (T is the output of the data selection circuit 13). The division of T by 4 is carried out in a data selection circuit 23, which in deviation of this division can also work in such a way that it divides T by.

The accumulator A2 now contains X, that is to say the video position of the starting point of the first X illumination period (see FIG. 4b).

A1 contains X + T / 2, which is the video position of the end point of the

1
first -τ - illuminating period.

(c) The contents of the accumulator A2 are used to address the IN part (bits B1, B2, B3) of the video memory M2 via data selection circuits 24 and 25. At the same time, the contents of the accumulator A1 are used to address the OUT part (bits B4, B5, B6) of the video memory M2 via data selection circuits 26 and 27. The contents of the accumulators A1 and A2 are calculated to an accuracy of more than half a distance unit (i.e. more than one video element) and rounded up or down to the nearest half unit (i.e. the closest video element) before being sent to the

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- 13 addressing the memory M2 can be used.

ϊ.

A check will be made / To determine if the bits' addressed in this way either the bit B1 or the Bit B4 already contains a 1, which can be the case if a previously calculated vector replaces the current vector in the current Line deflection overlaps. If neither one of these bit positions contains a 1, both Bit positions a 1 are written. If, on the other hand, there is already a 1 in one of these two bit positions, then prevents writing into the memory M2 for both bits.

Since the vectors are sorted in an order with decreasing tan θ the horizontal width of the current vector is always equal to or smaller than that of the previously calculated one Vector. Therefore, if writing in the memory M2 is prevented in this way, it only has the consequence that a lit section that is completely within a previously calculated lit section of the same brightness level is left out.

It is important that the IN and OUT bits are always paired are written or disabled so that the total number of ON switches in the memory M2 is always equal to the number which is OFF circuits.

i
Stage (2) actually runs together with stage (1) in order to reduce the time required for the overall calculation. If stage (1) is interrupted, stage (2) is also interrupted before any data is written into memory M2.

Level 3).

(a) Via the data selection circuit 21, the content of the accumulator A1 is read into the accumulator A2.

(b) The content of the accumulator Ä1 is selected via the data selection circuit 21 fed to adder 22, in which T / 2

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is added. The result is returned to the accumulator A1.

The accumulators A2 and A1 therefore now contain X + T / 2 and

X + T, i.e. the start or end point of the first% illumination period.

(c) The contents of the accumulators A2 and A1, which are in matching V / other rounded to the nearest half unit are used to address the memory M2 as in stage (2), and a 1 is written into the bit positions B2 and B5 addressed in this way, if both Bit positions are empty.

Level 4).

(a) The content of the accumulator A1 is read into the accumulator A2.

(b) The content of the accumulator A1 is added to T, and put the result back into accumulator A1.

The accumulators A2 and A1 now contain X + T or X + 2T, i.e. the start and end point of the full illumination period.

(c) The suitably rounded contents of the accumulators A2 and A1 are used to address the memory M2, as in step (2), and a 1 is written into the bit positions BJ5 and B6 addressed in this way, if both Bit positions are empty.

(a) The content of the accumulator A1 is read into the accumulator A2.

(b) T / 2 is added to the content of the accumulator A1. The result is read back into accumulator A1.

There are now X + 2T and X + 5T / 2 in the accumulators A2 and A1

included, i.e. the start and end point of the second -ψ -lightening period. 309818/1071

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(c) The appropriately rounded contents of the. Accumulators A2 and A1 are used to address the memory M2, and as in step (2), and a 1 is written into the bit positions B2 and B5 addressed in this way, if both Bit positions are empty.

Level (6).

(a) The content of the accumulator A1 is read into the accumulator A2.

(b) T / 2 is added to the content of accumulator A1, and the result is read back into the accumulator A1.

In the accumulators A2 and A1 there are now X + 5/2 and X + ■ 3T included, i.e. the start and end point of the second 4 illumination period.

(c) The suitably rounded contents of the accumulators A2 and A1 are used to address the memory M2, and as in step (2), and a 1 is written into the bit positions B1 and B4 addressed in this way, if both Bit positions are empty.

Level (7).

The memory M2 now contains all the information that the Identifies video brightness pattern that corresponds to the relevant vector for the current line deflection.

Simultaneously with the preceding stages (3) to (6), the content of the X memory S7 is via the data selection circuit 14 the fed to an input of the adder 15, and a value of 2 tan θ is added, which is via the data selection circuit 16 reaches adder 15. The result is brought back into the memory S7 for the current X value in order to be used for the next Row of the grid to serve as the X value.

The above-mentioned steps (1) through (7) are for the next Vector in memory M1 is repeated as it is by the next address memory S8 of the previous vector is determined.

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If the sign of θ of tan is positive (which means that the vector from left to right extends upwardly, rather than extending downward, as always for the vector P in FIG. 2 is the case), the above sequence as follows is changed :

(1) In part (b) of each of steps (2) to (6), the Size T / 2 (or T) subtracted instead of added with adder 22.

(2) In part (c) of each of steps (2) to (6), the Contents of the accumulator A2 instead of addressing the IN part of the memory M2 used to address the AÜS part, via the data selection circuits 26 and 27. In the corresponding Thus, the contents of the accumulator A1 are now used to address the IN part of the memory M2 via the data selection circuits 24 and 25 used.

(3) In the step (7), tan θ is subtracted from the content of the memory S7 for the current X by the adder 15.

When the amount of the integral component of tan θ is smaller than 1, as is the case for the vector Q shown in FIG. 2, the output T of the data selection circuit 13 takes the value 1, so that the values of the sizes X, X + T / 2, X + T, X + 2T, X + 5T / 2 and X + 3T overlap to a certain extent, if they are rounded up or down to the nearest video element. As already mentioned, the arrangement is made in such a way that that with such an overlap the higher Hellig- J level exceeds the lower. The result is in the Fig. 2 shown. During some line deflections, the brightness pattern runs as shown for line deflection B

2 ■ ■

is assumed that there is a video element ■ * elucidation, Ge l followed by a video element with full illumination and thereafter a video element ν illumination available. With a different line deflection, the brightness pattern runs as shown for line deflection C, which means that a video element with * r illumination is followed by a video element with full illumination and a video element with 4 illumination.

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As for the case of: near-horizontal lines this represents progressive increase and decrease in brightness ensure that the vector does not appear to the eye as a step-like image.

The calculations described above are carried out quickly enough so that the one available for calculation Time up to eight of the sixteen vectors can be processed. Although the arrangement according to their capacity up to can represent up to sixteen vectors in one frame of the grid, with a given line deflection, only up to eight of these vectors occur.

After the calculations described above have been carried out for all vectors in the current line deflection, the memory M2 is read out in synchronism with the execution of the line deflection by the cathode ray tube.

The reading of the memory M2 is controlled by a clock generator 28, its frequency is 14 MHz. This frequency corresponds to the division of the vector writing area with a line deflection in 512 elements. The output pulses of the clock generator 28 are counted by an address counter 29, which at the time of re-entering the vector writing area is reset to 0 on the line deflection.

The memory M2 is read out in that it is addressed with the content of the address counter 29 via the data selection circuits 25 and 27. In this way , each of the 512 words in the memory M2 is addressed at the moment at which ^: the corresponding element of the vector writing surface is scanned on the screen. ^:

The output of the memory M2 is fed to three up / down counters 30, 31 and 32 which correspond to the three video levels i illumination, 4 illumination and full illumination. These counters are initially set to 0 ^;

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If a word addressed in the memory M2 contains a 1 in any of its ON bit positions B1, B2 or B3, the associated up / down counter is incremented. If, in a corresponding manner, a word addressed in the memory M2 contains a 1 in one of its OFF bit positions B4, B5 or B6, the assigned up / down counter is switched back by 1. Therefore, if the content of one of the counters 30, 31 and 32 is zero, it means that the associated video level should be OFF since an equal number of ON and OFF signals have been read from the memory M2. Conversely, if the content of one of the counters 30, 31 and 32 is not zero, this means that the corresponding video level should be switched on, since more ON signals than OFF signals have been read from the memory HZ. It should be repeated at this point that, when writing into the memory KZ, precautions are taken to ensure that each ON bit is always assigned a corresponding OFF bit. When each word in the memory M2 has been read out, the content of this word is reset to zero in order to prepare the memory for the next line deflection.

The digital output from up / down counters 30, 31 and 32 is converted from a video output circuit 33 into a video output

signal implemented, which one of the three discrete levels ^ Hel-

2
ment, 7 illumination or full illumination, depending on which of the counters 30, 31 and 32 has a non-zero output. If more than one counter has a non-zero output, the higher video level suppresses the lower. The video output signal from the output circuit 33 is fed via an output line 34 to the mixer 5 (FIG. 1) and from there to the cathode ray tube 6.

It is advisable to divide the video memory M2 into two halves, each of which contains 256 words, each six bits in length. When writing to memory will be the two memory halves are addressed alternately so that adjacent Video elements in different halves of the store

get saved. When reading out the memory, similar

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licher way the two halves addressed alternately. Through this higher readout times are achieved than with an undivided memory.

In a modified vector generator 3, the video memory M2 can be replaced by two memories, each of which in the Is able to save a full video line sweep. While the content of one of these memories is being read out, the vector generator carries out calculations to transfer the contents of the other memory to the next line deflection bring up to date. With alternating line deflections, the roles of the two memories are reversed. By a such an arrangement considerably increases the time available for computation and includes a total line deflection period (64 microseconds) of the raster in addition to the flyback period. In this case, therefore, many more vectors can be processed and displayed at the same time (generally up to 40).

In another modification of the vector generator 3, the video memory M2 can be associated with an associative, i.e. content-addressed Memory to be replaced.

The video memory M2 shown in FIG. 5 contains at This modification has an associative memory which is divided into six memories, two for each illumination level. In the drawing there are only two memories 40 and 41 for the τ illumination level is shown.

Each memory contains a number of words of length of eight bits each. The content of each word in memory represents the X coordinates of the starting point of a given 4 level of illumination while the content is at the same The address in the memory 41 represents the X coordinates of the end point of this -τ -Elightenment level.

While the video memory M2 is being read out, the output an address counter 43 (which corresponds to counter 29 in FIG. 3), the associative inputs 48 of the memories 40 and

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fed. If there is a match between the input word and the content of a word in one of the two memories, an output signal occurs at the associative output which corresponds to this word and indicates that at this moment a τ level of illumination begins or ends.

The output from each word of the memory 40 is fed to one side of an associated bistable flip-flop 44, while the output from the corresponding word in the memory 41 is fed to the other side of the same bistable flip-flop 44. The bistable flip-flops 44 are clock-controlled by a clock generator 46 at the read-out frequency (14 MHz) of the arrangement. The current state of a given flip-flop 44 indicates whether the associated * * level of illumination is on or off at that moment.

The outputs from all bistable flip-flops 44 are combined in an OR gate 45. A 1 at the output of the OR gate 45 indicates that the video element being scanned has the -ψ highlight level .

The arrangement shown in FIG. 5 is for the ■ * illumination level and repeats the full level of illumination.

The use of an associative memory for the video memory M2 has the advantage that, as in the case of the arrangement according to the Fig. 3 does not require the input data in an order to be sorted with decreasing tan θ, since overlapping vectors do not pose any particular problem in this case. Namely, each vector is stored in a separate word of the video memory. Furthermore it is not required * - Lich, up / down counter for the output of the video memory to use.

Reference is made again to FIG. 3 below. The two shading bits in memory S10 of the input memory M1 are used to switch between two selected vector

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ren one -? - Use illumination shading. The two bits provide four different codes: one code indicates which vector switches on the shading, and another code indicates which vector switches off the shading. A third code indicates that no shadowing is assigned to the relevant vector.

If the shading bits of a given vector are set according to a fourth code, the highlighting will be that Vector completely suppressed. This allows all the necessary parameters for a vector stored in the input memory M1 and can be suppressed in a simple manner with a single computer input, until it is necessary to represent this vector.

The vector generator 3 can be used to generate curves, by stringing together several vectors so that the end point of one is the same as the start point of the other vector is. The greater the number of vectors used, the smoother the curve shown.

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Claims (1)

- 22 - Claims Device for generating a video signal for input into a raster-scanned display device for the purpose of displaying at least one graphic symbol,
characterized by an input memory (M1) for storing digitally represented input parameters of at least one graphic symbol, a digital data processing device (11 to 29, A1, A2, M2) for processing the parameters for the purpose of generating a digitally represented output signal which characterizes the video signal, and a device (30 to 33) for converting the digitally represented output signal into the video signal. 2. Device according to claim 1,
characterized in that the video signal is divided into several defined brightness levels. 3. Apparatus according to claim 1 or 2, characterized in that the digitally represented output signal identifies the start and end point of at least one video brightness level within the line deflections of the video signal. 4. Apparatus according to claim 3,
characterized in that the means for converting the digitally represented output signal contains at least one up / down counter (30 to 32) which is designed such that it counts up when the digitally represented output signal indicates a starting point of a video brightness level and counts down when the digitally represented signal indicates an end point of a video brightness level, and comprises means (33) for generating a video signal which shows the brightness level only when the count of the counter is not zero. 309818/1071 ί ?. Device according to one of the preceding claims, characterized, in that the digital data processing means includes: a video memory (M1) for storing information obtained from the Video signal identifies a part that corresponds to at least one line deflection of the raster, a computing device (11 to 28, A1, A2) to perform calculations on them Parameters consecutively with respect to each line deflection of the grid for the purpose of generating the information for loading the Video memory and a read-out device (29) for reading out the information from the video memory (M2) when the Line deflection calculations to produce that portion of the digitally represented output signal that corresponds to the line deflection. 6. Apparatus according to claim 5,
characterized in that the input memory (M1) is designed in such a way that it stores the parameters of several graphic symbols, and in that the computing device (11 to 28, A1, A2) is designed in such a way that for each line deflection of the raster the Performs calculations on the parameters of each of the graphic symbols in sequence. 7. Apparatus according to claim 5 or 6, characterized in that that the video memory (M2) has memory space for several words, the successive sections correspond to a line deflection of the raster, and that the read-out device (29) is designed to address each of the words sequentially at a predetermined frequency and converts the content of each word addressed in this way into the digitally represented output signal. 309818/1071 8. Device according to claim 7 »
characterized in that the computing device (11 to 28, A1, A2) is designed in such a way that it calculates in which sections of the line deflection the start and end points of at least one video brightness level occur within the video signal, and that they are converted into the words of the Video memory (M2) corresponding to these sections, enter digital codes that contain the initial and Specify the end point. 9. Apparatus according to claim 6 and 8, characterized in that that the computing device (11 to 28, A1, A2) is designed in such a way that it carries out the calculations on the parameters of the symbols in an order of decreasing dimension of the symbol in the direction of the line deflection makes it after execution of the calculations on each symbol Checks whether the start or end point of a video brightness level that corresponds to this Symbol is assigned, occurs in the same * section as a previously calculated symbol, and that, if so, it prevents the input of the digital codes with regard to the later symbol. 10. Apparatus according to claim 9,
characterized in that the symbols are straight vectors and in that the arithmetic unit (11 to 28, A1, A2) is designed such that it performs the calculations on the parameters in an order with decreasing tanQ, where θ is the angle between the vector and a direction perpendicular to the grid lines. 11. Device according to one of claims 5 to 10, characterized in that that the video memory (M2) is designed such that it contains information stores that identifies that part of the video signal which corresponds to a single line deflection of the raster, and that the entire device is set up in such a way 309818/1071 is that the arithmetic unit (11 to 28, -A1, .A2) does the calculations with respect to a line deflection during the line deflection flyback period immediately preceding that line deflection executes. 309818/1071