DE2233597A1 - CIRCUIT ARRANGEMENT FOR ERROR CORRECTION FOR DATA TRANSFER - Google Patents

Description

DR. MÜLLER-BORG DIPL.-PHYS. DR. MANICZ OIPL.-CHEM. DR. DEUFEL DlPL-ING. FINSTERWALD DIPL.-ING. GRÄMKOW

Munich, ~ ⁷ ' ^JüW "i'ik / th - C 2572

COMPAGHIE INDUSIRITCr.T.E DES

CIT-ALOAiEEL

12, rue de la Baume, Paris / France

Circuit arrangement for error correction * for data transmission

The invention relates to data transmission on a telephone line. It concerns the data transmission on a telephone line by means of pulse code modulation (MIC), their scanning sequence is faster than the telegraph speed (number of bits per second) which results in firstly in a MIC frame To transmit information bits, secondly, to transmit duplication bits, so-called redundancy bits, and, thirdly, to transmit additional ones Bits, which are referred to as the redundancy indicator that it namely enable to recognize whether a certain bit is an information bit or a redundancy bit. The consequence of the Redundancy display values follows a predetermined law, the invention providing the means to carry out a correction, if this law is not fulfilled. The application is data transmission in a pulse code modulation frame.

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Dr. Müller-Bore Dr. Manitz Dr. Deufel Dipl.-Ing. Finsterwald Dipl.-Ing. Qrämkov Braunschweig, Am Bürgerpark 8 8 Munich 22, Robert-Koch-Strasse t 7 Stuttgart-Bad Cannstatt, Markietaa «: p Telephone (0531) 73887 Telephone (0811) 293645, Telex 5-22050 mbpat Telephone (071Ί) 6872Sf Bank: Central Cash Office Bayer. Volksbanken, Munich, account number 9822 Post check: Munich 85495

The transmission of data on a telephone line takes place at a telegraphic speed which is below normal Telegraphy speeds can be selected, for example with one of the following speeds: 1200 - 2400 - 4800 9600 Bits per second.

The scan sequences of the MIC frames are in operation for data transmission on telephone lines multiples of 500 Hz. To avoid the transmission of data in a MIC frame Losing information requires using a higher frame rate, in a fixed ratio. For the telegraphic speeds V mentioned above, this leads to the following scanning sequences:

Ratio F / V 5/4

F. Hz for 1200 V 1500 Hz Il 2400 b / s 3000 Hz ti 4800 b / s 6000 Hz Il 9600 b / s 12000 b / s

5/4 5/4

This additional speed of the frequency MICF over the Telegraph speed V leads to an interruption, the same information bit of data twice in a row to feel. In this case, the second MIC bit corresponds to the same data bit and is referred to as the redundancy bit.

In these circumstances it is necessary to add an additional To send information on the line, which makes it possible to recognize whether a received bit is an information bit or is a redundancy bit. This is done by systematically using so-called redundancy display bits in a fixed sequence can be inserted with the following agreement:

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if the received redundancy indicator bit (IB) equals 1, the previous bit is a redundancy bit (BB); if that Redundancy 'bit is 0, -is the previous bit an information!) it. - ■

The further description takes place in the context of a data transmission with a specified telegraphic speed, for example with 4o00 b / si it should be noted that the The conclusion drawn applies to any telegraphic speed can relate, with a correspondingly adapted HIG frequency.

From the table above it can be seen that in principle a Ratio of 5/4 between the MIC frequency (6000 Hz) and the telegraph speed (4800 b / s) is available. It it is necessary to make the space available for redundancy displays as well. Simple arithmetic Relationships lead to the introduction of a redundancy display in four steps. Goes under these circumstances the MIC frequency from 6000 Hz to 8000 Hz (»6000 x |).

The assigned to the different telegraph speeds MlC frequencies thus have the following real values:

2000 Hz for 1200 b / s

4000 Hz "2400 b / s

8000 Hz "4800 b / s

16000 Hz "9600 b / s

It is easy to show that under these ideal conditions (data clock synchronized with the MIC clock, no "distortion, no transmission error) the flow of redundancy displays

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is periodic (with a period of 01011).

When synchronization is not guaranteed and when distortion phenomena occur, this period becomes a Pseudoperiod, and this then leads to the following results being obtained under the distortion limits given below en:

1. The values 0 (no redundancy) are always isolated, there are never more than two consecutive;

2. The values 1 (redundancy) occur no more than twice in a row but never three or more values.

It follows that any injury from any of these Criteria causes a transmission error and, conversely, that every transmission error is a violation of means one of these criteria.

The role of the corrector is such Fall in performing the required inversion of value. Through an in-depth analysis of the various Opportunities can be shown that in certain cases the incorrect redundancy display is corrected immediately and that in other cases the correction takes place with a time delay.

The correction of the redundancy display according to the invention is based a \ if the following postulate:

There are never two consecutive false redundancy displays. It can be shown that with practical values the

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BATH ORIGINAL

parameters given above with a probability

-10

out of 10 applies.

On the other hand, it is forbidden to make chain corrections, the result of which would lead to an error propagation: if one correction is made, at least two Waiting for cycle times before a decision is made as to whether a new correction may be necessary

The invention is described below, for example, with reference to the drawing; in this shows: · ■

Fig. 1 three graphical representations showing the interposition represent redundancy bits between certain information bits,

2 shows the correction process in various error cases,

Fig. 3 © i ¹¹ organizational chart of the correction device according to the invention,

Ii ¹ Xg. 4 a synoptic diagram of the correction device and

FIG. 5 is a logic circuit diagram of an embodiment of FIG correction device according to the invention.

Fig. 1 shows three sampling diagrams with a time sequence at a speed of 4800 b / s for a HIC frame at 6000 Hz. The sampling pulses MIO are respectively arranged in groups of three. There is redundancy when two MIG pulses occur in the same data time. In this Case, the reference line is indicated in a solid line. Each chart contains two lines: are on the top line

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the sampling times are plotted on the lower line the data plotted.

Diagram a) corresponds to the ITaIl with low distortion: it can be seen how the above-mentioned pseudoperiod is formed: 01011, 01011.

Diagram b) corresponds to a first limit distortion case of the data signal, which results in an extension of 20% of the period b'ei '/ periods j it can be seen that a sequence of three redundancies is formed (B).

The diagram c) corresponds to a second distortion limit case of the data signal, which / o during the period in 5 periods draws a shortening of the data signal by 20 ° to see: it is seen that a sequence of two Michtredundanzen forms (KB).

From these two observations it can be deduced that if the condition xtf is imposed on the input signal, to show a distortion of less than 20 % in the sense of an extension in seven periods and below 20% in the case of five periods in the sense of a shortening, in a sequence of ■ redundancy displays, three consecutive displays that are equal to 1 never occur, while two consecutive displays that are equal to 0 never occur.

The principle of error correction can be derived directly from this derive: every time the correction device detects two successive redundancy displays that are equal to 0 it sets the second to 1; every time the correction device detects three consecutive "indications,

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the same. 1, it sets the third to 0.

It also waits if a correction is made the correction device at least two new displays a "b before a new correction is carried out.

The 3? 2 shows a sequence of redundancy displays, in which nine positions are given as an example, and it becomes assumed that there is an error (reversal of a value) in each of the nine positions.

The law of the corrector is to replace a second 0 with a 1 that follows a first 0 and to replace a third 1 with a 0, wake up followed by a double 1.

The correction device carries out an immediate correction under the following conditions: Case (1), (2), (4-), (6), (8), (9) »it performs a delayed correction under the following conditions: Case (5)» (5), (7) · In the first case the correction relates to the faulty bit. In the second In this case, the correction is triggered by an incompatibility based on a previous error in a step can be attributed to: the correction takes place with a delay time, the corrected sequence is not identical to the specified 1-sequence, it allows an error to persist.

In cases (3) and (7), if a correction would be carried out and no precaution would be taken to wait two periods before making a decision, whether a new correction is possibly to be carried out, a chain correction phenomenon occur, the consequence of which is a

Error propagation would be. Instead of such an arbitrary one The result in the transmission sequence is locally left incompatible: two zeros in case (3), three 'ones in the pail (7). "

In the case of the immediate correction it obviously arises the following advantage: the error is deleted, no trace remains.

It will be shown below that in a particular example, namely in the case of the delayed correction, although a trace of the Error persists, the correction of which is no less indispensable.

Assume that the following signal is sent out (remember that BB is a redundancy bit means and that IB means a redundancy display):

Signal MIO sent a t 1 IB c d e IB f gh ... (1) Signal MIC without error

receive _it abBBIcdeOfgh ... (2)

Signal MIO -ofese- ! Error

receive abiOcdeOfgh ... (3)

Signal MIC corrected "

received ab1Ocde1fgh ... (4)

Data according to (2) abcdefgh ...

Data according to (3) abicdefg ...

Data according to (4) abicdfgh ...

The error lies in case (3) in the "transition of the first IB from the Value 1 to value 0. The delayed correction is in the transition of the second IB from value 0 to value 1.

Ds. it can be seen that in the data according to case (5) (not corrected error) beyond a b all bits are shifted, i.e. i.e., are wrong. In the dab according to "case (4 ·) lies a disturbance that affects the bits ede, after which the proper relationship is restored,

Fig. 3 "is a diagram showing a summarized Representation of the mode of operation of the correction device according to the invention reproduces.

The correction device represents a sequential system, its configuration as a function of the redundancy displays that occur is to be understood. This system has four states, which are linked together by the following conditions are as shown in the organizational chart of FIG. 5;

Transition from state (oQ to state (ß) if IB »0 "0 *)" (T) "- 1

Transition from state (S) to state (ß) when IB * O

Every time there is a transition to the state (<*), the last display is corrected: when the system changes from (ß) to (oO, the last redundancy display goes from O to 1 over j if the system changes from (<f) to (<*.) goes over, the last IB goes from 1 to O.

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On the other hand, examination of the Qrganigrainm shows that after performing a correction (state 6 * 0), at least two steps must be waited for before a new correction is carried out.

The i'ig. 4 is a synoptic diagram of the correction device in symbolic i'orm. The correction device has two subgroups: an organ (1), which follows the change in the correction state, the occurring redundancy display (IB) being received, as well as the timing of the redundancy displays HB. At the output, two signals A and B appear Combination makes it possible to define the four states that serve as the basis of the J'ig, 3 organizational chart. These signals are fed to organ (2) which also receives IB and which represents a circuit which carries out the correction - it supplies the corrected redundancy ^{display IB 1} as an output signal.

The states A and B are created by two storage elements supplied (flip-flops), which are used to store the four states. For example, the following can be used Establish relationships that represent a coding chosen at random from the 24 possible (24 «41) are;

«X A. B. State ß 0 0 State r 0 1 State 1 0 State 1 1

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The following truth tables can be derived from this:

Point in time N. Point in time N. Time N + 1 Point in time W IB A B state A B state IB ¹ 0 0 0 * 0 1 ß 0 1 0 0 «. 1 0 r 1 0 0 1 ß 0 0 oc 1 + 1 0 1 ß 10V Ί 0 1 o r 0 1 ß 0 1 ι ο r 11i 1 0 1 1 δ 0 1 P, 0 ' 1 11i 1 0 * 0 ++

In the case marked with +, a correction 0-1 and takes place in the case marked with ++ a correction of 1-0 is made in accordance with the organizational chart in Fig. 3

Figure 5 is a schematic of one embodiment of a Correction device, which is the organizational chart of Fig. 3 and corresponds to the xynoptic scheme of FIG. 4-.

It has an inverter 10 at the input, which receives the clock of the redundancy displays HB, and it has an 'AND circuit 11, which receives the occurring signal S and HB and supplies IB; it also has two tilting stages 12 and 13, which receive the signals HB on the terminal H, and those signals whose Origin is explained below and provide A and A, B and B, respectively.

One inverter (14) and seven UUD circuits (15, 16, 17, 18, 19, 20, 21) enable the terminal D of the trigger stage 12

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to apply a signal:

(IB) + AB, and the terminal D of the flip-flop 13 a signal to be added: AB + (IB) (A + B).

An AND circuit 22 which receives HB, (A + B) and (B + IB) provides IB '.

The circuits 21 and 22 form part of the subgroup 2 of FIG. 4. The circuit 20 is at the same time a part of subgroup 1 and subgroup 2. All other circuits form part of the Subgroup 1 of the i'ig. 4th

- patent claims -

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Claims (2)

Claims AJ Circuit arrangement for correcting the redundancy display in a data transmission, which is integrated in a pulse code modulation frame with a higher sampling frequency than the telegraphic speed of the data transmission and therefore has redundancy bits, with the pulse code modulation signal and the 'i'akt of the redundancy displays being received at the input forbidden sequences (00 ... and 111 ...) are based, characterized in that a logic device with four possible states (■% ö, r, <S), which are taken sequentially, is provided, according to the value of the successive redundancy displays (IB) and that a reversing device for the value 0-1 in the case of the transition from the state β to the state «* and a device for reversing the value 1-0 in the case of the transition from the state f to the state < * .. 2. Circuit arrangement according to claim 1, characterized in that two flip-flops (12, 13) are provided which have the input terminals H and D, which continue to have outputs A and S, B and B which continue to have in each case at the terminal H a signal BB "received from comes from the cycle of the redundancy displays, and on their terminals D two logical signals are received, which are developed from A, A ~, B and B, one of which ("ΪΒ") + AB and the other AB "+ (Tb") (A + B ") isb, where IB is the one Redundancy display denotes, which from the occurring signal S through an AND gate with the help of the clock signal HB - is developed. 209883/0874