DE2228204A1 - ADJUSTMENT - Google Patents

Description

Patent attorneys Dipl.-Ing. F.Weickmann, 799Ρ7ΠΑ.

Dipl.-Ing. H. Weickmann, Dipl.-Phys. Dr. K.Tincke Dipl.-Ing. RA-Teickmänn, Dipl.-Chem. B. Huber

8 MUNICH 86, DEN

PO Box 860 820

MÜHLSTRASSE 22, CALL NUMBER 98 3921/22

Automix Keyboards, Inc., 13256 Horthrup Way, Bellevue,

Washington, 98005, USA

Adjustment device b

The invention relates to a jus tieraj> ready for pasting a remaining adjustable line noise during operation a typesetting machine.

With a keypad apparatus, output information in Form of a paper tape can be generated as input information a typesetting machine, such as a light printing machine, or a device for casting fixed lines of letters serves. First, a row length for a given column size, e.g. a pica measure, is determined and this information punched into the punched tape to control the setting machine. At the end of the following line, the operator must However, similar to a typewriter carriage return, enter an end-of-line character so that the line has a predetermined one Line length does not exceed.

Heretofore, relatively extensive apparatuses have been used which specify a width for each selected character, which the character-

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Add up brei bo to an indication of the line length and the one Show almost filled line. A relatively large number of connections to the Keys of the keypad necessary to feed the widths of the characters. The decoding apparatus in turn provided input signals to a binary evaluation device, the - "Ln .the width the character v / leather generated binary output signal. The width of the characters was used to count down one line of letters ichers used. An analog output signal was often used used to operate a measuring device that the remaining Displayed a length of 1 meter and a predetermined length when it was reached Line length indicated an adjustable line.

The i'lrf indurif »: provides as a task a jus ti or apparatus which indicates dom \ '< -diotiungiimann that every goal is long; is to avoid unnecessarily long gaps between the ϊ / locations and lic shows the actually remaining lines.

The Setrxiaschim processing the punched tape. adjusted, jficl-; Row automatically by scrolling through the column Vsirfr'iiiJorun / ·; fills the spaces between words, womi the line length is long enough to be written in a predetermined, adjustable range to fall.

The invention solves its task in that a storage device a code signal for a character and e) in digital width signal for an increase width of the Character indicates that a memory counter is a digital, i / ert corresponding to the remaining line length stores that an incremental width counter means the width signal the memory device receives and changes each value in the memory counter according to the width signal and that one Display device shows the value in the memory counter.

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In one embodiment, what counts is; a binary counter corresponding to the predetermined line length supplied to the apparatus and
sends a binary output signal to a setting machine.

In a further embodiment of the invention, a circuit enables a character or a word to be erased. When deleting the character or word, the counts
Memory counter adds the saved width of the deleted part accordingly.

The invention provides an improved and simplified
Apparatus which stores the width of successive characters selected by the keypad of the typesetting machine and which displays the remaining line length. Of the
Apparatus furthermore has the advantage, by storing the width of successive characters to be printed, to deliver a digital reproduction of the width directly to a tape punch or a similar device, the reproduction of the width corresponding to a character code of a letter. The device continues to store the width of consecutive characters and digitally displays the remaining line length continuously in decimal format. By the
Summing up the widths of successive characters to be printed, the improved and simplified apparatus indicates as soon as an adjustable line is completed. In
In a further embodiment, the stored widths can be corrected when a word or a character is deleted.

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In order to explain the structure and the operating characteristics as well as further advantages, the invention is intended below in connection with the drawings, wherein like reference numbers refer to like elements.

Fig. 1 is a block diagram of a first part of the invention Apparatus;

Fig. 2 is a block diagram of a second part of the invention Apparatus;

Fig. 3 is a schematic circuit diagram of a switching device; and

Fig. 4 is a schematic circuit diagram of a typical one used Micro storage.

In a first section of the apparatus, FIG. 1 shows a keypad 10 which is connected to a tape punch 14 via lines 12. The keypad 10 provides output signals that the tape punch 14 according to the normal
Operate "TTS" telex or other suitable type of code. The keypad 10 and the tape punch 14
are common standard types and should not be described in detail. The punched paper strip then forms the input signal for a typesetting machine, such as a photo printing type setting machine or a device that casts fixed lines of letters from hot metal. A display signal 16 of the
Apparatus indicates to an operator as soon as a line is almost filled. This means that the operator is alerted by the display signal 16 as soon as the summed up thickness of the characters and spaces in a line almost fills a complete total length of the letters indicated by a column dimension is. In the meantime there is a visible

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bare display device 18 by the remaining line length continuous numerical reproduction of a digital number.

The display signal 16 is actuated at the point in time at which the line of indicated letters fills the column dimension adjustably. A minimum distance (between the words) and a maximum distance are given. When the number of Spaces or spaces indicated by the keypad 10 can be expanded so far that they fill the rest of the line, the display signal 16 informs the operator, while the display device 1Π Lhn constantly informs about the remaining line length, ITu a suitable one Time can be an end-of-line character using the keypad 10 delivered v / earth; The typesetting machine, dio the punched tape can then be scanned by inserting mechanical spacers or something similar between the words that make up the cell ,adjust. In this description the term "spacer" is used used synonymously with the expression "Leerstelle", to select or key in a space nti To designate keypad 10.

On closer inspection of the invention, the starting line will be grounded of the keypad 10, each character or space physically represented in a print line is to be delivered over lines 20 in a normal "TTS" telephoto code or another type of character code. The lines 20 correspond in this way to the lines 12, which are connected to the tape punch 14 and lead, each by itself, a signal that is present or absent the presence or absence of a hole in the punched tape is equivalent to. Lines 20 are connected to a micro-memory 22 and a code on lines 20, the

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corresponds to a character or a space, a digital output signal on lines 24 and "6 air digital" causes a character width to be displayed , or a part of it. The connection between these growth units and the conventional Pica-f-Wi or something similar is explained below.

The micro memory ??. has a large number of semiconducting elements in a mahr ix. A given'Μch ^ nkode therefore causes a 'digitally indicating signal or its reversion on all lines 24, 26. The remaining elements are preferably EH.polarransistors or field effect transistors. the Ilikrospeicner 2.2 is Uriwirkna-.imnchen ansgevrihlter Ffnlbleiterolcjinenhe on elnen special Typensatr nrogmmmioi · 'and, upon delivery of a Zeichenkodec eino di £; it:.. iL "presentation nasty A'ingangnsignals in growth units or TeiifJti: \ ev Zuwachseiiihf-Lt from . On this VWne wrvi «-. through the pro gr π ? r; \\. β η ing selected facilities segmented. The Hikrosneicher PP- can be a ^ ur-cL Monolith ic flenorios En ", ^ ffer t ^{! Gter n} rogramnierbnrar 'ί'γρ ο ^! Er a MO.'. 1 Li'l-Type, as he · z.ü. fUirrh Intel Corp. is produced "are provided 2 ^ 6 rnögiiche digital outputs _f of which are assigned by" w i type ° sets or magazines in each case 120 a. A switching device (not shown) switches between the two type sets or magazines. Furthermore, a large number of such micro-memories are provided, which can be switched between other type sets in a conventional manner and, moreover, can be expanded or exchanged for additional type sets.

In the implementation form described here, the micro-memory gives 22 a character width in binary coded form. The lines

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BATH ORIGINAL

24 transmit a first number in the form of a series of binary numbers, while the output signals on lines 26 express a second number or a higher order number in the form of binary numbers. The binary numbers are fed to respective counters 28 and 30 which together form an incremental width counter. Each of these binary counters 28 and 30 may count up or down, ie from O to 15 at 0, and generates a "VorV. ^R AERTS ⁿ output signal or in the reverse direction, a" reverse "output. The backward output signal of the binary counter 28 and 30 an input of a NOR gate's 32 is supplied. the Zuwaehsbreitenzähler 28, 30 principally operates as a down counter, which will hereinafter become more apparent, and a connection 34 to a downcounting input, the output signal transmits a clock signal generator 36. a forward signal output 37 and a reverse signal output 38 of the binary counter 28 are connected to an upward and a downward counter input of the binary counter 30. If the binary counter 28 counts in the positive direction and reaches 0, an up output signal on the line 37 advances the counter 30 by 1. If the binary counter 28, however, downwards above 0, the output signal on line 38 finally switches counter 30 by one unit t down. Counting circuits of this type are known and will not be described in detail here.

The digital value of the character width output from the micro-memory 22 is not "counted" in the incremental width counter 28, 30, but is fed directly to the incremental width counter 28, 30 in response to an evaluation signal. The evaluation signal is sent via lines 40 and 42 are supplied from a threshold detector 44 via an inverting amplifier 46. In response to the evaluation signal takes up the incremental width counter 28, 30 via the lines 24, 26 on the digital output signal directly by using it as a register works. At this point in time, the incremental width counter 28, 30 contains exactly that which is supplied via the lines 24, 26

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numerical output signal. This output signal is momentary supplied by the micro-memory 22, but in the incremental width counter 28, 30 saved.

Whenever a telex code character (as a representation of a character or otherwise) on lines 20 occurs, the threshold value detector 44 is actuated via one of the diodes 48. The threshold detector 44 indicates the presence of a code character and emits a positive pulse. The pulse is used by the reversing amplifier 46 as an evaluation signal inverted for the incremental width counter 28, 30. if the code character represents a character or a space, the incremental width counter 28, 30 stores this over the lines 24, 26 supplied output signal. The output signal for the width of the spaces indicates a minimum space between the words.

An output of the threshold detector 44 is via a capacitor 50 with an input of an inverting amplifier 52 connected, which operates an interlock circuit 54. The amplifier 52 is biased so that it has a positive output pulse after the evaluation output pulse from the inverting amplifier 46 has elapsed gives away. This output pulse from amplifier 52 activates the latch circuit 54 and causes a NAND gate 56 applied low output signal. The NAND gate 56 consequently has a high output signal and switches the clock signal generator 36. The clock signal generator 36 is an astable multivibrator and outputs via the line 34 an input signal for counting down the incremental width counter 28,30. If the incremental width counter 28, 30 is different from the original The value read in from the micro-memory 22 counts down to 0, sets the two inputs of the NOR gate 32 fed reverse signal has its output signal on high potential, thereby resetting the lockout circuit 54

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and the clock signal generator 36 is switched off. In the meantime the clock signal generator 36 has output a number of clocks which is the same as that originally from the micro-memory 22 is counted in the incremental width counter 28, 30. The clock signal generator 36 has an output frequency which is so large that it counts down the incremental width counter 28, 30 before the next output signal from the keypad 50 en can.

The line length suitable for filling a desired column dimension is adjustable by a plurality of switches 58, each of which is designed to provide certain switch outputs grounded in a binary coded decimal sequence according to the desired number. The switches 58 are available for selection or the desired line length is fed in in incremental units. In the embodiment described, the counts Clock signal generator 36 the incremental width counter 28, 30 in Quarter increment units. The outputs of the? Switch 58 are connected to decades 60, 62, 64 and 66 of a memory counter. Each of these decades 60, 62, 64 or 66 has an im essentially the counter corresponding to the incremental width counter 28, 30 described above. The counters are in cascades and provide a binary coded decimal counter Outputs of the decades are connected to decoder circuits 68, 70, 72 and 74.

To the number selected on the switches 58 in the memory counter To bring in 60, 62, 64, 66, a button 78 is pressed to trigger, which sets a monovibrator 80. The monovibrator 80 then transmits a trigger pulse to a line 82

a NOR gate 84. The decades 60, 62, 64 and 66 respond to the trigger pulse received via the line 82 the information directly in binary coded, decimal form

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the switches 58 on. The monovibrator 80 emits a single positive pulse on which the output signal, the NOR gate 84 drops briefly and emits the trigger pulse to line 82. The same trigger impulse is effected via a cable 88 a presetting of a two-stage division counter 86.

The decoding circuits 68, 70, 72 and 74 have seven-segment driver outputs, which are connected to display devices 18 via resistors 76. Each display device 18 is as Illuminated display (e.g. Monsanto "Man" No. 1) carried out. The light display has seven horizontal and vertical light elements which, all excited together, form a visible representation of Figure 8 in block form. The other digits are formed by a smaller number of segments. In the example shown, the number is 1296 from switches 58 is read into the decades 60, 62, 64 and 66 and appears at the beginning of each line on the display devices 18.

The one generated by the clock signal generator 36, an incremental subunit Representing pulses form an input signal of the division counter 86, which in turn has a NAND gate 90 and 92 deliver up and down counting pulses to the memory counter 60-66. The NAND gate 92 is normally switched on, which is why the memory counter 60 to 66 from the value initially read in from the switches 58 downwards counts. This process is described in more detail below. In this particular example, the clock signal generator 36 outputs four impulses for each unit of growth width. The division counter 86 therefore has two stages and the second stage is there input pulses via a line 94 as the number of incremental units to NAND gates 90 and 92. If both inputs of one of the NAND gates 90 or 92 are activated, there are this an output signal that the memory counter 60 to advances in the selected direction.

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Since the division counter 86 counts quarter and half incremental units, display devices for such are obvious quarter and half increments are provided. Additional switches are used for quarter or half increments, in connection with the switches 58, for presetting one or both levels of the division counter 86.

When the NAND gate 92 is on via a line 96, the memory counter 60-66 counts similarly to that by the clock signal generator 36, for each new character after 0, the incremental width counter 28, 30 counts down a part of the previously over the Switch 58 read-in line length down. A total stored in the memory counter 60 to 66 decreases with each subsequent characters or space up to an adjustable value. The display devices 18 show the remaining Line length and the operator is constantly informed of an approaching end of line. The decimal Coded output signals of the decades 60, 62 and 64 also form input signals of a comparator 98 (FIG. 2). the The combined lines 100, 102 and 104 of the outputs of the decades 60, 62 and 64 are connected to the comparator 98 in FIG tied together. Here four lines are combined and transmit a binary coded decimal place. It will only the three lowest decimal places compared.

The comparator not only takes the output signals from decades 60, 62 and 64, but also takes the corresponding binary coded signals Decimal output signals of a register with one decade 106, 108 and 110 each. The register 106, 108, 110 is a "Up" counter and therefore only shows up counting Lines 112 and 114 between the stages. The corresponding decimal places are digit by digit in the comparator 98 compared, i.e. the units digit of lines 100 from decade 60 is, as the lowest digit, with the

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output signal of decade 106 compared, while the output signal of decade 62 on lines 102 with the output signal of decade 108 and the output signal of decade 64 on lines 104 with the output signal of decade 110 is compared. The register 106, 108, 110, as will be explained in more detail below, stores a value that corresponds to the represents the maximum allowable expansion of a space multiplied by a number of the spaces. To this Way, each time the operator selects a space on the keypad 10, the space in the register 106, 108, 110 number contained by a number of units that correspond to a predetermined permissible extent of each Correspond to the gap. When the memory counter 60 to counts down from the preset line length, so the register 106, 108, 110 counts up and gives a maximum total value up to then by the operator in the line indicated spaces. The comparator suitably has a number of EXCLUSIVE-OR gates, Compare the BCD input signals of decades 60, 62, 64 and decades 106, 108, 110 digit by digit until they are equal Output signals occur or until the output signals of decades 60, 62, 64 reach the output signals of decades 106, 108, "exceed". When comparing, the comparator 98 emits a signal and actuates a blocking circuit 116. The blocking circuit 116 switches on the display signal 16, which in turn emits a light signal, an audible sound or something similar. A The line print setting signal resets the blocking circuit 116 via a line 118.

As soon as the operator receives a signal from the display signal 16, he observes the displayed by the display device 18, units remaining in the line and terminate the line as soon as # possible by using the keypad

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provides a suitable code character. The tape punch 14 punches this code character into the punched tape and the setting machine starts a new line in response to this code character. The setting machine naturally adjusts the completed one automatically Line to the desired length. If the operator finds that he cannot end the line immediately, he can they decide whether the remaining line length displayed by the display device 18 is a completion of a Word allowed or whether the word should be split or deleted.

The code character output by the keypad 10 for the end of the line resets the blocking circuit 116 via the line 118. Pressed at the same time as the code character for the end of the line was issued the keypad 10 via a line 120 the NOR gate 84 and the memory counter 60 to 66 reads the entire line length from the switches 58 on again.

A maximum value of the extent of each space becomes entered into the apparatus via switch 122. Switches 122 are essentially the same as switches 58. Each of the switches 122 outputs a binary-coded decimal output signal to an up- and down-counting counter 124, 126. Of the Counters 124, 126 have counting decades 124 and 126. The counting decades 124 and 126 are connected to one another in essentially the same way as the counters 28 and 30 described above the keypad 10 at the end of a space character on a line 128 via an amplifying and pulse shaping Circuit 130 reads an evaluation signal from it as a register operated counters 124, 126 the information from the switches 122. A flip-flop operated simultaneously via a line 134 Circuit 132 switches on an astable multivibrator 136 which generates a series of output pulses. The astable

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_ 14 -

Multivibrator 136 is suitably similar in construction and its operating frequency to the clock signal generator 36. The output pulses of the astable multivibrator 136 are a Input signal of the counting decade 124, through which the counter 124, 126 is counted down from the maximum value of the expansion read in from the switches 122. The one over a line output pulses fed to the register 106 * 108, 110 at the same time of the astable multivibrator 136, the registers 106, 108, 110 count up. The register 106, 108, 110 counts each space character output from the keypad 10 upwards and continuously stores a value equal to that of the number is the space entered by the keypad 10, multiplied by the allowable value of the space extent. At the If a blank occurs, the flip-flop circuit is reset. The flip-flop circuit 132 switches the astable Multivibrator 136 from as soon as the number in counter 124, 126 reaches 0. To do this, take two inverting amplifiers 14O and 142 a "down" output from the counting decades 124 and 126 and their combined output signals the flip-flop circuit 132 via an inverting Amplifier 144 returns when both counting decades 124 and 126 lead such a reverse output signal. The counter 124, 126, along with astable multivibrator 136 and associated circuitry, includes devices that respond to space characters of the keypad 10 respond and emit an output signal which corresponds to a permissible increase in the maximum extent for a single space.

The line length selected at the switches 58 is shown in the punched tape punched and fed to the setting machine. The keypad 10 has a button or a switch for this purpose which emits a line length character via a line 146. At the same time the key 78 or the line length character is actuated of the keypad 10 operated via an additional

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-Ip-

Liche line (not shown) the monovibrator 80th the memory counter 60 to 66 reads the line length character - before another character is entered on the keypad 10 - the line length from the switches 58 is re-entered.

The line length character operates via line 146 a trap circuit 148 which has a flip-flop circuit. Of the Lockout circuit 148 actuates a two-stage counter 150, the has two flip-flop circuits, which, according to the states of the counter stages, a series of inverted and not Output inverted output signals via lines 152. The output signals appear one after the other in four different ways Combinations on and operate successively NAND gates 154, 156, 158 and 160. The trap circuit 148 initially operates the Counter 150 and thus the NAND gate 154. The NAND gate switches via a line 155 and via the NAND gate 56 to the Clock signal generator 36 a. The clock signal generator 36 generates thereupon a series of output pulses which increment the division counter 86 and which the memory counter 60 to 66 count down from the value set via the switch 58 for the line length. The memory counter 60 to 66 is now counted down to 0. When the value reaches 0, give decades 60, 62, 64 and 66 via "reverse" signal outputs and inverting amplifiers 162, 164, 166 and 168 a common output signal on a line 170 from. The second stage of the division counter 86 shows a zero state also via an inverting amplifier 172 on line 170. The line 170 is one input with one NAND gate 174, while another input of NAND gate 174 is connected to the first stage of the division counter connected is. When both stages of the division counter 86 and all stages of the memory counter 60 to 66 count down to 0 NAND gate 174 outputs via line 176 an output signal. The output signal forms an input

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signal for a NOR gate 178. The NOR gate 178 then supplies an inverted by an amplifier 180 and through a combination of a resistor 182 and a capacitor 184, the output signal is somewhat delayed and switches the counter 150 to its next number. A suitable combination of output signals then switches via the Lines 152 turn NAND gate 154 off and NAND gate 156 a. As a result, the clock signal generator 36 is also switched off.

While the memory counter 60 to 66 is counting down, the first stage of the division counter 86 inputs via a line 186 Input signal to a binary counter with stages 18Θ, 190 and 192. The binary counter 188, 190, 192 is connected so that it counts purely in binary and not in binary coded decimal form. Output signals on output lines 194 are therefore one Binary representation of the line length, as previously contained in memory counters 60 to 66 in binary coded decimal form. if the memory counter 60 to 66 counts down, then the binary counter 188, 190, 192 counts the same value in binary representation upwards. During the counting, the blocking circuit 148 switches the binary stages 188, 190 and 192 via a line 196 a.

The input signals output from the first stage of the division counter 86 via the line 186 correspond to a number for half a unit. For each signal output to decade 60 via NAND gate 92, line 186 given two signals. The output lines 194 therefore carry binary values from 1/2 to 1024 starting from the bottom Binary values from 1/2 to 16 are supplied to NAND gates 198, while binary values from 32 to 1024 are supplied to NAND gates 200 will.

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When the counter 150 turns on the NAND gate 156 and turns off the NAND gate 154, the NAND gates 198 are turned on through a capacitor 202 and an inverting amplifier 20k . Output lines of NAND gates 198 then provide binary values between half a unit and 16 units. This first set of binary values is suitably fed to the paper tape punch via six lines and the paper tape punch can punch a first part of a line-length perforation in a row. The tape punch emits a signal via a line 206 when punching. This signal indicates that the tape punch has punched. The signal on line 206 turns on NOR gate 178 and advances counter 150 one step. This turns on NAND gate 158 and turns off NAND gates 154, 156, and 160. The NAND gates 200 are thus switched on via a capacitor 209 and an inverting amplifier 211. The tape punch now punches the higher-order binary digits. Once this has been done, the signal on line 206 advances counter 150 by a further step. The NAND gate 160 is now switched on and resets the trap circuit 148 via a capacitor 213. After resetting the binary counter 188, 190, 192 via the line 198, a cycle has been completed. The line length can now be read into the memory counter 60 to 66 again with the aid of the key 78 and the keypad 10 can be operated as usual to punch the information of a line to be printed in the tape of the tape punch.

In a number of cases it is desirable to have one already punched into the punched tape by the tape punch Word vein to delete a character again. The perforated tape decoration is for this purpose, as usual> rewound and it becomes

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punched all the holes in each of the rows containing the unwanted information. In this way, an undesirable Character or word by operating the tape punch backwards and by supplying an erase instruction the keypad 10. Unfortunately, this kind of behavior has a detrimental effect on the operation of the apparatus at Display the remaining line length or on the display showing an adjustable remaining line length. A circuit is therefore provided which corresponds to the number in the memory counter 60 to 66 for the remaining line length changes the deleted characters raid words. First, in particular with reference to FIG. 2, the deletion of a single character is intended explained.

A character counter includes binary counters 208 and 210 which are essentially are interconnected in the same way as the decades of the memory counter 60 to 66. The character counter 208, 210 works in binary and counts a lower digit in the binary counter 208 and a higher digit in the binary counter 210. The clock signal generator 36 supplies via a line 212 a count input signal for the character counter 208, 210. In the normal state, an inverting amplifier switches 216 a NAND gate 214, so that the character counter 208, 210 counts up when the memory counter 60 to 66 down counts. Since the inverting amplifier 216 is also connected to the NAND gate 92 via a line 218 and If this is switched on, the memory counter 60 to 66 »counts downwards in the normal state as described above. To this During the execution of a line, the character counter 208, 210 reads the incremental number for each character in quarter units a. Line 218 normally carries an on signal to a remaining input of NAND gate 56 to.

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Each time the tape punch 14 punches, a data execution signal emitted via a line 220 sets the Character counters 208, 210 back. The data execution signal on line 220 causes a negative going output signal an amplifying and pulse shaping circuit 222 which turns an output of a NAND gate 224 on and the character counter 208, 210 is reset via a line 226. The character counter 208, 210 is therefore normal deferred before counting the next character.

If the operator wants to remove a character, he first triggers a reverse function and the tape punch 14 emits a return signal on a line 230. That Return signal switches a flip-flop circuit having Lock-out circuit 232 on. The operator gives with With the help of the keypad 10, a code erasing signal as a code erasing instruction is sent via a line 228. The code clear signal on line 228 and an output of trap circuit 223 each go negative and produce a positive going Output pulse of a NOR gate 234, which is inverted by an inverting amplifier 236. From this it follows a signal going negative turns on a character erasure inhibitor circuit comprising a flip-flop circuit. The character erasure inhibitor circuit 236 outputs one of the signals for a NOR gate 240, the output of which if one is present such signal drops. An inverting amplifier 242 inverts this output signal and gives a positive going Signal on line 244 from. The signal going positive turns on a NAND gate 246 and, at the same time, the NAND gate 214 off. As long as the NAND gate 246 is switched on instead of the NAND gate 214, the character counter 208 counts, starting from the display of the character growth width stored here down to 0. The positive signal on the line 244, supplied to the NAND gate 90 in FIG. 2, switches it on, while the NAND gate 92 in FIG. 1 turns it on O signal df of line 218 switches off. The same 0 signal causes the clock signal generator 36 at the NAND gate 56

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emits a series of impulses, but the memory counter 60 to 66 upwards contrary to its normal working method counting. In this case, the NAND gate 90 is switched on instead of the NAND gate 92 and the operation of the Storage counter 60 to 66 is therefore reversed. When a normal character punched into the punched tape reduces the number in the memory counter 60 to 66 and thus the remainder of one Line is displayed, deleting such a character has the opposite effect on the stored number, that is, in this case the number stored and the display of the display device 18 increases. It is counted as long as until the character counter 208, 210 in FIG. 2 has counted to 0. This state is shown by two "reverse" input signals of the Binary counters 208 and 210 which are fed to a NOR gate 245. An output of the NOR gate 245 is through a inverting amplifier 248 inverts and resets the blocking circuit 238 via a line 250. As soon as the lock circle 238 is reset, line 244 is also normal. The memory counter 60 to 66 then counts up and the character counter 208, 210 counts down. After these successive operations are completed, operation can continue until an adjustable line is displayed. Each data character punched by the tape punch 14 sets the Trap circuit 232 via line 206 back.

When a word is erased, a counter with binary counters 252, 254 and 256 works in parallel with the operation of the character Counter 208, 210 and receives the same input signals as the character counter 208, 210. The binary counter However, counters 252, 254, 256 are reset not at the end of each character but at the end of each word. After every word the keypad 10 outputs a space signal on a line 258. The blank signal is negative and causes a positive output of a NAND gate 260, the

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resets the counter 252, 254, 256. The one for the blank displayed increase width becomes after a short delay in a delaying and pulse-shaping circuit Lines 264 are read into the binary counter from the binary counter 208, if the binary counter 252 via a line 266 a trigger pulse is applied. This becomes the number for the pad growth width read into counter 252, 254, 256 at the beginning of each word. This way, the space becomes on The beginning of the word is added to the word when the word is deleted and the memory counter 60 to 66 is counted up to the end of the previous one Word reset. The line end character represents both the character counter 208, 210 and via a line 280 also back the counter 252, 254, 256.

If a word is to be deleted, an additional counter (not shown) can be provided on the tape punch 14 be. This counter simply counts the number of characters in each word and is reset after each space. If the operator wants to delete a character automatically, he generates a code that the tape punch 14 to lets the number of punched rows shown by the counter run back and punches all of them in the area of the deleted word Holes. The same functions can of course also be performed by resetting the tape punch 14 and by punching all holes in the area of the word are made by hand. The additional, counter is not part of the present Invention.

With a word delete instruction, the operator gives the Keypad 10 sends a word erase signal to line 268. The word erase signal switches a word erasure lock circuit 270 with it a flip-flop circuit. An output of the word erasure inhibitor circuit 270 actuates NOR gate 240 as in the case of clearing

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of a character and thus prepares the counter 252, 254, 256 and the memory counter 60 to 66 for counting. The counter 252, 254, 256 and the memory counter 60 to 66 count in the opposite direction to the normal in this case. The character counter 208, 210 is reset via an amplifying and pulse shaping circuit 271 and the NAND gate 224. Furthermore, the signal on line 218 in turn switches on the clock signal generator 36. The counter 252, 254, 256 counts then down as the memory counter 60-66 counts up until the counter 252, 254, 256 reaches zero. One inverting each "Reverse" signals fed to amplifiers 272, 274, 276 generate an output signal at combined outputs, which via an inverting amplifier 278 den Word erasure inhibitor 270 resets. The memory counter 60 to 66 counts up to the end of the deleted word.

In the event that the operator write past the end of the line or specifies a line that cannot be set by the typesetting machine, the memory counter counts 60 through 66 through 0. This situation must generally be avoided and for this purpose a NAND gate is shown in FIG 282 provided. NAND gate 282 has an input on line 170 and takes the "reverse" signal similar signal from the second stage of the division counter 86 via the inverting amplifier 172. A second entrance of NAND gate 282 is the first with an output Stage of the division counter 86 connected. If the line is overdetermined, then the NAND gate 282 responds if a number is present, which is less than 0 in the line length minus the total stored growth widths. The NAND gate 282 indicates this via a display device 284. In addition, an output signal emitted via a line 286 blocks the keypad 10 and the tape punch 14. The character causing the character overflow and other characters

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can no longer use this line via the keypad 10 can be added. However, a new line can be started.

One of the switches 58 is shown in greater detail in FIG. The switch 58 has a plurality of mutually coupled Switching groups 310, 312, 314 and 316, their moving contacts are connected to inputs of the decade 66. Selected fixed contacts are connected to each other and to ground. In selected switch positions, inputs of the decade 66 are therefore switched to ground. The switch positions are selected so that the switching groups 310, 312, 314 and 316 send a binary coded input signal to the decade 66, the switching group 310 being assigned to the lowest digit. In a 0 position of the switch 58 connects none of the switching groups 310, 312, 314 and 316 have the inputs of the decade 66 with ground. In a "1" position connects the Switching group 310 a line with ground assigned to the lowest position. In position "2" the switching group connects 312 a line with ground, which is assigned to a second location. In a position "3" of the switch 58 both switch Switching groups 310 and 312 the lines connected to the decade 66 to ground. Switch 58 connects the inputs of the decades according to the binary code with ground. The physical one Formation of the switch 58 can be implemented in various ways.

When operating the adjustment device, the operator first selects the number of units per using the switch 58 Row. The number of units set for the line naturally depends on the intended column size and a point size of the letters. In a special embodiment the individual incremental unit is 1/18 of an em (1 em corresponds to 12 English-American points), i.e. 1 em has 18 Incremental units. The number 216 divided by the point

209884/0222

The size of the letters gives the units per pica, the point size being determined by the micro-memory 22. For the em per pica are set to a certain point size of the letters. The actual line length in picas per Row is determined by measuring with each pica equal to 4.25 mm. The number of units per line to be included in the Switches 58 is to be set, is calculated. It is the number of units per pica (for the special letter set) multiplied by the number of picas per line (which were measured). At 36 units per pica for 6-point letters and a column dimension of 18 picas, the number 36 χ 18 or 648 units must be set on switches 58.

An embodiment of the micro-memory 22 is shown in FIG. The micro-memory 22 has a word selection matrix which receives the character code via the lines 20 and then connects a selected line 290 through. In a typical embodiment, the word selection matrix 288 is in the form of a diode matrix which, in response to a given character code at the input, which consists of a combination of input signals on the input lines 20, selects one of the lines at the output. An additional input 318 switches between letters that correspond to an upper and a lower type case and a further input 320 selects between “magazines” of two type sets. The input code determines a line 290 at the output in a conventional manner via an EXCLUSIVE UWD link. The character codes for different characters and for the space each determine a different line 290. The word selection matrix 288 here determines one of the _{lines 290 labeled C 1} , C ₂ ... C _n at the output. The word selection matrix 288 addresses a memory matrix 292. The memory matrix 292 has transistors 294, 296... 298, whose base connections are each connected to one of the lines 290. Here

209884/0222

a separate transistor is connected for each of the 256 lines 290. Each transistor 294, 296 ... 298 is connected to and with a voltage source via a collector connection an emitter connection to a respective storage element 300, 302... 304. Each of these storage elements 300,. 302... 304 has a "programmable" fuse and is connected to a base of an output transistor 306. The base of the output transistor 306 is connected to an emitter of the transistor 306 via an input resistor 308 connected. The emitter of output transistor 306 is connected to a voltage source and the collector is on a line of lines 24, designated here by 24 ', is connected to the output. For each of lines 24 and 26 am A similar memory matrix 292 is provided at the output. In the illustrated memory array 292, create an existing one. Storage element 300, 302... 304 have an "0" output signal and a non-existent "1" output signal. Should for "programming" of the memory matrix 292 one of the memory elements 300, 302... 304 are removed, then, corresponding to a at the same time via the lines 20 supplied input code, an output terminal, which later a "1" output signal should lead, a certain negative current is supplied. This will put the circuit at the location of this output terminal connected storage element interrupted. This interruption corresponds in binary form to one digit of the supplied Character codes.

Each of the lines 290 is connected to corresponding transistors of each individual memory matrix 292, which is why to At the beginning of every output signal combination is possible. The micro memory 22 can of course be designed as an integrated circuit with 256 addressable lines 290 or it can have a plurality of smaller integrated memory circuits which are selectively controlled.

209884/0222

Claims (12)

Claims 1J adjusting device for displaying a remaining adjustable Line length when operating a typesetting machine, characterized in that a memory device (22) contains a code signal records for a character and emits a digital width signal for an increase in width of the character, that a memory counter (60 - 66) stores a digital value corresponding to the remaining line length, that an incremental width counter (28, 30, 36) receives the width signal of the memory device (22) and the value im Storage counter (60 - 66) changes according to the width signal and that a display device (18) displays the value in the memory counter (60-66). 2. Adjusting apparatus according to claim 1, characterized in that a register (106, 108, 110) permissible growth widths of Spaces characters in the line are summed up and a respective sum value of the permissible space expansion is stored that a comparator (98) compares the sum value of the register (106, 108, 110) with the value of the memory counter (60-66) and emits a signal when the value of the memory counter (60-66) is less than or equal to the sum value of the register (106, 108, 110), and that a display signal device (16) displays an adjustable line length in response to the signal. 3. Adjustment apparatus according to claim 1 or 2, characterized in that the incremental width counter (28, 30, 36) has a width signal receiving and storing as a number incremental counter (28, 30) and a clock signal to the incremental counter (28, 30) and to the Memory counter (60 -66) 209884/0222 Benden clock signal generator (36) and that the clock signals step by step the number stored in the incremental width counter (28, 30) and the stored in the storage counter (60 - 66) Increase the value step by step at the same time. 4. Adjusting apparatus according to claim 3, characterized in that the incremental width counter (28, 30) the digital width signal takes over in parallel from the storage device. 5. Adjusting apparatus according to one of the preceding claims, characterized in that the memory device (22) is programmable Have memory matrices (292) which, in response to an input code signal corresponding to the character, the digital Give a broad signal for the character. 6. Adjusting apparatus according to claim 5, characterized in that at least one of the programmable memory matrices (292) per Type set is programmed in such a way that it has a minimum growth width emits a corresponding digital broad signal. 7. Adjusting apparatus according to claim 5 or 6, characterized in that the memory matrix (292) has a plurality of programmable Storage elements (300, 302 ... 304), which are supplied by a control signal supplied to the storage element (300, 302 ... 304) are programmable. 8 * Adjustment apparatus according to claim 7, characterized in that the storage element (300, 302 ... 304) is a fuse and the control signal interrupts the fuse. 9. Adjusting apparatus according to one of the preceding claims, characterized in that a preselection switch (58) is a digital, signal corresponding to the maximum line length for 209884/0222 the setting of the memory counter (60 - 66) is transferred to it. 10. Adjusting apparatus according to one of the preceding claims, characterized in that a binary counter (188, 190, 192) the Clock signals of the clock signal generator (36) counts and thus contains a binary representation of the line length and that output gate circuits (198, 200) send the binary representation of the line length to the typesetting machine as line length information. 11. Adjusting apparatus according to one of the preceding claims, characterized in that a clear counter (208, 210, 252, 254, 256) simultaneously with the memory counter (60 - 66), corresponding to the clock signals of the clock generator (36), the growth width counts each character and / or the incremental width of each word and sets it back after each character or word, that a counter reversing device (238, 270, 240, 242, 246) at Erasing a character or word reverses a counting direction of the erase counter (208, 210, 252, 254, 256) until those stored therein The incremental widths of the character and / or the word have been deleted. 12. Adjusting apparatus according to one of the preceding claims, characterized in that the memory counter (60-66) is digital Stores decimal numbers. 09884/0222 al Blank page