DE2224829A1 - Method and device for generating time stamps with variable intervals - Google Patents

Description

File number of the applicant: SZ 971 002

Method and device for generating time stamps with variable intervals '

The invention relates to a method and a device for generating of time limits, the intervals of which from the preceding or following time stamps can be changed over time.

Devices for generating time stamps can be found in particular in
use of digital technology, namely wherever measured values
should be displayed digitally, such as in the digital measurement of noise levels with a display in decibels or from
Light (lux meter), and in digital tube voltmeters. Another area of application is the logarithmic analog / digital conversion, particularly in digital speech coding and in
Video technology is required.

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In contrast to time mark or zoit impulses in time measurement technology, where the greatest possible constancy of the intervals between adjacent time marks or pulses, even over very long time is important for the applications mentioned above the variability of these distances asked, being this variability admittedly usually has to follow a periodicity.

The older technology of time stamp generators with variable Timestamp intervals were based in particular on circuits in which the non-linearity of the diode characteristic was exploited. These However, circuits all have the disadvantage of temperature drift, since the diodes are extremely temperature-dependent. One has tries to remedy this disadvantage by installing the generators in thermostatically controlled ovens. However, it is obvious that the outlay on equipment is considerable.

The aim of the invention is therefore to provide a new method for producing of timestamp sequences with variable intervals as well as a generator for carrying out this method, which is largely temperature stable and with little circuitry the implementation of any pre-selected mathematical Laws variable intervals between successive

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Time stamps allowed.

The inventive method is characterized in that the value of the energy stored in an energy store with compared two different reference values and the comparison result a bistable circuit ■ is supplied, wherein the bistable circuit whenever the energy value matches and / or exceeds one of the reference values, is overturned in the other of its stable states, and that the characterizing the switching state of the bistable circuit Output signals of the same for controlling at least one energy source connected to the energy store "is used".

An apparatus for carrying out the method according to the invention is characterized by an energy store and at least one energy source that can be connected to the energy store, two comparators for comparing the value of the energy stored in the energy store with two of the comparators individually associated, different reference quantities and by a bistable trigger circuit connected to the comparator, the with the time mark output and with the control input of one of the Energy source associated switch is connected.

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Details of the invention are set out in the following description of a Exemplary embodiments are explained with reference to the drawings. Show it·:

1 to 3 different waveforms of the reference voltage and the associated time mark pulse sequences;

4 shows a basic circuit diagram of the time mark generator;

Fig. 5 unsynmetric charge and discharge currents and the to

associated timestamp pulse train;

Fig. 6 is a circuit diagram of an exponential time stamp gene

rators

7 schematically shows a delta encoder

8 is a block diagram of a delta encoder.

The principle of the method according to the invention is based on comparison the energy stored in an energy store, e.g. a capacitor, with two different reference values and by reversing the energy supplied to the energy store as a function of the comparison result. The first is the Reference values are defined as the lower threshold, the second as the upper threshold. If energy is therefore continuously supplied to the energy store, so their value will eventually reach the upper threshold,

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whereby the reversal of the energy source takes place in the sense, that the energy storage device is discharged again until the lower threshold is reached (and possibly exceeded) whereupon the charge starts again.

In this way, the amount of energy constantly oscillates back and forth between the two limits. In the case of the capacitor as energy storage and two, for example, constant reference voltages, the terminal voltage on the capacitor would essentially, " Triangular in shape with the bases more consecutive Triangles would be the same length and the triangles would be congruent.

It is an essential feature of the present invention that only one of the reference quantities is constant while the other is variable as a function of time. If the second reference variable is, for example, linear over time increasing voltage (sawtooth voltage), the terminal voltage at the capacitor is again triangular, where however, increase the lengths of the bases of successive triangles by a fixed percentage (based on the preceding Base length), since the heights of the triangles become larger due to the constantly increasing upper threshold value.

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The triangles are therefore no longer congruent, as with awei constant Reference values, just similar. The base lengths of consecutive Triangles form a geonic series, and the time increase in the distances between the same reference points is successive Triangles is exponential.

As mentioned, the comparison result of a bistable circuit is supplied, which provides a constant output signal for each of its switching states, wherein a condition once ingested stored ■ ** is, until the opposite threshold value is reached.

For most applications of the time stamp generator, the pattern it generates must be periodically repetitive. It is obvious to use the period of the sampling interval as a basis, if the application involves an analog / digital converter or similar acts. An external frequency can of course also be used. . ·,

Fig. 1 shows the sawtooth envelope (V), the course of the associated terminal voltage on the capacitor (V ^- .) And the output signal of the time mark generator (E). FIGS. 2 and 3 show examples of non-linear envelopes and the associated terminal voltages and

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Output signals. In all cases there is an increase in the distances

* clearly visible between adjacent output pulses.

In FIG. 2, the increase does not take place until the end of the cycle, while in FIG. 3, where it is an RC charging, the increase takes place according to an exponential function, with increasing stabilization of the distances towards the end of each cycle. The time mark generator according to the invention can relate to the increase or decrease in the intervals between the pulses due to the corresponding distortion of the sawtooth voltage can be adapted to practically any application by means of a non-linear element.

4 shows a basic circuit diagram of the inventive device Time stamp generator. Basically, the circuit shown is a special multivibrator, the eich distinguishes itself from many others in that it has only one ■ Has capacity. In general, capacitively coupled multi vibrators have two capacities, from which the special one The disadvantage is that they do not start to oscillate automatically under certain conditions; they must therefore be initiated externally will. With only one capacity, as here, the multivibrator must start up under all starting conditions.

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Two current sources 11 and 12 are connected to a capacitor C and supply currents 21 and I, respectively. The current flow direction is determined in such a way that the current I flows continuously from the capacitor C., while the current 21 _{flows into the capacitor C when the switch S 1 is} closed, so that the resulting current, depending on the position of the switch S, either +1 or -I is.

The currents of the current sources 11 and 12 do not have to be have a ratio of 2: 1. For example, they can also be the same size, in which case both must be switched over,,

or unequal, i.e. asymmetrical, with different Rising and trailing edge steepnesses of the charging and discharging currents result.

The charging or discharging of the capacitor C. is terminated in each case, when the capacitor voltage reaches an upper or lower limit value. These limit values are represented by reference voltages, with which the voltage on capacitor C is continuously compared. The lower limit is at the one to be described Embodiment set to 0 volts. The other, upper limit, corresponds to the instantaneous value of a periodically variable

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Voltage V (t). This voltage V can, as mentioned, a Be the sawtooth voltage, which consists of a current source 13 and a capacitor C consisting of a current I. Sawtooth generator is generated with a reset mechanism.

The comparison of the voltage on the capacitor C. with the reference voltages takes place by means of two comparators 14 and 15. These comparators each have two inputs, those shown in FIG "+" and "-" are designated. The "I" input of the comparator 14 and the "-" input of the comparator 15 are connected to the capacitor C. connected, while the relevant reference voltages are fed to the other two inputs of the comparators. The exits the comparators 14 and 15 are connected to a bistable multivibrator (hereinafter referred to as memory cell 16), which consists of two NAND gates 17 and 18 consists. Each of the NAND gates has two inputs, one of which is connected to the output of the associated comparator 14 or 15 is connected, while the second input is connected to the output of the other NAND gate.

Taking into account the fact that the AND condition at the input has to be met, the function explained below results for the memory cell 16.

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The comparators 14 and 15 are connected in such a way that they have a negative Supply output voltage when the limit value assigned to them is reached or exceeded. Because the comparators against each other work, they can never deliver a negative output signal at the same time.

The following linking tables can be set up for the NAND elements 17 and 18, with the inputs and outputs according to FIG with the letters A to D are:

Link table 1 B. C. Link table 2 D. B. NAND element 17 0 1 NAND element 18 0 1 A. 0 1 C. 0 1 0 1 1 0 1 . 1 1 1 0 1 1 0 0 0 1 1

Provided that the comparator is a logical one Value "0" supplies the corresponding output signal (A = 0) because the If the threshold value assigned to it is reached, it must be assumed that the comparator 14 has a logic value "1" output signal occurs (D = 1). From link table 1 it follows that if A = 0 i st, then C = I always applies; from the link table

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it can be seen that with C · - 1 and D = I the output B of the NAND gate 18 must deliver the signal O, and that is also in Correspondence with the first line of the link table 1.

Because of the known switching characteristics, the comparator remains the same this state is maintained until the 0 volt threshold of the comparator 14 is actually reached. The comparator then delivers a negative signal to the D input of the NAND gate 18 (D = O). As a result, the output B of the NAND element 18 must supply a logical "1" (link table 2). With A = I the exit takes place C of the NAND gate 17 to the logical value "O" (Table 1). In the meantime the signal at the input D of the NAND gate 18 has disappeared (D = 1). It follows from link table 2 that B = I remains, and from 'the first, while C = O. That is again in accordance with link table 2.

The output signal from the NAND element 18 (see also E in FIGS. 1, 2, 3) is used to switch S to operate, which controls the charging or discharging of the capacitor C by the current sources U and 12. As mentioned earlier, will discharge the capacitor C with the switch S open with dpm current I; When the switch S is closed, the current 21-1 = 41 flows into the

«■

Capacitor C.

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In all cases where the reference voltage is V, be it periodic or aperiodically, be brought back to an initial value it should be noted that this initial word is not 0 volts should, since then the change between charging and discharging the capacitor C would have to take place at an infinitely high frequency, what is of course undesirable. In Fig. 4 switches S and S are shown

Ct J

with the help of which the discharge of the capacitor C (V. = 0 volts) and the resetting of the reference voltage V _? takes place at its initial value. The switches S and S can be operated, for example, with the clock frequency or the sampling frequency. If the time stamp generator is used for speech coding, the use of the 64 kHz sampling frequency is recommended. While the capacitor C. is completely discharged at the end of each sampling interval, since the switch S_ short-circuits it, the voltage V_ is only reduced to the bias voltage V applied to the switch S, the magnitude of which is, for example, 5 ... 10 % of the maximum amplitude of the Voltage V_ can be.

If the charging and discharging currents of the capacitor are equal, then there is a triangular shape for the capacitor voltage, where all triangles are similar because their heights and base lengths are always in the same proportion to each other. A triangle with the peak voltage V.

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corresponds to a complete pulse of the output signal at point 19. Since these are isosceles triangles, the impulse roof and the impulse gap of an impulse are of the same length.

This does not apply if the charging and discharging currents are unequal (I £ ^ -J) The triangles of the capacitor voltage are then not isosceles, so that the top and bottom of the pulse are no longer the same length for a single pulse. An example with a higher charging than discharging current is shown in FIG.

The mathematical law according to which the distances between successive Increasing or decreasing pulses is determined by the curve shape of the reference voltage V_. An exponential one As mentioned, the increase occurs with a (periodically) linearly increasing reference voltage. Other non-linear laws of increase can be achieved by suitable transformation of the curve shape by switching on a non-linear element 20 in the line 21. Such a non-linear element can be a field effect transistor (with a square characteristic) a diode (with an exponential or logarithmic characteristic) or other active or passive elements or combinations of such elements.

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6 shows a simplified circuit diagram of a time mark generator that works with increasing spacing the method according to the invention carries out. The StroinqueJle 11 4 is formed by a PNP transistor 43 and a resistor 32. The current source 12 comprises an NPN transistor and a resistor 34. In the embodiment shown here, the ratio of the Strchnc is 2: 1 in favor of the power source The comparators 14 and 15 of FIG. 4 are designed as pairs of transistors 35, 36 and 37, 38, respectively. The memory cell 16 has the Transistors 39 and 40 on; their mode of operation is not self-evident and therefore needs to be explained briefly.

If the voltage V. on the capacitor C. has values above 0 volts, the transistor 35 conducts. If the voltage V goes to 0 volts, then the transistor transistor 36 becomes increasingly conductive, until the total current is 0 volts is evenly distributed over the transistors 35 and 36. At values below 0 volts, the current is more and more displaced into the right branch, i.e. the transistor 36 is more conductive than the transistor Since the collector current of the transistor 36 flows through the resistors and 42, the voltage drop occurring across them causes that the base of the transistor 39 becomes negative, whereby the transistor 39 is blocked. Hence, the current is in the right branch

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displaced with the transistor 40, i.e. this becomes conductive. Through this but if the voltage drop across resistor 42 becomes even greater, so that the voltage at the base of transistor 39 decreases further.

At the same time, the voltage at the base of the transistor 43, ^ decreases bo that it becomes conductive, i.e. the switch S is closed, and the capacitor C is charged again. The memory cell 16, however, retains its state. The voltage V increases until the Comparator 15 responds. As soon as the voltage V becomes more positive than V, it starts the current through the transistor 37 to flow and the current flow through the transistor 38 decreases until it is finally complete stops. This means that the memory cell 16 is also de-energized since the common Emitter line 44 of transistors 39 and 40 'is connected to the collector of transistor 38.

The current consumed by the memory cell 16 had previously flowed through the transistor 40 and had a resistor 42 Voltage drop caused. The decrease in the current flow through the resistor 42 therefore causes a potential increase on the Line 45 and via the resistor 41 also at the base of the transistor 39 · until finally the potential at the base of the transistor 39 exceeds the fixed potential at the base of transistor 40.

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This makes the transistor 39 more conductive than the transistor 40, whereby the voltage drop across resistor 42 is further reduced and the base of transistor 39 smells more positive. The , Memory cell 16 has thus overturned into its second stable state.

Since the voltage across capacitor C is positive, so is the base of the transistor 35 is positive and the comparator 14 conducts on its left path, which means that the currentless Transistor 36 at resistors 41 and 42 no voltage drop can cause.

As a result of the increase in potential on line 45, the base of transistor 43 is also more positive than the base of the transistor The transistor 43 is therefore blocked (S opens) and switches the Current +21 from capacitor C. As a result, the " Capacitor is discharged through the current -I and the transistor 37 carries less current, since its base becomes more negative. It takes place thus finally again a diversion of the current to the right path of the comparator 15, so that the memory cell 16 again receives full power.

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In summary, you can use this unconventional type of control Describe a bistable circuit in such a way that the tipping over into one position by basic control, into the other position by control of the entire current flow through the circuit.

The output signal appearing on line 45 (point 19 in FIG. 4) of the time mark generator can be taken via an impedance converter 57 which has the transistors 46 and 47. The impedance converter is necessary because the line 45 / die as a control line is used, is relatively high resistance and can therefore not be loaded.

The variable reference voltage V is in the embodiment of FIG. 4 shows a sawtooth voltage that is generated by charging and discharging by means of a current source comprising a transistor 48 and a resistor 49 a capacitor C is generated. Connected to this sawtooth generator is a reset circuit which is fed into an · input terminal 50 fed clock pulses is controlled. The clock pulses are sent via two diodes 51 and 52 to the base connections two transistors 53- and 54 are supplied, thereby saturating them to be driven. The transistor 54 switches on the capacitor C via a line 55 connected to its collector Ground, i.e. the capacitor C is completely discharged with each clock pulse.

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. The collector of transistor 53 is via a line 56 to the Capacitor C connected. Its emitter gets a little bias V, the size of which is e.g. 5 ... 10% of the amplitude the sawtooth voltage can be. To this bias, the capacitor C is discharged with each clock pulse. Through this what is achieved is that the bistable circuit forming the memory cell 16 does not initially have to switch infinitely quickly.

From a functional point of view, the sawtooth generator 48, 49, C, 53 a voltage that increases linearly from a bias voltage to a maximum value, which increases with the clock frequency (or sampling frequency) is periodic.

The time mark generator of FIG. 6 can be used, for example, in an adaptive delta coder. Become a delta encoder often used in the coding of speech in order to convert it into analog Form to convert voice signal into a digital signal for the purpose of transmission. This technique is familiar to the person skilled in the art and is therefore not to be explained in more detail. The adaptive delta encoder chooses even its step size depending on the current analog signal. This adjustment is done indirectly by determining like the sequences of digital information generated by the encoder

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are made. This can be deduced from the lengths of the sequences whether the steps are correct or too small or too ' were chosen large, and in which direction one possibly required change. the step size has to be done. However, the adjustment of the slufen size will not work for every small one Deviation carried out, but only if there is a deviation over a preselectable number of sampling intervals persists in one direction. This deviation manifests itself in a sequence of constant binary values. the The maximum length of the sequence that can still be tolerated is, as mentioned, preselectable and depends on which coding noise is still in Purchase can be made.

The simplest delta encoder is a feedback system in which the feedback signal is quantized in amplitude and time. It it is therefore about periodic in a fixed sampling interval Pulses, whereby the amplitude quantization can assume the values +1 and -1. The impulses are integrated, which is the simplest In the case of an integrator, it is generally done in a linear network. Fig. 7 shows schematically a delta encoder, the one Differential amplifier 60, a limiter 61, a switch 62 and a feedback network 63 comprises. It is the

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Special case of a servo system in which the switch 62 is in time the sampling frequency is operated.

Fig. 8 shows the block diagram of a delta-coder used by makes use of the ZeilTaarkcn generator according to the invention. The voice signal fed into an input 72 is fed to a comparator 71. The comparator 71 acts as a quantizer; it is connected to a flip-flop 73, in which the sampling takes place in that its input is always open, except when the clock signal is also present. With the output of the flip-flop 73 are a sequence analyzer 74 and an integrator network tied together. A flip-flop 76 connected to a diode network is intended for the determination of the absolute amount of the charge Q flowing into the integrator 75, i.e. for the determination the step size. The charge is the product of electricity and Time; the current is limited in this circuit by a current limiter diode 78. By switching the other diodes accordingly it is achieved that a single current limiter diode is sufficient for positive and negative currents, the current always in the same Direction is flowed through. Therefore the current surges (+ or -) are practically always the same size.

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The signal appearing at the output 79 of the flip-flop 73 is through an inverter 80 is performed. It determines the sign of the current flowing into the integrator 75. The duration of the current flow is determined by the switch-on duration of the flip-flop 76. When the flip-flop 76 is switched off, the current flows into a shunt.

The time stamp generator 31 is both connected to the sequence analyzer as well as connected to the flip-flop 76. It is determined by the sampling clock signal controlled. '

The digital output signal occurring at the output of the flip-flop 73 of the delta encoder is running through the sequence analyzer 74, i.e. at the cycle time, monitored by the sequence of O-. and 1- binary values are checked. A detector contained in the sequence analyzer counts the same binary values in a sequence and initiates one Counting the counter to a higher or lower value if the sequences of the same binary values exceed or exceed a specified value. fall below. The over or Falling below the counter range prevented. The counter keeps a record of the step size in binary form (in db).

For a delta encoder with a reasonable dynamic range

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has a compression ratio (i.e. ratio of the greeted for the smallest step size of 24 db has been shown to be favorable. The difference between neighboring pin sizes should not be 2 dB exceed. That means that the coder has thirteen positives for each and must be able to generate negative levels of a preselectable size.

This can be achieved by using the Zcitmtrkcn generator can carry out 25 charge changes within each sampling interval and, for example, the beginning of a charging process in each case used as a time stamp. The resulting intervals grow exponentially over time.

The currently effective step size is determined by means of a in the sequence analyzer 74 contained in the comparator to the determined sequence of the same binary values in relation and by means of the comparison result the step size is reduced, kept or increased.

As already mentioned, the step size corresponds to that in the integrator flowing charge Q; this is the product of the constant current I through the current limiter diode 78 and the time in which

Approx

he flows.

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The time interval for the current flow is set by switching on the Flip-flops 76 determined. The output signal of the integrator 75 is fed to the comparator 71 and from this with then Input speech signal compared.

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Claims (15)

- 24 - PATE NTAN S CHALLENGES Method for generating time stamps with mutual spacing which can be varied according to a preselected law, characterized in that the value of the energy stored in an energy store (Cj) is compared with two different reference values (Vq, V2) and the comparison result is fed to a bistable circuit (16) , whereby.die bistable circuit (16) is overturned in the other of its stable states when the energy value corresponds to one of the reference variables (Vq, V ₂ ) and / or exceeds it, and that the switching state of the bistable circuit (16 ) characterizing output signal of the same for controlling at least one energy source (11, 12) connected to the energy store (Cj) is used. 2. The method according to claim 1, characterized in that the first reference variable (Vq) is a constant voltage, the second reference variable (V ₂ ) is a time-variable voltage j st. 3. The method according to claim 2, characterized in that the time-variable voltage (V ₂ ) has a sawtooth-shaped curve. 4. The method according to claim 1, characterized in that a current source is provided whose current flow direction through the Output signals of the bistable circuit (16) is alternated. sz 9 71 ου.? 2 09851/110 1 5. The method according to claim 1, characterized in that two current sources (11, 12) are provided, of which the first (12) is firmly connected to the energy store (C ₁ ) while . the second by the output signals of the bistable circuit (16) is switched on and off. 6. The method according to claim 5, characterized in that the first current source (12) the current -I, the second current source (11) supplies the current +21. 7. The method according to claim 2, characterized in that the time-variable voltage (V2) one by the transfer function a non-linear element (20) has a certain curve shape. 8. The method according to claim 1, characterized in that the energy store (C ₁ ) is periodically discharged and that the second reference _{variable (V 0} ) is periodically returned to an initial value (V3). 9. The method according to claim 2, characterized in that the variable Reference variable (V2) and the energy supplied by the energy source (11, 12) are set so that the intervals successive time stamps increase exponentially. sz 971 002 209851/1181 10. Apparatus for carrying out the method according to claim 1, characterized by an energy store (Ci) and at least one energy source that can be connected to the energy store (Cj) (11, 12), two comparators (14, 15) for comparing the value of the energy stored in the energy store (C ^) with two the comparators (14, 15) individually assigned, different reference variables (Vq, V2) and by one to the comparators (14, 15) connected bistable flip-flop circuit (16), which with the time mark output (E) and with the control input (F) of a the energy source (11, 12) associated switch (S.) ver; is bound. 11. The device according to claim 10, characterized in that the reference variable (Vq) is the mass potential and that for generating the other reference variable (V2) is a sawtooth generator (SG) is provided. 12. The device according to claim 11, characterized in that the sawtooth generator is followed by a non-linear element (20) is. 13. The device according to claim 10, characterized in that the bistable trigger circuit (16) consists of two NAND gates (17, 13) consists, whose output (B, C) is connected to one of the inputs of the other NAND gate, during each other input (A, D) of the NAND gliders (17, 18) to the output 209851/1181 output of their individually assigned comparator (14 or 15) is connected. 14. Apparatus according to claim 10, characterized in that two equally large, oppositely polarized current sources (11, 12) are provided, which are alternatively connected to the energy store (C ₁ ) _{via the switch (S 1).} 15. The device according to claim 10, characterized in that two unequally large, oppositely polarized current sources (11 _f . 12) are provided, one of which (12) constantly, the other via the switch (S ₁ ) to the energy store (C ₁ ) is connected. 7 0 M ti ü 1/1 1 UI Blank page