DE2223487A1 - PROCEDURE AND ARRANGEMENT FOR DIGITAL CONTROL OF OPERATING FUNCTIONS, PREFERABLY IN RADIO AND TELEVISION SETS - Google Patents

Description

Method and arrangement for the digital control of operating functions, preferably in radio and television sets The invention relates to methods and arrangements for digital control of operating functions using current or voltage levels, preferably in radio and television sets, especially according to patent ....... (patent application P 21 38 876, W. Schröder-46).

There are already electronic information stores known under other r also for storing voltage values for step-by-step regulation of operating functions in radio and television sets (see e.g. German Patent specification 1 059 508, SEL Reg. io 471, w. Schröder-7). According to this patent specification is also the application of "multiple arrangements, of bistable flip-flop stages" known (see e.g.

Column 1, line 15). In addition, it has already been mentioned (column 8, Line 35) that the said information memory four to five flip-flop StuSen can replace.

An economical solution already proposed is to that the stages in one direction one after the other by \ up counting pulses at the counting input a digital counting circuit or a digital information memory and via the same counter input in the same direction (cycle) a burst of (N-1) pulses are delayed one step at a time, with N is the total number of counting steps of a complete counting cycle (patent application P 21 38 876, W. Schröder-46).

After further explanations of this mentioned proposal are under other arrangements for generating the (N-1) countdown burst are also described and its feeding into the counting input of a counting chain, so that the counting chain each independent operating function thereby receives two counter inputs: one for the Infeed of a single impulse for each forward step of the operating function and another for injecting an (N-1) burst for each backward step the operating function.

Previously it was used to remotely control the operating functions of radio and televisions it is common to assign each operating function its own control frequency. With the predominantly common ultrasonic remote controls, every operating function has a function their own ultrasonic frequency.

The disadvantage of this method is the extensive technical effort the necessary adjustment of these frequencies, the same on the ultrasound transmitter, such as must also be carried out on the ultrasound receiver. Since you have the forward and backward controls each must count as a separate function are used for remote control of color television receivers for example, at least eight different control frequencies are required. Disadvantageous it is also that such arrangements are not easily integrated into technology Circuits can run because of the required inductances and some of the larger capacities have not yet been integrated.

The invention is based on the problem of methods and arrangements for digital control for operating functions by means of current or voltage levels indicate that do not have the disadvantages mentioned.

It has already been proposed (patent application P 21 49 519, W. Schröder-47), for each of several operating functions to be activated one per to generate a coded number of pulses as a command signal and for each new operating step to repeat this command signal over a common transmission link to send, to save temporarily, to decode and to trigger the digital To use the operating signal.

With acoustically transmitted command impulses in the ultrasound range the pulse modulation by echo signals, which is inevitable in normal living spaces are significantly disturbed. In such cases it is again advantageous as command signals to use different unmodulated frequencies. It is beneficial in this case To use command signal generators that can be switched to different frequencies. The command signal generator can, for example, correspond to one that has already been proposed Circuit (patent application P 22 17 124, Wo Schröder-48) be constructed in such a way that the touchable electrodes or their subsequent circuitry with a electrical matrix circuit consisting of a diode gate, and, the diode combination is connected in a manner known per se in such a way that Frequencies, modulations, pulses and / or capacitors, resistors and / or coils can be added to coded command signals that can only be touched by one Electrode or simultaneous contact with its counter electrode triggered The electrical signals of the command signal generator are an electroacoustic one Transducer, preferably an ultrasonic transducer, for acoustic radiation or a light source, e.g. also an infrared source.

The invention is based on the object for such command signal generators to create a command signal receiver, in which you can switch to different frequencies with just one adjustment process.

This object is achieved according to the invention in that the command signal receiver contains a receiving circuit, which is digital with an electronically circulating Switch one after the other to all command frequencies or their converted frequencies is switched so that the increased at resonance with the received command frequency Resonant circuit voltage is fed to an amplitude filter after rectification, if necessary, that the output of the amplitude filter via the electronically rotating switch is connected directly or indirectly to the signal outputs one after the other, which are assigned to the command frequencies, and that the signal outputs each with are connected to the inputs of the circuits, which in particular according to patent application P 21 38 876, W. Schröder-46, trigger the assigned digital operating functions.

The tuning of the receiving circuit can be done by means of a capacitance diode take place whose reverse voltage or forward current with a (e.g. known) staircase voltage generator is controlled. A more precise coordination can thereby be achieved in accordance with the invention that additional capacitors have electronic switches parallel to the basic capacitance of the receiving circuit can be switched.

According to one embodiment of the invention, the parallel connection or a respective combination of capacitors according to a binary system by putting in parallel to the basic capacity of the receiving circuit for 2n different command frequencies only n additional capacitors are switched, the next smaller capacitance of which in each case half the size of the next larger one, that n electronic switches in series with the n additional capacitors lie and that the electronic switches each of be switched to another output of an n-stage binary divider whose Control frequency has 2n times the output clock frequency.

According to another embodiment of the invention, the reception a command signal triggered clock signals of the electronically rotating switch or the binary divider is fed to a divider or counter, at the output of which a slow clock signal for triggering the operating functions is taken.

Another embodiment of the invention is that the control oscillator emits a higher control frequency than twice the control frequency for the electronically circulating switch is required, preferably 2tn + m) times, where n and m are integers and greater than zero and between the control generator and the electronically rotating switch or the n-step binary divider, the the n electronic switches of the n additional capacitors switches, further divider stages are arranged, which shorter pulses than the clock pulses in certain phase positions can be removed. The shorter pulses in certain phase positions are for example used as pre- and post-pulses for pulse regeneration of the received signal.

Digital remote control circuits are generally designed to that the time selected service cycle is given automatically in the receiving part, as long as a command signal is broadcast. About delays in tripping To keep the first operating step as small as possible, it is advisable to use the Cycle of the electronically rotating switch for switching the receiving frequency to select much faster than the cycle for triggering an operating function, practically between half a second and a second for each change step an operating function is running. This makes it possible to trigger a first Change level of an operating function within a cycle for the electronic to reach circumferential switch. If for extraction a slower one Operating clock from the faster circulation frequency in the receiver a counter is used it should not be able to be influenced by reception disturbances.

The reception disturbances include, above all, amplitude drops due to room reflections during acoustic transmission in the ultrasonic range.

Therefore, another embodiment of the invention is that a multi-stage, in particular binary coded counter receives its first counting pulse from the command signal received via the output switched through by the electronically rotating switch and a first individual switching (e.g. OR gate).

after the first counting step with the help of the potential change to the Outputs of the counter is blocked, and that all further counting steps via a second input circuit (e.g.

NOR gate) are triggered by an independent pulse train, and that the second input circuit at the end of each counting cycle from the change in potential the outputs of the counter is blocked.

The advantages achieved with the invention are in particular: that the receiver circuit allows greater tolerances of the components, that further the adjustment work is minimal and the troubleshooting is clear. In addition, lets the circuit largely integrate. Another great advantage is that that the output signals to trigger the digital operating functions the timing of the electronic switching is already pulse-modulated and easy can be prepared for the digital control circuits of the operating functions. In addition, the pulse series used are phase-locked to one another. A disturbance reflections in the room are effectively prevented.

Embodiments of the invention are shown in the drawings and described in more detail below. Show it Figure la to Figure lc, the function symbols used per se of the digital areas, Figure 2 a schematically greatly simplified circuit to explain the basic principle of the invention Figure 3 diagrams to explain the operation of the circuit Dargesi1lten in Figure 2 Figure 4 the control circuit for frequency shift keying and for the signal distribution, FIG. 5 a detail of FIG. 4, FIG. 6 and FIG. 8 further diagrams to explain the mode of operation of the arrangements shown in FIG. 2 to FIG Leading pulses (V pulses) with the associated diagrams shown in FIG. 11; FIG. 11 shows a circuit for generating the V "pulses with the associated diagrams shown in FIG. 12.

For a better understanding of the description, some of the follow The descriptions and functional symbols of digital technology used in the explanations defined in advance.

The flip-flop elements shown as boxes in the drawings for counter and divider circuits correspond to one in the practical circuit used version (e.g. known under the designation SAJ 110). Just a positive one A change in voltage at the input, which is designated with L ("high"), changes the switching state at the output of the flip-flops from (zero, 1, low? 1) to L and vice versa. Are in a Flip-flop chain circuit set all outputs to 8, causing an L signal at the input of the chain switching all outputs from to L.

An output of the flip-flop, which is set to L, can be directly at this output with a short pulse from L to implement. Mostly will for this purpose a transistor is used (npn), whose collector with the flip-flop output and whose emitter is connected to the ground potential (=). An L pulse at the base sets the flip-flop output on.

Signals, e.g. E, F, G, which must also be used inverted, are denoted by E, F, G. For the function of the l'Oder "gate (Figure la) apply the following relationships: Table 1 Inputs Output E1 E2 A # # # L # L L L L L L Just if the inputs are set to at the same time, a signal occurs at the output.

For the "NOR" gate (= "OR" circuit) with subsequent negation Figure 1b) applies: Table 2 Inputs Output E1 E2 A L L L L L Only if the inputs are set to at the same time, an L signal occurs at the output.

The inverter (Figure 1c) corresponds to a simple phase inversion stage (Negation) and contains the t'negation point ": Table 3 Input Output E A L L In order to avoid confusion, the inputs and outputs of the function characters shown not indicated by other letters in the drawings.

The supply voltage of the ultrasonic remote control receiver and the associated circuitry is stabilized at 10 V.

All pulse voltages between # and L are around 8 to 10 volts peak voltage.

After this clarification of the terms used, the following now follows Functional description of the ultrasonic operating receiver, and Although initially the basic mode of operation of the digital shown in Figure 2 scanned receiver.

The digitally scanning receiver The static ultrasonic microphone 1 in Figure 2 is polarized with a DC voltage of approximately -250 V and supplies the received command signals to the input of the four-stage transistor amplifier 2, which amplifies and limits the sinusoidal input voltages so that at his Output square-wave pulses of approx. 10 V are emitted. The impulses become capacitive fed into the resonance circuit L1 / Co, which has a fundamental frequency of about 45 kHz is balanced. The capacitors C1, C2 and C3 tune the resonance circuit cyclically to seven additional reception frequencies between 44; and 35 kHz off by it be connected electronically in parallel in different combinations in a periodic cycle. A frequency shift keying cycle lasts approximately 80 ms, with each of the eight receive frequencies is held for approx. 10 ms.

The diode Dl ri shows the received, selected in the resonance circuit Command signal is the same. When viewed over the time axis, one of the Selection of the resonance circuit corresponding step-shaped amplitude curve with a phase position dependent on the transmitted command frequency, a period of 80 ms and a stair step width of 10 ms. U2 in Figure 3 represents the oscillogram an amplitude curve, in which in this case the command signal is in the Phase position 5 'is in resonance with the receiving circuit. Overall are accordingly of the capacitor combinations eight different phase positions 1 '... 8' possible, with which depending on the reception or. Command frequency a maximum of the staircase curve arises, as soon as there is a resonance between the receive and transmit frequency.

The following amplitude sieve 3 in FIG. 2 cuts out the highest stair step and inverts it as AS signal (amplitude sieve signal) is available for further evaluation (e.g. at the D; odengatter). The AS signal has one of the eight possible phase positions that are assigned to a specific receive or transmit frequency within a keying cycle. The AS signal, which is inverted in comparison to 5 'of the stepped curve U2, is shown in FIG. 3 in the phase position 5'.

Next is the control circuit for the receive frequency shift keying or for switching the capacitors and for signal distribution.

The multivibrator 4 in Figure 4 provides the input of the 6-membered binary flip-flop divider chain 5 to 10 with 1600 Hz square pulses of approx. 10 V. The last output of the chain then reaches as a result of the continuous frequency division the keying frequency of 12.5 Hz. The outputs of the last three divider flip-flops 8 ', 9 and 10, supply the square-wave pulses E, F and via the inverters 11, 12 and 13 G, which via electronic switches the capacitors C1, C2 and C3 to the receiving circuit connect in parallel.

The structure of an electronic switch can be seen in Figure 5: The Capacitor C1 is connected to the resonance circuit L1 / Co via the anti-parallel connection of the transistor T1 and the diode D2.

When the base of the transistor T1 is open, the diode D2 directs the oscillation voltage of the resonance circuit and generates a reverse voltage itself. There too Transistor is blocked, the capacitor Cl remains disconnected from the resonance circuit.

Only when the L phase of the square wave voltage E has a base current in T1 feeds, T1 is for the positive phase and D2 for the negative phase of the oscillation voltage conductive at the resonance circuit, and the capacitor C1 is thus parallel to the resonance circuit switched.

The same applies to the parallel connection of capacitors C2 and C3 by the square-wave voltages F and G, the electronic Switches are constructed analogously to FIG.

This describes the switching states of the capacitors C1, C2 and C3 Diagram shown in Figure 6 with the help of the square-wave voltages E, F and G, the depending on the different division, double the pulse length of the previous one Have voltage: Table 4 E controls C1 = 800 pF F "C2 = 1600 pF = 2 Cl C3 = 3200 pF = 2 C2 The phase positions are designated (as in Figure 3) with 1 '... 8' and the switching states with = capacitor switched off and L = capacitor connected in parallel.

From this it follows, depending on the phase position and the result of E, F, d resulted in a combination of capacities a table 5 for the calculation of the resulting parallel additional capacities (see FIG. 6) and taking into account of the values given in Table 4: Table 5 Phase position as per 2 '3' 4 '5' 6 '7' 8 ' Switching) C1 L L L L) state C2 # # L L # #) of) C3 # # # # L L L L resulting Parallel capacitance 0 80o 1600 2400 3200 4000 4800 5600 pF A part of the outputs of the control circuit shown in Figure 4 also controls the inputs of the diode gate 14 shown in Figure 7 are synchronous with the eight phase positions the eight outputs a to h in FIG. 7 of the diode gate 14 are also switched. To the Inputs of the diode gate 14 are in addition to the inverted output signals E, F and G also the direct output signals E, F and G of the divider stages 8, 9 and 10. In this form, the diode gate acts as an OR circuit (see Table 1). Only if at all associated diode inputs of the diode gate 14 at the same time A signal is present, the associated output also emits a signal. The diagrams of Figure 8 (see Figure 6 with non-inverted signals) make it clear that this state for each output with a different one of the eight phase positions 1 '... 8' occurs, as described in Table 6, in which the switched Frequencies or capacities (Tables 4 and 5) are given: Table 6 Phase State additional reception function position (from Fig. 8) capacitance frequency (table 5) (at 8800 pF = C0) 1 'É F G O pF, 45.00 kHz a Power On (N) Off 2' E F G 800 pF + 43.08 kHz b Volume + (L) 3 'E F G 1600 pF 41.39 kHz c Volume -4' E F G 2400 pF 39.89 kHz d Brightness + (H) 5 'E F G 3200 pF 38.54 kHz e Brightness -6' E F G 4000 pF 37.31 kHz f color saturation + (F) 7 'E F G 4800 pF 36.20 kHz g color saturation -8' E F G 5600 pF 35.18 abbreviated h program selection (P) The respective horizontal rows correspond here the table of the respective horizontal rows of the diode gate 14.

The selected assignment of the receive and command frequency is from the table to the output a to h of the diode gate and the operating function connected there recognizable, which are switched on cyclically, but only if an associated one is available Command signal or an AS pulse of the appropriate phase position is switched through will. So that the diode gate 14 only emits a pulse to the output if whose assigned command frequency is sent and received are all Outputs in addition to the diodes belonging to E, F, G and E, F, G via others diodes belonging to R and V "with one of those of the two inputs of the diode gate 14 connected to which the V ?? - and the R signal are fed to that in turn Among other things, as will be described, it depends on the AS pulse of the command signals are. These two signals only occur simultaneously with the already known AS signal on, but are prepared in a special way to ensure a slower operating cycle and a forward (V) and backward (R) control of the operating registers and the To enable operating functions. As long as the V "or R pulses are missing, stay all outputs of the diode gate 14 blocked. The derivation of these impulses will explained below.

One of the prerequisites for this is the V-pulse, which is also used for switching the mains on and off 16 is required in front of the power switch relay 17 in FIG. 18, 20, 22, 24 are inverters.

Generation of the V-pulse The V-pulse is a regenerated AS-pulse, by which it is also triggered with a period of 80 ms. Since the AS pulse is off a rectified RF signal obtained via a subsequent low-pass circuit there is a delay in this signal compared to the control signals, which open and close the diode gate 14 for the associated outputs. The delay causes an interfering pulse at the output that is switched cyclically afterwards. The glitch becomes thereby suppresses that the V-pulse compared to the "preparation signal" begins delayed by approx. 1.25 ms, but ends with it.

These impulses are referred to as "preparation signals "5 which from the square pulses E, E, F, F, G and G according to FIG. 8 in each of the Phase positions 1 '... 8' are generated in the diode gate 14 with a pulse width of approx. 10 ms and each output of the gate one after the other for opening by a V "- or prepare R-pulse The V-pulse arises at the output of the flip-flop 28 in FIG 9 as a pulse. It is initiated by the pre-pulse B C D, which consists of the divider flip-flops 5, 6 and 7 and the inverters 26 and 27 in Figure 4 is obtained. From the figure 10 it can be seen that the pulses B, C and D only in the phase position 2 ?? simultaneously Reach the position, at the output of the OR gate 31 in Figure 9 at its inputs these pulses lie, the pre-pulse B C D (see FIGS. 9 and 10) arises. He sets with the help of the transistor T4 the output of the flip-flop 28 only then in the position, if an AS signal occurs at the same time at the second input of the NQR-Gattieræ 32, So the command signal generator is actuated by us4.

The V-pulse begins 1.25 ms after the start of the period (see bottom diagram of Figure 10) 8.75 ms later, at the end of the old one and at the beginning the new period are generated by the divider flip-flops 5, 6 and 7 via the inverters 25, 26 and 27 and the OR gate 29, the post-pulse B C D. This post-pulse is also in phase position 1? each period at the first input of the NOR gate 30, however, remains ineffective as long as the output of the flip-flop 28 remains in the L state and with this potential at the second input of the NOR gate 30 ensures that none L pulse from NOR gate output delivered to the flip-flop input can be. However, after the pre-pulse previously the position of the two possible states at the output of the flip-flop hergestelit and thus the V-pulse has started, can the after-pulse B C D switch the flip-flop output back to the L position and thus terminate the V pulse (Figure 9 and Figure 10).

The generation of the V "pulse from the V pulse The V" pulse is identical in duration, phase position and polarity to the V-pulse. Its repetition rate on the other hand is only about a 7th of the 12.5 Hz frequency of the V-pulse.

It causes the successive ones in this cycle with an interval of approx. 0.56 s Change steps of the function registers in the forward direction. It corresponds to his Phase position 1 '... 8' of the assignment of the frequency emitted by the command signal.

By the V-pulse to a 7th of its original repetition rate to slow down, a three-stage binary pause counter 37, 38, 39 (Figure 11) used. Its first counting step starts with the trailing edge of the differentiated at C4 / R1 V pulse. Output a controls the remaining seven counting steps (Figures 11 and Figure 7) of the diode gate 14 with its E F G pulse in the phase position 1 '. This As already mentioned, pulse is used for the mains on-off switch and here is also used for a phase generation that is insensitive to interference and thus solves the initially described sub-task in a simple way.

The E F G pulse occurs periodically without interruption even without receiving a command signal in the phase position 1 'according to Figure 6 or

Figure 8. By counting on independently of the received signals after the start, not only is the desired immunity to faults achieved, but also the most favorable starting position prepared for new command signals. Since the first generated V-pulse at the same time as the generation of the V '' pulse is used, the waiting time is from the receipt of the command to the reaction of a function register or the program selector a maximum of 70 ms.

The OR gate fed by the three flip-flop outputs 33, 34 and 35 40 gives the start pulse for the at the second input of the NOR gate 36 in FIG first counting step only free if all counting outputs are in position. After the first counting step, the gate 36 is immediately blocked again because the seven next counting positions at the output of the OR gate 40 generate the L state, its inversion, however, in the inverter 37, the NOR gate 58 for further counting the next seven E F G pulses (from output a of diode gate 14, Figure 7, 8 and 11). After these pulses complete the counting cycle up to the position continue control, in which all counting outputs have the position again, the counter is idle until a new start impulse arrives.

Figure 12 shows the most important signals of the circuit of Figure 11, which occur there after triggering a V-pulse train at a command frequency, which in this example is assigned to the phase position 5 '. (The phase position 5 'of the in the first row of the diagram, Figure 12, corresponds to the V-pulse shown Center (5 '') of that shown in the last row of Figure 10, on a different scale V-pulse shown). From the differentiated pulse train Vdiff (second row Figure 12) is at the input of the counting flip-flop stage 36 only the first differentiated and again inverted pulse V1diff effective in period 1+. In the next Periods 2 + ... 7+ solve it by the inverted B C D pulses B C D (cf. also Figure 10) in the phase position 1 '. In period 8+ begins with the next triggered pulse Vldiff a new counting cycle.

The signal V 'taken at the output of the OR gate 40 only has during the seven counts led by the G F G pulses triggered become, L potential. That is in the counting pauses and during the first V-pulse Potential. The merging of the V and V 'signals at the inputs of the OR gate 41 generates the V "signal at the output of the gate with the mandatory pause of almost seven 80 ms periods.

Generation of the R-pulse The function registers are used for reverse control the register uses an (N-1) burst, as explained in more detail at the beginning (cf. also patent application P 21 38 876, W. Schröder-46), which is referred to here as an R signal is. N is the possible number of change steps in a register.

The function registers are designed for eight changeable levels each, which are set with simple impulses in the forward direction. For every step backwards A 7-fold burst must then be available.

The 7-fold burst R is easily generated with the OR gate 42 generated according to Figure 13, the first input to the output A of the 1600 Hz multivibrator 4 is connected according to Figure 4, and the second input receives V ″ pulses. the end For the reasons explained earlier, the V '' pulse is opposite the preparation signals a to h shorter by an 8th. Each V ″ pulse is therefore at the output of the OR gate 42 modulated with just seven square wave changes of the A signal. The resulting 7-fold burst R supplies the three 1? Backward" -Inputs of function registers 19, 21 and 23.

8 claims 7 sheets of drawings

Claims (8)

Method for the digital control of operating functions by means of current or voltage levels, preferably in radio and television sets, especially according to patent ...... (Patent application P 21 38 876, W. Schröder-46), characterized in that that the command signal receiver contains a receiving circuit (L1, CO) which is digital with an electronically rotating switch (Figures 4, 5 and 7) one after the other all command frequencies or their converted frequencies are switched over, that the increased resonant circuit voltage in the event of resonance with the received command frequency possibly -after rectification an amplitude filter (3) is fed that the output of the amplitude sieve (3) indirectly or via the electronically rotating switch is connected directly to the signal outputs (a to h) one after the other, which the Command frequencies are assigned, and that the signal outputs each with the inputs (N, L, H, F, P) of the circuits are connected, which (in particular - according to patent application P 21 38 876, W. Schröder-46) trigger the assigned digital operating functions. 2. command signal receiver according to claim 1, characterized in that that the receiving circuit (L1 / Co) is tuned by means of a capacitance diode, whose Reverse voltage or forward current is controlled with a staircase voltage generator. 3. command signal receiver according to claim 1, characterized in that that additional capacitors (C1, C2, C3) via electronic switches (T1, D2) in parallel to the basic capacity of the receiving circuit (L1 / C0). 4. command signal receiver according to claim 1 and 2, characterized in that that parallel to the basic capacity (L1 / Co) of the receiving group only n additional capacitors (cit, C2, C3) switched for 2n different command frequencies whose next smaller capacity is half the size of the next larger that n electronic switches (T1, D2) in series with the n additional capacitors lie and that the electronic switch each from a different output of one n-level binary divider can be switched, the control frequency of which is 2n times of the output clock frequency. 5. command signal receiver according to claim 4, characterized in that that the in series with the additional capacitors (C1, C2, C3) lying electronic Switch each consisting of an anti-parallel connection of a transistor (T1) with a diode (D2) are formed and the circuit is connected to the resonance circuit (L1, C) in this way and is dimensioned so that the diode (D2) in the phase the oscillation voltage of the Rectifies the resonance circuit (L1, Co) and generates a reverse voltage for itself, while the control voltage in the base of the transistor (T1) during the conductive Phase (L-phase) feeds a current, so that the transistor (T1) for the positive Phase and the diode (D2) for the negative phase of the oscillation voltage on the resonance circuit becomes conductive and switches the capacitor parallel to the resonant circuit (L1, 0o. 6. command signal receiver according to one of the preceding claims, characterized in that the triggered by the receipt of a command signal Clock signals of the electronically rotating switch or the binary divider Divider or counter are fed, at the output of a slower clock signal to trigger the operating functions. 7. command signal receiver according to one of the preceding claims, characterized in that the control frequency output by the control oscillator is higher is than 2n times the control frequency for the electronically rotating switch is required, preferably 2 (n + m) times, where n and m are integers and larger as zero and between the control generator and the electronically circulating Switch or the n-level binary divider that controls the n electronic switches n additional capacitors are switched, further divider stages are arranged, which shorter ones Pulses are taken as the clock pulses in certain phase positions. 8. Command signal receiver according to one of the preceding claims, characterized in that to obtain the operating clock, a multi-stage, in particular binary-coded counter receives its first counting pulse from the received command signal via the output switched through by the electronically rotating switch and a first input circuit (in particular OR gate), after the first counting / step is blocked with the help of the potential change at the outputs of the counter, and that all further counting steps via a second input circuit (in particular NOR gate) are triggered by an independent pulse train, and that the second input circuit at the end every count cycle is blocked by the potential change at the outputs of the counter.