DE2216062A1 - Monolithically integrated memory circuit with insulating layer field effect transistors - Google Patents

Description

Monolithic integrated memory circuit with insulating film field effect transistors' - ■ ''

The invention relates to a monolithically integrated memory circuit with insulating film field effect transistors as storage transistors and as load elements of these memory transistors, for the field effect transistors serving as load elements an insulating layer, which is thicker than the memory transistors, is provided in the gate or channel area.

For reasons of their relatively high possible packing density as well their regularly relatively low power loss compared to bipolar memory circuits can be found in so-called unipolar technology, d. H. monolithic memory circuits constructed with field effect transistors a widespread application. In such memory arrangements, the actual memory cell is often in the Form of the known flip-flop circuit with directly cross-coupled Field effect transistors built. It is also known to take place in the load branches of the cross-coupled memory transistors customary diffused resistors serving as load element field effect transistors to be provided (e.g. Electronics, February 16

209844/1056

1970, page 109). These measures brought the advantage that now the load elements with the actual storage transistors could also be produced in a uniform manner. Based on these uniform production of all field effect transistors, d. H. both the memory and the load transistors, however such load elements have an insulating layer that is equally thin in comparison to the memory transistors in the respective gate area on. In order to be able to influence the resistance value of these load elements, in particular in the sense of a desirable increase In order to achieve an overall low power loss, the field effect transistors serving as load elements had to when they are designed in monolithic form, relatively elongated narrow channel areas are provided (Electronics, loc. cit.). Such a design has the disadvantage of requiring a large, undesirable semiconductor surface area, which in turn is unfavorable affects the desired packing density.

US Pat. No. 3,530,443 also discloses a memory cell known with field effect transistors, in the comparison for the field effect transistors serving as load elements to the memory transistors thicker insulating layer in their Gatebzw. Channel range is selected. While this is the above disadvantageous large semiconductor area requirement avoided, but there is now the risk of conductive parasitic field effect transistor structures .

If, for example, one chooses for the field effect transistors serving as load elements, their gate insulating layer thickness is the same as that for the rest of the semiconductor surface with the exception of the gate regions the insulating layer selected for the memory transistors, it is no longer guaranteed that any parasitic field effect transistor structures, z. B. in areas with a ladder routing, safely stay off. It should be noted that the as Field effect transistors serving load elements must be switchable.

Docket FI 970 101 2 0 9 8 44/1056

221C062

The object of the invention is to provide those with insulating layer field effect transistors to improve built monolithically integrated memory circuits so that with guaranteed Switchability of the field effect transistors with a thick gate oxide in areas with an insulating layer of the same thickness are parasitic Field effect transistor structures remain safely switched off.

Proceeding from a monolithically integrated memory circuit of the type indicated above, the invention is characterized in that, in order to avoid conductive parasitic field effect transistor structures, over a metallization, e.g. B. from
Conductor lines covered selective doping areas in the semiconductor body with an insulating layer of the same thickness as the gate areas of the field effect transistors serving as load elements for the
parasitic field effect transistor structures a higher threshold voltage is forced in comparison to the load elements. In
advantageous embodiment of the invention is provided that the
higher threshold voltage V by defining the operating voltage values using the relationship

t ^v S Sub

with V _c as the source voltage and V ″, as the substrate voltage, is forced in such a way that the source voltage of the parasitic structure is higher than the source voltage of the switchable field effect transistors serving as load elements. This advantageously makes use of the fact that the threshold voltage is influenced not only by the thickness of the insulating layer over the channel regions, but also, inter alia, by the voltage difference between the source connection and the semiconductor substrate. In order to avoid the disadvantageous state that such parasitic field effect transistor structures become current-carrying, the degree of freedom of the remains
selectable source voltage of these parasitic structures.

Docket FI 970 101 20 9844/105

The invention is described below on the basis of an exemplary embodiment explained in more detail with the aid of the drawings.

Show it:

1 shows the electrical circuit diagram of a memory cell,

to which the invention can be applied;

Fig. 2 is a plan view of the in a monolithic

Integrated memory cell and

3 shows the manner in which a plurality of memory cells are arranged on the semiconductor die are.

The reference numerals 11 and 12 in FIGS. 1 and 2 denote a pair of field effect transistors with corresponding source terminals 13 and 14, which are connected to the ground line 15. The field effect transistors 11 and 12 continue to have Drain connections 16, 17 and gate connections 18 and 19. The drain terminal 16 of the field effect transistor 11 is via the line 20 is connected to the gate terminal 19 of the field effect transistor 12. There is an electrical connection in a corresponding manner via the line 21 between the drain terminal 17 of the field effect transistor 12 to the gate terminal 18 of the field effect transistor 11, whereby a known directly cross-coupled Circuit arrangement arises.

With 22 and 23 are the load elements of this circuit in general denotes, of which each load element is equipped with a source connection 24, 25, each with the drain connections 16, 17 of the field effect transistors 11 and 12, respectively. The load elements 22 and 23 also have drain connections 26 and 27 and gate connections 28 and 29, respectively. The drain connections 26, 27 are connected to the drain voltage line 30.

Docket Fi 970 ιοί 209844/1056

mm, t ^ mm

'With the reference numeral 31 is generally a parasitic field effect transistor with a source connection 32 connected to the drain connections 26 and 27 of the load elements 22 and 23. The drain connection 33 of the parasitic field effect transistor 31 is connected to the line 34, via the line 34 and the line 36 'branched off therefrom becomes the gate voltage for the load elements 22 and 23 supplied. The gate terminal 35 'of the parasitic field effect transistor 31 is connected to the line 36'.

With the reference numerals 35 and 36 are the input-Z output transistors denotes the memory cell, which is connected via the connections 37, 38 to the bit lines 39, 40 and via the connections 41, 42 to the drain connections 16, 17 of the field effect transistors 11 and 12 are connected. The gate connections 43 and 44 of the field effect transistors 35 and 36 are also coupled to word line 47 via lines 45 and 46.

The reference numerals 28, 49 to 53 in Fig. 2 denote corresponding ones Contact holes that extend from the associated diffusion areas below to the metallization above extend. The detail shown in FIG. 2 is closed several times in the larger detail view according to FIG. 3 recognize.

The mode of operation of the memory cell will be explained below. The field effect transistors 11 and 12 constitute a flip-flop circuit one transistor is energized while the other is switched off. The drain of the each conductive transistor is then at a relatively low potential, while the drain terminal of the switched off Transistor is at a relatively high potential. Via corresponding pulses on the bit lines 39, 40 can the flip-flop circuit in one of the two states described

Docket Fi 970 ιοί 209844/1056

be switched. For example, if it is desired that the flip-flop circuit is in a state in which the drain terminal 16 is at a high potential and the drain terminal 17 is at a relatively low potential, a relative high potential can be applied to the bit line 39 and a relatively low potential to the bit line 40. To get that out To finally switch the field effect transistors 11, 12 existing flip-flops into this state, the potential of the word line must 47 are raised. Once the memory transistors are in the desired state, this state remains without any further Maintaining the voltage conditions on word line 47 exist.

The channel region of the parasitic field effect transistor 31 as well as the field effect transistors 22 serving as load elements, 23 is formed below a silicon oxide layer with a thickness on the order of about 5000 Å, which insulating layer is thus about ten times thicker than that over the channel regions of the field effect transistors 11, 12 forming the flip-flop circuit and the field effect transistors 35, 36. Since the conductivity of a field effect transistor is inversely proportional to Oxide layer thickness over the respective channel area behaves, the load elements 22 and 23 have a relatively high resistance value on. On the other hand, this means that only a relatively small current flows through the field effect transistors which are the load elements 22, 23 and thus through the flip-flop transistors 11 and 12 flows. However, this fact is very beneficial because it results in a significantly reduced power loss.

Due to the relatively thick oxide, the threshold voltage of the parasitic field effect transistor 31 is still relatively high, whereby this is supported in maintaining its switched-off state. The thick oxide supports this property, is not sufficient on its own. After all, the load elements have to be on the other side

Docket Fi 970 ιοί 20 9 84 WI 056

mm. * 7 mm,

22, 23, which also have the thick oxide over their channel areas are covered, be switchable. However, the threshold voltage of the parasitic transistor 31 is set to as follows described manner compared to the corresponding threshold voltage, voltage of the load elements 22, 23 also increased considerably. The value for the threshold voltage is calculated as the root value of the voltage difference between source and substrate. Since the voltage at the source terminal 32 of the parasitic field effect transistor 31 is relatively high, so is the voltage between source and substrate and thus the threshold voltage of the parasitic Transistor 31 higher than that of the load transistors 22 and

23. Due to its higher threshold voltage, the parasitic field effect transistor 31 is thus switched off keep.

According to the invention, the (source) voltage is at the source terminal 32 of the parasitic field effect transistor 31 to be selected higher than the source voltages at the terminals 24 and 25 of the load elements Serving field effect transistors 22 and 23 respectively and the source voltage increases the threshold voltage of the parasitic field effect transistor 31 and thus becomes conductive prevented. In addition, due to the same measure according to the invention, there is an increase in the source voltage at the connection 32 that in the parasitic field effect transistor 31 the voltage value that is decisive for the setting of a conductive channel, namely, the difference between the gate voltage and the source voltage is also decreased. Because the parasitic field effect transistor structure 31 and the field effect transistors 22 and 23 serving as load elements with one another with respect to their gate connection are connected, the parasitic field effect transistor has not only a higher threshold voltage, as mentioned, but also a lower one acting in the same direction voltage difference between its gate and source potential.

Docket FI 970 101 209844/1056

Thus, with guaranteed switchability, the is used as load elements Serving field effect transistors for any parasitic field effect transistors equipped with the same insulating layer thickness that they are permanently switched off.

Docket FI 970 101 20984 4/1056

Claims (4)

PATENT CLAIMS Monolithically integrated memory circuit with insulating film field effect transistors as memory transistors and as load elements of these memory transistors, wherein for the field effect transistors serving as load elements an insulating layer, which is thicker than the memory transistors, is provided in their gate or channel region is, characterized in that to avoid conductive parasitic field effect transistor structures over from metallization, e.g. B. covered by conductor tracks with selective doping areas in the semiconductor body equally thick insulating layer as the gate areas of the field effect transistors serving as load elements for the parasitic field effect transistor structures have a higher threshold voltage compared to the load elements is forced. 2. Monolithically integrated memory circuit according to claim 1, characterized in that the higher threshold voltage V by defining the operating voltage values using the relationship V _t -V Vg - V _Sub with V _q as the source voltage and V ". is forced as a substrate voltage, such that the source voltage of the parasitic structure is higher than the source voltage of the switchable field effect transistors serving as load elements. 3. Monolithically integrated memory circuit according to claims 1 or 2, characterized in that the parasitic field effect transistor structure in addition Docket FI 970 101 209844/1056 in addition to its increased threshold voltage, a reduced differential voltage acting in the same direction between has its gate and source connection. 4. Monolithically integrated memory circuit according to one of the preceding claims, characterized in that the Memory transistors (11, 12) directly with respect to their gate and drain connections (18, 19; 16, 17) in a known manner are cross-coupled that in the drain or load branch of the memory transistors one each as a load element (22; 23) serving further field effect transistor is switched on, the gate or drain connections (28, 29; 26, 27) each with one another and with an operating voltage line (36 · and 34 and 30) are connected, and that the field effect transistors serving as load elements are a compared to the memory transistors have significantly thicker, in particular approximately ten times thicker gate insulating layer. DocKet Fi 970 101 209844/1056 A4 Blank page