DE2158522A1 - Electronically controlled clock, in particular wristwatch - Google Patents

Description

Electronically controlled clock, in particular wristwatch

The invention relates to an electronically controlled watch, in particular a wrist watch, with a particularly one Oscillating crystal having normal frequency oscillator, one consisting of several stages, preferably below Using complementary symmetrical metal oxide semiconductors created frequency divider circuit and an the digital display device connected to the stages, which is equipped in particular with liquid crystal elements.

It has proven to be extraordinary in the past proved difficult to provide watches of the aforementioned type with a time setting or time correction device, which is only approximately as inexpensive and especially easy to handle as it is with comparable ones Facilities of conventional mechanical clocks is the case, The setting of clocks of the type mentioned is therefore mostly reserved for a person skilled in the art, facilities for Adjustments by a layperson are not intended.

With the invention, a watch of the type mentioned be provided with a time setting or time correction device, which allows a corresponding adjustment of the Time display to be carried out easily and accurately by anyone permitted, whereby such a watch should be practical and convenient to use.

209824/0951

Dipl .-! Ng. Heinz Lesser, patent attorney D - 8 mouths 81. Cosimastrofce 8! Telephone (0811) 483820

According to the invention, this is achieved in that, in addition to a first reset switch, with the help of which all frequency divider stages can be reset at the same time Another reset switch is provided, which is only connected to the reset input of the first, the smallest digital Display value upstream frequency divider stage is connected.

While the reset switch, with the help of which all frequency divider stages can be reset at the same time, enables the general resetting of the time display, for example, to We * zero and thus synchronizes the frequency divider stages, the second, only the switch assigned to the first frequency divider stage to carry out a time correction in the smallest order of magnitude. Slight deviations, for whatever reason, can therefore be easily addressed by the User of the watch can be corrected at any time. This first frequency divider stage is therefore connected downstream of the oscillator and is upstream of the smallest display value of the time display. This can be a seconds display or else also be a minute display, depending on how finely divided the time display is provided.

In a particularly preferred embodiment of the invention, however, not only the first, but also further ones are on it The following and preferably all frequency divider stages have their own reset switches, which can be operated independently of one another, so that several or all of the display values can be set individually. Such Equipping the watch is particularly advantageous in the case of repairs, maintenance and the like, if by appropriate Work on the clock setting the individual frequency divider stages, at least in part as binary counters are formed, are no longer adapted to one another.

Dipl.-Ing. Heinz lesset, patent attorney D - 8 Munich 81. Cosimajtrafce 81 Telephone: (0811) 483820

The invention is explained in more detail below with reference to the exemplary embodiment shown in the drawing. Show it:

Fig. 1 is a block diagram of an embodiment of a clock equipped according to the invention;

Fig. 2 shows an inverter from complementarily symmetrical Metal oxide semiconductors;

3 shows an amplitude counter which is made using complementarily symmetrical metal oxide semiconductors is made.

For reasons of space, FIG. 1 is divided into two partial representations, the lines a to f of the upper part of the picture ending on the right must be thought of as being connected to the lines of the same name beginning on the left of the lower part of the picture. As a time standard, a crystal resonator X is used whose frequency is ⁿ Hz is generally 2, can therefore be TELLEN low. The * output signal of this crystal oscillator is amplified and reversed in phase with the help of an inverter and then fed to an amplitude counter 1, which can be constructed as a ring counter or shift register (ripple carry counter) and has complementary symmetrical metal oxide semiconductors (abbreviated: COS / MOS).

FIG. 2 shows a basic component of the circuit according to FIG. 1, specifically in connection between the circuit diagram of the inverter from complementarily symmetrical Metal oxide semiconductors and their input and output waveforms.

FIG. 3 shows the state of an amplitude binary counter and its input and output signal forms. The counter starts counting when the reset terminal R is low and it is reset, as soon as R shows a high potential.

20982 4/0951

Dipl.-Ing. Heinz Lesser, patent attorney D -8 Munich 81, Cosimastrafce 81 Telephone: (0811) 483820.

The counter denoted by 1 in FIG. 1 has a capacity of η-steps and gives a 1-second-signal at its output from which of the next frequency divider stage is supplied via the output Q. Stage 2 has a decade counter and a segment decoder and creates a 10-second signal from the 1-second signal. At the same time, a signal is rectified which is fed to the one-second display on the art display area 7 will. (Line f). Levels 3 and 5 house frequency divider circuits with a division ratio of 1: 6 and corresponding decoders to display the tens of seconds and to be able to operate the tens-minute display. Level 4, on the other hand, has a decade counter and a Decoder for the one-minute display, while level 6 has a frequency divider circuit with the divider ratio 1: 24 and a decoder that is assigned to the two-digit hour display. The respective outputs for The setting of the value display are shown in FIG. 1 with the aid of dashed arrow lines with regard to their assignment indexed.

The resetting of the individual counters or frequency divider stages, i.e.. the time setting or correction, now proceeds as follows:

If the switch S _{1 is} switched on, the reset inputs R of all stages 1 to 6 are reset via a diode and inverter. Therefore, if the switch S _{1 is operated} between its on and off position, the clock can be used as a stopwatch. However, if the clock is intended for normal use, it can only be set to zero or zero once a day _{with the aid of switch S 1.} 24-hour display can be set. However, such an adjustment option alone is not reasonable. For this reason, a second switch S is provided according to the invention, with the aid of which stage 1 can be reset independently of the other stages. To this

209824/0951

Dipl.-Ing. Heinz Lesser, patent attorney D - 8 Munich 8Ί, Cosimastrafce 81 Telephone: (0811) 483820

The time display can be set to the correct time at will, that is, the switch S ₂ enables the time display to be corrected at any point in time.

In the event that the display device only allows the display of hours and minutes, the switch can

5 _{2 are designed} for resetting stages 1, 2 and 3; in this way one achieves the possibility of a time correction every minute. An advantageous addition to this time correction option is the switch

5 ₃ to S-, which are assigned to the frequency divider stages in accordance with the block diagram according to FIG. 1, are provided. The function will be explained using the example of switch S- Since the direct current component of the output signal is blocked by the capacitor C ^, the input of the inverter that drives stage 2 is through the resistor R _{1 held} at a low potential V ₅₅ . If the switch S _{3 is} actuated, the input signal of the inverter causes a signal to the reversing circuit of stage 2 for each switching on and off; in this way the correspondingly assigned numerical display can be corrected.

In the same way, each display unit can be used individually Can be influenced with the help of switches S. to S-; these

4 /

Correction can be done quickly and precisely at the beginning of operation or even when the electrical energy source is switched on if the report is far outside the relevant range, can be carried out.

20982 4/0951

Claims (1)

Dipl.-Ina. Heinz Lesser, patent attorney D - 8 Munich 81. CosimastroRe 81 Telephone (0811) 4838 20 PATENT CLAIMS Electronically controlled clock, in particular wristwatch, with a normal frequency oscillator, in particular having a vibrating crystal, a frequency divider circuit consisting of several stages, preferably created using complementary symmetrical metal oxide semiconductors, and a digital display device connected to the stages, which is in particular equipped with liquid crystal elements, characterized in that In addition to a first reset switch (S.), with the help of which all frequency divider stages (1 to 6) can be reset at the same time, a further reset switch (S ₂ ) is provided, which is only connected to the reset input (R) of the first frequency divider stage preceding the smallest digital display value (1) is connected. Clock according to Claim 1, characterized in that the reset inputs (R) of the frequency divider stages of several, preferably all, display values (lsec, lOsec, 1min, lOmln, lh) can be controlled independently of one another. 20982 4/0951 Blank page