DE2150853C3 - Division device for a serial four-species arithmetic unit - Google Patents

Description

The invention relates to a division device for a serial four-species arithmetic unit according to the preamble of claim 1.

A well-known decimal multiplier (see DD-PS 30 925) is provided: with a computing device for the cross-multiplication of multi-digit numbers and for the addition of the Part products,

with operand registers for receiving the numbers to be processed and

with a switching unit containing a counter for entering the operands into the arithmetic unit by digit.

in any case, this should at least mean subtgraction and Division cannot be performed.

In contrast, it is the object of the invention, based on this prior art, as it is by the DD-PS 30 925 given and in the preamble of claim 1 with respect to the circuit Training is specified to create a division device for a serial four-species arithmetic unit, so that this can be carried out in a simple manner, that is to say with as few additional devices as possible, division and, if necessary, also subtraction.

This object is achieved according to the invention by the teaching according to the characterizing part of the Claim 1.

In this way, the Divisiöns-Algöfithmüs specified in the preamble of claim 1 (not yet known) is implemented.

It is particularly advantageous that the result register, which is already present, is used to record the respective trial quotient is used, which after completion of the trial division cycles in a correspondingly corrected form represents the real quotient.

While so far in the implementation of the division

The divisor was repeatedly subtracted from the total dividend until the correct quotient was reached, according to the invention, the subtraction is made from a part of the dividend, namely that beginning with the highest digit and with a number of digits corresponding to that of the divisor, the subtrahend being indicated by a cross Multiplication is the product of the trial quotient digit and the divisor is In successive cycles, the trial quotient and the partial dividend are then successively increased by one digit per cycle until the entire dividend has been processed

Advantageous refinements of the invention are specified in the subclaims.

Of particular interest is the teaching according to claim 4, since two complement formers are then provided in the addition device, which together with the rest of the arithmetic unit allow an elegant implementation of the subtraction because, during in addition, the two complement formers do not take the places of the first or second summand complement, when subtracting in the first step, the one complementing element leaves the minuend unchanged while the other complementer complements the subtrahend, which company the both complementers is also retained in the second step of subtraction, if the minuend is further greater than the subtrahend while when the minuend becomes smaller in comparison to The first-mentioned complementary subtracts and the other complementary complements then no longer complemented

In contrast, it has so far only become known (see. DE-OS 19 56 209, p. 18, para. 3), for Difference formation between two operands to change these within the arithmetic unit, if the subtraction results in a negative value without this having been implemented more precisely in terms of the circuitry.

The division device according to the invention is suitable particularly suitable for simple digital computers, e.g. B. as a process computer, but also od for tabulating and accounting machines, cash registers.

The division device according to the invention is on an application example in an electronic keyboard calculator that works with up to eight-digit decimal numbers in the binary-decimal system, explained in more detail with reference to the drawing. It shows

F i g. 1 is a block diagram of the computer which has a serial four-species arithmetic unit and

Fig.2 an execution example of the used Division algorithm.

However, the arithmetic unit shown can be used in its unchanged form for processing numbers Number of digits and can be used in any place value system and in a wide variety of codes.

The computer contains a serial four-species arithmetic logic unit I, consisting of a multiplier 2 for single-digit numbers, an addition device 3, a switching unit 4, a first gate group S, a second gate group 6 and a third gate group 7 of input gates (eder- Gates) and a gate group 8 of output gates of the arithmetic unit 1.

The computer also contains: an input unit 9, a control unit 10, a first operand register 11, a Second operand register 12 and a result register 13.

The input unit 9 h? » a numeric keypad 14, a Onerationsart keyboard 15 and an encoder 16. The

Outputs of the numeric keypad 14 are connected to corresponding inputs of the encoder 16. the Outputs of the type of operation keyboard 15 are connected to corresponding inputs of the control unit 10.

The outputs of the encoder 16 are via busbars or lines with information inputs from gate units - called gates for short - 17o ... 17 _{7 of} a gate group 17 for storing all positions of the first operand register 11 as well as an information input from gates I80 ... I87 Gate group 18 for storing all positions of the second operand register 12 connected. The tail unit

10 is via a control rail (not shown) for preparation of the storage in the first operand register 11 with a first control input of all Gates 17o ... 177 and via a control rail or line (not shown) for preparing the storage in the second operand register 12 with a first control input of all gates I80 ... I87 connected.

The outputs of the three lowest digits of bidirectional counters 19, 20 and 21 of the switching unit 4 are connected to corresponding inputs of binary decoders 22, 23 and 24 of the switching unit 4. the The outputs of the decoders 22-24 are in places connected to the first control input of the corresponding gates 5 /> ... 57,60 ... 67 or 7o ... 77 of the first, the second and the third gate group 5, 6 and 7 of entrance gates of the arithmetic unit 1 are placed

The outputs of the decoders 22 and 23 are also locally connected to the second control input of the corresponding gates 17o ... 177 for the first operand register

11 and the gates I80 ... I87 for the second operand register 12

The outputs of the decoder 24 are also locally connected to the first control input of the corresponding gates 80 ... 87 and 8s ... 815 of the gate group 8 of Output gates of the arithmetic unit 1 laid

The zero output of the fourth digit of the counters 19, 20 and 21 is to the second control input of all gates of the first, the second and the third gate group 5, 6 and 7 placed The zero output of the counter 21 is also connected to the second control input of all gates 80 ... 87 of the Goal group 8 placed.

The one output of the fourth digit of the counters 19, 20 and 21 is connected to the respective entrances of the empennage 10 via rails (not shown) The one output of the fourth digit of the counter 21 is also at the second control input of all gates 8s ... 8 | 5 put The outputs of registers 11 - 13 are in places with corresponding entrances to the gates, the first, the second and the third gate group 5,6 brw. 7 connected by input gates of the arithmetic unit 1.

The outputs of all gates of the first gate group 5 of input gates of the arithmetic unit 1 are connected to the corresponding inputs of an input gate 25 of the multiplication direction 2, an input gate 26 of the adder 3 and a first operand code evaluator 27.

The exits of all gates of the second gate group 6 of entrance gates are with the corresponding Inputs of an input gate 28 of the multiplication device 2, an input gate 29 of the addition device 3 and a second operand code evaluator 30 connected.

The outputs of all goals of the third goal group 7 of

Entrance gates are connected to the corresponding inputs of an entrance gate 31 of the multiplication device 2, an input gate 32 of the addition device 3 and a result code evaluator 33 are connected. the The outputs of the code evaluators 27, 30 and 33 are via rails (not shown) with corresponding inputs of the tail unit 10 connected.

The first multiplicand inputs of the multiplier 2 have corresponding outputs of gates 25 and 31 connected. The second multiplicand inputs of the multiplier 2 are with corresponding outputs of the gate 28 connected.

The outputs of the lowest product position of the multiplier 2 are connected to corresponding ones Inputs of the input gate 34 of the addition device 3 placed. The outputs of the highest product position of the Multiplication device 2 are connected to corresponding inputs of input gate 35 of the addition device 3 geicgt.

The outputs of the input gates 26 and 29 of the addition device 3 are connected to corresponding information inputs placed by complement builders 36 and 37.

The inputs of a ones adder 38 of the adder 3 are connected to corresponding outputs of the gates 32 and 34 and the complementary 36 and 37. The inputs of a ten adder 39 of the addition device 3 are connected to corresponding outputs of the gate 35 placed. The carry output of the ones adder 38 is connected to the corresponding input of the tens adder 39 and the carry output of the ten adder 39 to the corresponding input of a carry indicator 40 placed.

The sum outputs of the units adder 38 are connected to corresponding inputs of an output gate 41 of the addition device 3, the outputs of which are connected to the corresponding inputs of all gates 8o ... 8 _{t5 of} the gate group 8 of output gates of the arithmetic unit 1.

The control inputs of gates 25, 26, 28, 29, 31, 32, 34, 35, 41, the control inputs of the complement generator 36 functions with the aid of the switching unit 4 of the arithmetic unit 1.

Let us now assume that the computer is operated one after the other when entering and performing the operations "> Addition. Subtraction, multiplication and division considered.

The numbering of the digits takes place according to the base power that gives the place value certainly. For example, the ones place is referred to as the zeroth κι place and the tens place as the first place.

input

The switching of the inputs of the master operand register

i ^r i sters 11 when the first operand is entered is carried out by the bidirectional counter 19 and the decoder 22.

Each reverse counter 19, 20 or 21 of the switching device 4 generally has the count

2 (i from 0 to 2k-1, where k is the digit capacity of the registers. Corresponding to the assumed digit capacity of the computer, the counter 19 has four binary digits. The decimal digits of the registers are numbered from 0 to 7, the digit of the register is a

r> such state of the associated meter assigned, in which the content of three of its lowest digits is a binary representation of the given digit number. The rises of these three lowest places of the Counter 19 are connected to the inputs of the binary decoding

! » rers 22 connected. In each of the eight states of the three lowest digits of counter 19 appear on output rails of the decoder corresponding to this state 22 a signal which is sent to the first control inputs of the corresponding gates of gate group 17 for the

ι '· First operand register 11 arrives and when entering the respective position for information storage prepared. When asked, i. H. when executing the Arithmetic operation when an interrogation permission signal from the output of the fourth Ste'le of the counter 19 is present

■ »<> (this signal corresponds to the Nuüzusiand of the fourth digit), causes the above-mentioned signal from the Δ itcaontvccfHipn;» Hip AiiccraKi * rif »r Information ntic Hpr

19, 20 and 21 as well as the delete and shift inputs the addition device 3 are via control rails (not shown) with corresponding outputs of the Tail unit 10 connected.

When operating the computer described, the operator proceeds as follows:

a) input of the first operand;

b) pressing the type of operation key, which determines the type of operation to be performed;

c) input of the second operand;

d) pressing the key that allows the given operation to be carried out.

The operands are entered in natural order, starting with the highest digit, in such a way that that the highest position of the operand always goes to the highest position of the associated operand register 11 or 12, while the position of the lowest digit in the operand register depends on the length of the operand The first operand is in the first operand register 11 and the second in the second operand register 12 entered.

The switching of the operand register inputs for the input of the operands and the output of the Results and the query of the operand registers 11 and 12 while the arithmetic operations are being carried out Place via the corresponding gate of the input gate group 5 of the arithmetic unit 1.

It can be seen that the states of the counters 19-21 clearly the numbers of the bodies participating in the operation of the calculator at the given time determine.

The counters 19-21 are controlled by the

i'i tail unit 10 in accordance with the to be executed Operations and will be discussed below.

Before the input, the switching unit 4 is in the initial state, ie a storage preparation signal is given from the control unit 10 to the first control inputs of the gates 17 ₀ ... 177 for all positions of the first operand register 11, the counter 19 is at the counter reading 111! reset, and a preparation signal is given to the subtraction input of the same counter 19. Here, the gate group 5 of entrance gates is blocked by the absence of a signal from the output of the fourth digit of the counter 19, and the output rail 22z of the decoder? 22 is excited As a result, the seventh position of the first operand re-

f> 5 registers 11 prepared for storing information

When you press that key on the numeric keypad 14, the number of the highest digit of the first

Corresponds to operands, the code of the The number entered is supplied, which is possibly stored in the seventh position of the first operand register 11 will.

After pressing any number key and storing the corresponding code in the first operand register 11, the control unit 10 supplies a clock pulse to the counting input of the counter 19. Here the count of the counter 19 is reduced by one and, if necessary, the output rail 22 & des Decoder 22 energized, i.e. H. to store the next digit (position) of the first operand the sixth position of the first operand register 11 prepared.

All remaining digits of the first operand are entered in a similar manner.

After entering the first operand, one of the keys of the operation type keyboard i5 is pressed, which determines the type of operation to be carried out. In this case, a storage preparation signal is sent from the control unit 10 to the first control input of the gates of the gate group 18 for all positions in the second operand register 12, as well as a preparation signal to the subtraction input of the counter 20. Since the counter 20, like the counter 19, was reset to state 1111, the seventh position of the second operand register 12 is now prepared for storing information. The input of the second operand in the second operand register 12 is similar to the ^M Lingabe of the first operand in the register Erstoperanden. 11

After completing the input of the first (second) operand, the first (second) counter 19 is located (20) in a state that corresponds to the digit number of the Ersl (second) operand register, the immediately follows the position at which the digit of the lowest position of the first (second) operand is stored. If the digit capacity of any operand equals the digit capacity of the operand register is and therefore the lowest digit of the O

addition

^ ersnderi \ r the rvj

11 or 12 is entered, the corresponding counter 19 or 20 is brought to the counter reading 1111.

The described operating sequence of the switching unit 4 * ⁵ when entering the operands applies to addition, subtraction and multiplication. The division requires some deviations from this operational sequence, which are discussed below.

The execution of any arithmetic operation ^Μ begins after pressing the ON key. Before starting the steps that are directly related to the execution of the corresponding operation, some general preparations are made:

55

a) Increase in the count of counters 19 and 20 by one, which means that the lowest digits are queried both operands prepared; and

b) Resetting the fourth digit of the counters 19 and 20 to the zero count, which is the query of the «ι First and second operand registers 11 and 12 are allowed

The execution of the calculation of the individual result digits or digits is each elementary cycle called, whereby each elementary cycle has a number equal to the number of the cycle through it obtained result position is assigned

In the zeroth elementary cycle of adding two numbers, the zeroth (decimal) digits (units) are the summands are added, so that the zeroth digit of the sum and, if necessary, a carry-one for Tens digits (if the sum of the ones digits is greater than 9).

In the first elementary cycle, the first digits (tens digits) of the numbers and the are added possible carry-over from the ones place etc.

The highest digit of the sum is the sum of the highest digits of the summands and a possible one Carry over from the previous lowest digits if this sum is less than 10, or as Carry-one, if the sum is greater than 9, is formed. In the former case is the number of addition unit cycles equal to the number of digits of the larger summand, in the second case larger by one.

In detail:

Before starting the addition operation, the summands are entered:

into the first operand register 11 A = a ₂ a \ a ₀ ,
into the second operand register 12 B

as explained above (in the description of the input operation).

When the addition is carried out, the complement formers 36 and 37 of the tail unit 10 are constantly activated Non-complement formation commands given. The bidirectional counter is set to the Counter reading 0000 brought. This means that the information (the lowest digit of the Sum) the zeroth position of the result register 13 prepared. The tail unit 10 supplies preparatory signals to the summing inputs of counters 19, 20 and 21.

After pressing the ON key, the counters 19 and 20 are set to a count which corresponds to the query of the units ao and bo of the summands (this count may be 0101 for the counter 19 and 0011 for the counter 20).

Im nnjjt *> n F] * »rr» «» nt2r; 7vl / | ijc AHHitjrin € T »K | rjac

Tail unit 10 sends a control signal to gate 26, as a result of which the non-complement code ao reaches the inputs of units adder 38 of addition device 3 via the complement generator. The tail unit 10 then sends a control signal to the gate 29, and the non-complement code bo is sent to the inputs of the units adder 38 via the complement generator 37. The addition of the codes ao and fib is carried out in the ones adder 38. The sequence of addition, the total correction (if necessary) and the type of transfer of a carried forward to the next higher position are not considered here, as these depend on the coding system used and the type of adder and are carried out in a known manner.

The results of the zeroth addition elementary cycle are: lowest (zeroth) digit of the sum Q, and if necessary carry over to the next higher digit. The code of the sum Co passes from the outputs of the units adder 38 to the information inputs of the gate 41. At this time, a release signal for the output of the result is given from the control unit 10 to the control inputs of the gate 41, and the code CJ is entered into the prepared The zeroth digit of the result register 13 is stored. The (possibly present) carry to the next higher digit is stored in the units adder

38 and takes on the following addition elementary cycle part.

At the end of the zeroth elementary cycle, the preparation of the switching unit 4 takes place for the execution of the The next elementary cycle takes place, namely from the control unit 10 a clock pulse to the arithmetic input of all three bidirectional counters 19, 20 and 21 are given so that the counters (here) assume the following counter readings:

Counter 19: 0110, counter 20: 0100, counter 21: 0001. This means that the query of the digits a \ and b \ of the summands and the storage of the results in the first digit of the result register 13 are saved.

The addition of the codes a \ and b \ and the resulting carry from the previous elementary cycle is carried out in the first elementary cycle in a similar way to the addition described above in the zeroth elementary cycle. The result of the first elementary cycle is the sum digit G and, if necessary, a carryover to the next higher digit.

This ablaut for the execution of the addition elementary cycle repeats itself until there are significant places in both summands. In one certain elementary cycle, the highest digit of one of the summands is processed (here: the digit / fe des first summand, which is processed in the second elementary cycle).

The switching unit 4 then functions as follows:

At the end of the second elementary cycle, the clock pulse brings the counter 19 to the count 1000 and the counter 20 to the counter reading 0110. In all subsequent elementary cycles (until termination the addition operation) finds the addition of the digits of the second summand with any Carry-overs from the preceding passages take place, while the first addend to the Adder the zero code is given (in the assumed coding system), since the gate group 5 of entrance gates of the arithmetic unit 1 is blocked by a signal from the fourth digit of the counter 19.

In the fourth elementary cycle (here) the position b \ of the second summand is processed and the value of the

^ ru bllJlbllt. C ~ »VlItUIlUII, UCI III UIC VlCI IC OlClIC UCd

Result register 13 is stored. In this Elementary cycle, the counter 20 is set to the counter reading 1000 (the counter 19 is on the Counter reading 1010). At the same time the one in the fourth position of the counters 19 and 20 indicates that the query the summand has ended. According to this criterion, the tail unit 10 completes the addition operation, as soon as there is no carryover from the last elementary cycle. If there is a carry over, this has the effect Tail unit 10 the storage of the transfer to the fifth position of the result register 13, whereupon it the Operation Summation completes.

subtraction

Traditionally, the subtraction operation in digital computers is usually done by adding the Complement codes of the operands on an adder with cyclic carry or by adding the Complement codes on an adder without a cyclic carry. If here the difference is negative Number is is before the output of the result from the Arithmetic unit their recoding required.

To enable the use of simple information sources (simple data acquisition) and It is sufficient to avoid additional structural effort to carry out the recoding mentioned it in the present arithmetic unit, with each subtraction the minuend as a positive number and the subtrahend to be regarded as a negative number and to select the operand as the minuend that follows the The absolute value is greater. Then the result of the machine subtraction is always a positive number, so that on the output of the arithmetic unit the results of the digit-by-digit operations in complement codes which, under these conditions, coincide with the non-complement codes. The result sign can easily be changed according to the sign of the operands and their relative Numerical value can be determined.

Machine subtraction consists of two steps:
First step:

Comparison of the operands according to the absolute value. When performing this step, the

w adder is supplied with the first operand in non-complement code and the second in complement code. The result of this addition does not reach the output. The relative value of the operands is determined after the occurrence and absence of a carry by adding the highest digits: In the case of a carry, the first operand is greater than the second; without a carry, the second operand is greater than the first.
Second step:
In accordance with the comparison carried out in the first step, the operand in the complement code and the larger operand in the non-complement code are fed to the adder according to the absolute value. Then an addition is carried out in places without taking cyclical carry over into account.

In detail:

The minuend is stored in the first operand register 11 and the subtrahend in the second operand register 12 entered.

When performing the first step of the subtraction operation, the tail unit is constantly being used 10 a non-complement formation instruction into the complement generator 36 and into the complement generator 37

U-T-I-I ι

JUIVI £ gCL / C "

The partial addition of the non-complement code of the minuende to the complement code of the subtrahend is carried out in a similar way to the addition operation described above, only the results are not included in the result register 13 is stored, since there is no release signal for the result output in this step is given to the gate 41. At the same time, the one in the fourth position of the counters 19 and 20 shows the conclusion of the first step (operand comparison). According to this criterion, the tail unit 10 causes the Evaluation of the comparison results on hand

a carryover from the highest places of the comparative figures. The control of the second subtraction step depends on this evaluation. If there is a carry over from the highest digit, it is Minuend greater than the subtrahend, the control of the complement formers 36 and 37 remains in the The second step is the same as in the first step. If, on the other hand, there is no carry over, the minuend is smaller as the subtrahend, a complement formation command is sent to the complement generator 36 and to the complement generator 37 a non-complement formation command issued.

In addition, the tail unit 10 has the following effect during the transition to the second step:

a) Setting of the counter 21 to the counter reading 0000, whereby the zeroth Stellr of the result register 13 is prepared for storing information (lowest difference point);

b) Storage of a one at the lowest Binary digit of the ones adder 38, whereby the addition necessary in the second subtraction step is saved in complement codes;

c) Resetting the fourth digit of the counters 19 and

20 to zero, which means that operand registers 11 and 12 are repeatedly queried in the second subraction step is allowed.

The counter status of the counters 19 and 20 at the beginning of the second step depends on the ratio of the position-based operand lengths. For the operand of greater length, the counter reading is 0000, while for the operand of shorter length it is equal to the binary representation of the operand length difference.

After the preparation described, the computer will start executing the second step of the Operation subtraction. The criterion for completing the operation is the presence of one on the fourth Place the counters 19 and 20, so the number of addition elementary cycles in the second step is the Operation subtraction equals eight, regardless of the operand length. In the zeroth elementary cycle of In the second step, the zeroth position of the operand register that has the longer one is queried Contains operands, and that position of the second operand register whose number is equal to the difference is the operand length. If the length of both operands is less than the length of the operand register, so in this elementary cycle the "empty" memory locations of both operand registers are queried, d. H. the memory locations without significant digits. The code evaluators deliver in such "idle" elementary cycles 27 and 30 of the operand registers 11 and 12 corresponding signals to the control unit 10, which at in this situation the gates 26, 29 and 41 as well as the counter 21 blocks. The number of "idle" elementary cycles is equal to the difference in length of the operand register and the operand with the larger Steiienanzani. 1st If the length of even one of the operands is equal to the length of the register, the "idle" elementary cycles remain the end. During the "idle" elementary cycles, as in normal elementary cycles given in the adding inputs of the counters 19 and 20 preparation signals. Hence increases to a certain Time of the counter, which queries the operation register of the longer operand, a counter reading, which corresponds to the query of the lowest digit of this operand. As in the counter of the other operand register At the beginning of the second step the difference between the operand lengths was stored, becomes the same Time, the lowest digit is also queried for the other operand. When this counter reading is reached, d. H. when significant operand positions appear, the code evaluators 27 and 30 output the Tail unit 10 the counter 21 and the gates 26,29,41 free.

Immediately after this, the zeroth elementary cycle of the second step of the subtraction operation takes place The addition of the one previously stored in the ones adder 38 is carried out in this cycle to the non-complement code of the lowest digit of the larger operand and to the complement code of the lowest digit of the smaller operand. The result - the lowest digit of the difference - is stored in the zeroth position of the result register 13.

The other elementary cycles of the second step are carried out similarly.

The criterion for completing the subtraction operation is the occurrence of a one in the fourth position both counters 19 and 20 during the execution of the second step.

multiplication

In the present arithmetic unit, the multiplication according to defrl is known per se (cf. DD-PS 30 925) Algorithm of the so-called "crosswise multiplication" carried out, which consists of the following (cf. also the process steps CD and O in F i g. 2):

The multiplication of two n-digit factors (multiplicand and multiplier) is carried out over 2n elementary cycles.

In the zeroth elementary cycle there is an elementary product by multiplying the zeroth (lowest) digit of the multiplicand by the zeroth (lowest) digit of the multiplier. The lowest digit of this elementary product is equal to the zeroth (lowest) Digit of the end (result) product, while its highest digit is the carryover to the first digit.

In the first elementary cycle there are two elementary products by multiplying the zeroth digit of the multiplicand by the first digit of the multiplier and also the first digit of the multiplicand is formed with the zeroth digit of the multiplier. The partial product of the first elementary cycle is equal to the sum of these two elementary products and that in the zeroth Elementary cycle obtained carry. The lowest digit of the partial product of the first elementary cycle is equal to the first digit of the end product, while its highest digits carry over to the next higher Bodies are.

In each subsequent elementary cycle - from the zeroth to the (n - 1) th cycle - the number of elementary products is increased by one, but further - from the (n - 1) th to the (2n - 1) th elementary cycle - reduced by one each time. In each elementary cycle, the products of all possible pairs of digits of the operand positions are considered to be elementary products (in each pair one digit comes from the multiplicand and one from the multiplier), whereby the sum of the digit numbers of both digits of any pair is equal to the elementary cycle number.

In each elementary cycle the exact value is given to one digit of the end product, its number is equal to the elementary cycle number. The highest, i.e. (2 /? - I) -th, digit of the end product is equal to the sum of the carryovers obtained in the previous elementary cycles.

In detail:

The multiplicand is in the first operand register 11 and the multiplier in the second operand register 12 brought.

In the general description of the operation sequence (crosswise) multiplication was has shown that the formation of elementary products is necessary in order to obtain the Ath position of the product Pairs of digits is required, the sum of which is equal to / is The selection of these pairs of digits is made by the switching unit 4 made according to the following rules:

In each multiplication elementary cycle, one counts the bidirectional counters 19 and 20 from 0 to / and the

others from / to 0, it can be seen d & Ö when im Beginning time the first counter interrogates the zeroth digit of one factor and the second the one Query of the / -th digit of the other factor determined has, in the case of continuous counting, the sum of the s Numbers of the queried positions are always the same / is

The transition from one counter to the is used as the criterion for completing an elementary cycle Counter reading 0000.

During the transition from the / th elementary cycle to the to (i + l) th elementary cycle, a one is added to the counter that is in the / state, while the other counter remains at the zero count

In the (/ + l) -th elementary cycle, the counting sequence is changed: Now the first counter counts from (i + \) to 0 and the second from 0 to (i + \). Thus, in the (i + l) -th elementary cycle, those positions are queried whose sum of numbers is equal to (i + 1)

The described operating sequence of the bidirectional counter is retained when all In elementary M cycles are executed. Here, beginning with the (n - \ y \ sa elementary cycle, pairs of digit numbers appear, one of which exceeds the number of operand digits This is automatically ensured in the switching unit 4 used that, as soon as a number appears in any counter which exceeds the digit capacity of the operand register, a signal from the highest digit of this register appears Counter blocks the query of the corresponding operand register. As a result, in all elementary multiplication cycles, including the elementary cycles with numbers greater than (n- 1), only the significant positions of the factors participate in the formation of partial products.

Let us now consider the operation of arithmetic unit I during the execution of the multiplication operation. In accordance with the cross-multiplication algorithm, the partial product, which is equal to the sum of all elementary products of the given cycle, is calculated in each elementary cycle. 10 by providing the stabilizer in the query each factor unit pair signals to the input ports 25 and 28 of the multiplier 2. The code of the (decimal) number of the first multiplier reaches the inputs of the first factor of the Multiplikationseinrich- ^x device 2 and the code of the numeral of the second multiplier to the inputs of the second factor. At the same time the control unit 10 supplies control signals to the gates 34 and 35. As a result, the code of the lowest digit of the elementary product is applied to the ^5S input of the ones adder 38 and the code of the highest digit of the elementary product is applied to the input of the tens adder 39 of Multiplier 3 given. In the adder 38 (39) the units (tens) of all elementary items of the given * ° elementary cycle are added up. In this case, the carryovers from the units adder 38 are transferred to the tens adder 39 and those from the tens adder 39 are transferred to the carry indicator 40. The content of the ones adder 38 is equal to the value of the corresponding digit of the end product at the end of each elementary cycle. A release signal for the output of the results is given from the control unit 10 to the output gate 41, and the code of the given digit of the end product is stored in the position in the result register 13 prepared for storage. by it

a) sends a signal to the addition device 3 for a right shift by one decimal place;

b) the counter 21 switches to the next count, whereby the next digit of the Result register 13 is prepared for storing the next digit of the end product.

It should be noted that when processing of the fictitious places of the factors on one of the input gates of the multiplication device 2 of the Zero code (in the assumed coding system) is given so that the fictitious elementary products equal zero and have no influence on the sub-products.

Up to now, the multiplication of eight-digit operands has been considered, with the counters 19 and 20 The start of the operation was at zero. In the general case, with any number of digits in the operands or factors, the counters show after Entered counter readings that correspond to the number of digits of the entered factors, while the lowest Positions in operand registers 11 and 12 remain "empty". Here the length of the product is the same the sum of the factor lengths is less than 2n, and the multiplication operation is carried out with a corresponding number of elementary cycles

In this case, the counters 19 and 20 show certain counts other than zero. The tail unit 10 begins work in accordance with these conditions, namely delivers preparatory signals on the subtraction input of counter 19. The elementary cycle becomes zero when the counter reading is reached ended by the counter 20. It can be seen that in this elementary cycle only the first elementary product through the significant (lowest) digits of both Factors is formed. On each of the remaining elementary products, one of the "empty" places takes the second factor, so they have no influence on the partial product. Thus, in the elementary cycle under consideration, the lowest (zeroth) digit of the end result becomes generated, which is why it is considered to be the zeroth elementary cycle

Subsequently, the operation of the multiplication control circuit and the control of the take place Arithmetic unit in accordance with the conditions described above, but the partial products are only identified by the significant places in the Factors formed

division

Conventionally, in digital computers, division is done by continuously subtracting the divisor carried out by the current remainder with default and make wise shifting of the remainder

In contrast, the invention goes to enable the use of simple information sources (simple data acquisition) and the structural effort reduce, from a division algorithm by means of quotient digits taken on a trial basis (called trial quotient digits for short).

To make the Dtvisions algorithm easier to understand, reference is made to the exemplary embodiment in FIG. 2 referenced, which should basically be understandable in and of itself. The capital book circled there by

The procedural steps indicated are described below as a precaution at relevant points in In the context of the further explanation of the division algorithm.

The consecutive trial quotient digits (digits) are (starting with the highest digit) determined by continuous testing (from I to 9) (process step ©).

With each trial, the divisor (e.g. 24) is multiplied by all the (final result) quotient digits (including the lowest trial quotient digit) already obtained in the preceding elementary cycles (process steps © and Q)).

The divisors that divide without a remainder are determined on a trial basis and are each derived from the corresponding most significant part of the dividend (e.g. 768) subtracted (process step ©).

If the sign of this difference is positive, then the next largest for the given sample quotient position Digit taken.

If, on the other hand, the sign of this difference is negative (process step ©), the final value is given quotient position, the number of the previous sample quotient position is stored (method step (P)).

The subtraction and multiplication algorithms used in the present arithmetic unit advantageously allow this to be carried out Division algorithm without memory for storing the divisors that divide without remainder and the remainders as well get along without any changes to the output (operand) information. this is achieved as follows:

With each elementary cycle of multiplication (cf. above description of the multiplication) an exact number of the current product position is formed This digit is immediately added to the complement code of the corresponding dividend digit Processing of all product locations is due to the occurrence or the absence of a cyclical transfer The sign of the difference can be seen, which is solely due to a further increase in the trial quotient position by One decides The comparison used here of the divisor that divides without a remainder with the Dividends is similar to comparing the operands in the first step of subtraction (see description of subtraction).

The dividend (e.g. 768) is stored in the first operand register 11 and the divisor (e.g. 24) in the Second operand register 12 stored When the dividend is stored, the payer 19's payer status, such as usually decreased by one, however, after pressing the operation type key 14, the operation Division determines the "normal" operating sequence of the two-way counters 19 and 20 described above leave, and indeed will! the payer 19 is brought to the payer status zero) and its subtraction input parallel to the subtraction input of the payer 20 As a result, when the divisor is entered, the counters 19 and 20 are synchronized by one decreased with each digit entered. After entering the divisor and pressing the ON key, the Storage location of the second operand register 12 at which the lowest position of the divisor is located, and the position of the same name in the first operand register U prepared. Furthermore, the tail unit 10 carries out the following operations before the start of Operation Division:

a) switches the control of the multiplication operation from the addition and subtraction inputs the bidirectional counter 19 to the corresponding inputs of the bidirectional counter 21; b) issues a complement code generation command to the Complementer 36;

c) gives control signals to the gates 28,31,34 and 35;

d) sets the counter 21 to the counter reading Olli, whereby the seventh position of the result register 13

ίο for storing the highest quotient digit is being prepared.

The actual division process then begins. Since in the initial elementary cycle the value of the

is reached the highest (seventh) quotient digit (cf. Process step © in FIG. 2), let this division elementary cycle be the number seven in accordance with the assumed condition and be the decrease in the next division elementary cycles de assigned to numbers six, five, etc.

Let us now consider the operation of the calculator when executing the seventh division elementary cycle considered According to the division algorithm used (see above) is the first one taken on a trial basis Quotient place equals one (see process step ©). To obtain this "trial quotient position" by a signal from the tail unit 10 in the units adder 38 the one code wor given to a control signal on the output gate 41 becomes, whereby the one code in the prepared seventh The memory location of the result register 13 is then reached. The first trial multiplication of the predetermined one then begins Trial quotient digit one with the divisor (method

rens step ®) with simultaneous place-by-place comparison of the product positions of the divisor dividing without a remainder (e.g. 24 in Fig. 2) with the corresponding positions (e.g. 76 in Fig. 2V of the dividend (e.g. 768; see process step @ ) The trial multiplication

is with the content of the operand registers 12 and 13 carried out, queried by the payers 20 and 21 will.

in each elementary cycle of the (first) trial multiplication, those according to those from the crosswise Multiplication known rules formed digit pairs of the operand registers 12 and 13 interrogated, wherein the places of the quotient via the gate 31 to the inputs for the first factor of the multiplier 2 and the places of the divisor finer the gate 28

so given to the inputs for the second factor will. The elementary products that are generated by the multiplier 2 pass through the Gates 34 and 35 to the inputs of adders 38 and 39. At the end of the zeroth elementary cycle of the first The trial multiplication of the seventh division elementary cycle becomes the exact digit of the ones adder 38 The zeroth digit of the first divisor dividing without a remainder is formed Control signal given to the gate 25, and on the

μ unit adder 38 gets the complement code the dividend place that corresponds to the lowest divisor place (since after entering the payer 19 just queries this point). In the units adder 38 the addition of these codes takes place and a possible one Carry goes into the ten adder 39. Then the control unit 10 sends a command to shift the Contents of the adder 3 delivered one decimal place to the right. The content of the one's ad

derers 38 is lost while the contents of the Ten adder 39 is fed to the ones adder 38. Then the count of the counter 19 becomes one accordingly, the next higher digit of the dividend is prepared for comparison in the next elementary cycle of the given probation multiplication will.

After completing all elementary cycles of the first trial multiplication (process step ©) of the seventh Division elementary cycle and comparison of all digits of the first divisor that divides without a remainder with the corresponding digits of the dividend (see process step @) the counter 19 is in the counter reading 1000 brought while one of the counters 20 and 21 on Zero is reset, the tail unit 10 receives an overflow signal as a criterion for the Termination of the trial multiplication is used.

Then the preparation of the counters 19, 20 and 21 to execute the next division elementary cycle. For this purpose, the counters IS and 20 preparatory signals are sent to the addition input given as long as a signal from the output of the code evaluator 30 of the second operand register 12 This causes the counters 19 and 20 to be brought back into the state whose number corresponds to the number of Storage location of the second operand register 12 at which the lowest digit of the divisor is stored, then corresponds to the addition input of the Counters 19 and 21 given preparation signals as long as a signal from the output of the code evaluator 33 of the result register 13 is present. As a result, the counter 21 is brought back to the count, the the query of the seventh position of the result register 13 corresponds, and the counter 19 to the counter reading, the the query corresponds to that position of the primary operand register 11 whose number is less than one by one is at the previous sample multiplication

The comparison results are then evaluated. Two cases (named a and b) are possible here:

a) In the ones adder 38, there is a carry-one; h, the trial quotient digit has the exceeded correct value. In this case, the tail unit 10 supplies a control signal to the gate 32, whereby the code of the Trial quotient position is fed to the units adder 38, into which the one-complement code then also arrives, so that the trial quotient parts are reduced by one, whereupon a control signal given to the output gate 41 and the correct quotient position is stored in the corresponding memory position of the result register 13 (see process step ©). Then a preparation signal is given to the subtraction input of the counter 21, the by a subsequent clock pulse to one of the processing of the next lowest Quotient digit corresponding counter reading is brought. If the counter 21 arrives at the Counter reading 1111, i.e. that in the previous Division elementary cycle the zeroth part of the quotient has been obtained, the tail unit closes 10 perform the division operation (see procedural step

Otherwise there is a transition to the zeroth elementary cycle of the first sample multiplication (cf. process step (S)) of the next (sixth) division elementary cycle, which is similar to the one above is carried out as described, b) In the ones adder 38 there is no carry-one, d, h, the trial quotient position is smaller (equal) than the correct value

In this case an attempt is made to increase the trial quotient position (by one) (with subsequent Sample multiplication) (cf. process steps ©), for which the tail unit 10 sends a control signal to the goal 32 gives, which is the code of the trial quotient digit the ones adder 38! is fed. On the Addition input of the counter 19 is given a preparation signal, so that the counter 19, the Execution of the next division elementary cycle is ready by a subsequent one Clock pulse to the counter reading required to continue the previous division elementary cycle is brought back. This is followed by the transition to the next trial multiplication.

In summary, the four basic arithmetic operations can be carried out in the arithmetic unit described, such as can be presented as follows, which at the same time proves its simplicity:

addition

Both complement builders 36 and 37 are controlled by the tail unit 10 scr that the two Summands are allowed through uncomplemented.

subtraction

The tail unit 10 controls so that the complement generator 36 in the first step (comparison) the minuend uncomplemented, however, the complementer 37 allows the subtrahend to pass through complemented; at the In the second step (actually an addition), the control depends on the comparison result:

If the minuend is greater than the subtrahend, it remains the control of the complement formers 36 and 37 by the tail unit 10 remains unchanged; is jedfe .. 'h - the other way round - The subtrahend is greater than the minuend, the control unit 10 exchanges the control: The Complement generator 36 complements, while the complement generator 37 lets through uncomplemented

multiplication

so Both complement builders 36 and 37 are not involved in it, i. H. both factors are a priori as positive numbers are considered, so that they are uncomplemented via the gates 25 and 28 to the inputs of the Multiplier 2 arrive and from their Outputs the elementary products via the gates 34 and 35 of the addition device 3 can also be supplied in an uncomplemented manner.

division

The complementing party 37 is not involved in it, while the complementer 36 forwards the dividends in a complementary manner, so that the necessary (in According to the algorithm applied) Comparison of the dividend with the products of Trial quotient and divisor is guaranteed.

For this purpose 2 sheets of drawings

Claims (6)

Patent claims: J. Apparatus for a serial four-species arithmetic unit for dividing entered numbers by taking the difference between that by multiplying the divisor by itself from the value one continuously increasing by one sample quotient in each case obtained product and that of the number of digits of the product, part of the dividend beginning with the highest digit and by means of Determination of the highest trial quotient that just has not yet changed the sign of the difference in, if necessary, analogously to for processing the dividend repeating cycles; with a computing device for crosswise multiplication of multi-digit numbers and for Addition of the partial products, with operand registers to accommodate the numbers to be processed and with a switching unit containing a counter for entering the operands into the Computing device, characterized by a) a result register (13) also for recording the respective trial quotient; b) a first goal group (7) for entering the respective from the result register (13) removed sample quotient into the multiplication device (2); c) a second goal group (6) for entering the divisor into the multiplication device (2); d) Goals (34,35) for entering the received Product in the adder (3); and e) a third gate group (?) for entering the corresponding dividend points in the addition device (3) via one in this intended complementing agent (36). 2. Apparatus according to claim 1, characterized in that the switching unit (4) via counter (19-21) and downstream decoders (22-24) the first, second and third gate group (7, 6, 5) controls 3. Apparatus according to claim 2, characterized in that the switching unit (4) via which also the first gate group (7) controlling counter (21) and the associated decoder (24) a fourth, the Controls the goal group (8) entering the result numbers in the result register (13). 4. Device according to one of the preceding claims, characterized in that the addition device (3) has: a ones adder (38), a ten adder (39), a carry indicator (40) and Complement formers (36, 37) connected upstream of the units adder (38). 5. Apparatus according to claim 4, characterized in that the first sample quotient position first is set equal to one by entering one into the ones adder (38) and from this via a Output gate (41) is stored in the highest memory location of the result register (13); and that in the case of a negative difference between the product obtained by multiplying the divisor by the sample quotient and that of the Number of digits of the product corresponding to the part of the dividend beginning with the highest digit Via the first gate group (7) and a gate (32) connected downstream of it, the trial quotient point into the One adder (38) is entered and one is subtracted from it there, after which the subtraction result is returned to the output gate (41) corresponding memory location de? Result register (13) is stored; however, if there is a positive or zero difference via the gate (32) downstream of the first gate group (7) the last taken sample quotient digit is entered in the ones adder (38) to become one to be added, and then via the output gate (41) into the corresponding memory location of the Result register (13) is stored. 6. Apparatus according to claim 5, characterized in that in a known manner Tail unit (10) is provided which, when the operation type key (operation type keyboard 15) is pressed, corresponding to the arithmetic operation to be carried out controls: the counters contained in the switching unit (19-21), Entry gates (25, 28, 31) and exit gates (34, 35) of the multiplication device (2), gates (26, 29) upstream of the complementary formers (36, 37), the output gate (41) connected downstream of the addition device (3) and the for (32) arranged between the first gate group (7) and the addition device (3).