DE2148410C2 - Circuit arrangement for avoiding double connections in time division multiplex telecommunications systems, in particular PCM time division multiplex telephone exchanges - Google Patents

Description

One of the tasks in the telephone exchanges is to prevent undesired connections between two already interconnected participants and a third participant, so-called Avoid double connections. Such double connections can be used in conventional switched switching systems occur in that two dialing devices approximately simultaneously one and the same Check that the line is free and try to assign it; because initially both voting institutions have the If the line is in the free state, the corresponding test switching means can also be used for both dialing devices speak and seize the free line. Such a double occupancy can occur all the sooner the longer the period of time the test switching means to address and thus to seize the relevant line and to block against a need additional occupancy. One is therefore striving in conventional switching technology that To keep the danger time, in which double connections can arise, small.

The newer switching technology has led, among other things, to the development of switching systems, with which not, as with conventional telecommunications.

Telephone leasing systems. one of temporally continuous analog, spatially separated overfid d bi d

the connections ^already
drove in the course of a
also in several, each
d V

em loading

Art

φI p ^

• «ίΙριΓ in spatially separated over- also m several, una each». ».... _the

Scale takes place, but in which, instead of just existing verb inventions more ode _v, in space division multiplexing principle of time Principle 5 less many ^ itkanaimgen _Koppe lpunkt-

rX-iuc "is made, whereby temporally discontinuous such switches can be _{transmitted in particular * £ W ^ Zejt} . rh / λη lUm- or digital simals. be contacts by means of which in a gi

SOkE ¹ Mi switching systems are not. w, e in the case of a multiplex switching system in a plurality of ⁿ wave switching systems that send the information to multiplex lines

forth in existing connections along the lines 10 are connectable via iiv.-sweges distributed relay like. gespei- multiplex lines ve each other by such information are in this context it is _equipment,

concentrate as each other, respectively / u linking (German Patent No. 1 8 57 *, α _participants Leitu.iL · portions indicating Ada s address in each of which a M lirzdW _{characterized}

, "K.vicher saved. In such a time ^{- 15 associated multiplex rails, to Uml} : Srnmelde-. especially telephony to a line group together

Deposits it is due to a time-consuming via connection lines m. _mailul . separate handling of relating to the entrenched time channel switches each enzel.Hi local exchange ^ * - are as connectable, ihrers ^ - _"plex - _rails possible from the outset unwanted, o summarized ^ are and de .V" ^ ^

_{because of this}

- - -'Ch possible, combined are ζ _one

In order to avoid the precondition of any supergroup "nteremander" know l fhlfi exercises d V hltng and m

know

α ^^

^ jed it help? ine multiplex _C o _PP eIpunktkon-

/ ί Multiplex J _{ehcn is} .

Address of

Commitments to be mediated for each supergroup «

; st an error-free transmission and multiplexed ^{intermediate line and ^ ^ r for dlt:} production and release of the ^rails i rfe d ^^

to / like required information. It's in-e.ne further Li, approaches to rule out the possibility of an unfavorable circumference to one

B. faulty processing or transferring ^ certain information or the occurrence of clocks can be connected s.nd

^. "Pulse. nevertheless to an undesirable rail en ^^% _ε

Can lead to double connections. m refuse the | £ _{ish line} given

in in such a switching system nevertheless 30 be reffenden ^ ^{u "tip} _d ™ _r effende multiplex rail still unwanted double connections to comparable ^Adre ^ ^{se" d} / ^^^ K nludcn. It is already known (German Patent ^^^^ PiS ^ ) that riduun at a pelpunktkontaktt of a Vergleichst- depending Weinges "comparison made a bond respectively.""£" * £ ^ ⁵ JJSLh successively il just by an address generator, which are cyclical 35 [ '^"a £ S", ibzwisck, , lei ™ _? en Successive the addresses of a straight dieAdressendtreinzelnwmu ι _ejncr

u hren loop status queries the connection, «" Vege.d.er ^ ah ™ nd de ^ ^^ line delivers until the connection line for the address in question through the ^adrt ^ ^ng _{address in} iaufpeicher connection line due to its operating state successively ™ tJen m * The switching processes to be ^{processed in the memory are} _{40 ειη6Γ Α} ^ ^ϋ111 Ρ ^ ™ "° · _η correspondingly with fnd, the address delivered with the in e.nem ^ ^^« 1, J eicher the others

ηig ^ n connections at which the connection line is involved with the address that is currently stored in the address register. One such Procedure allow avoidance of such Double connections attributed to it are that with proper Betneb in the course a time division multiplex system penode only once time channel switches to be operated impulsively in FeWerhafter way several times per time division multiplex system. period are operated. This is sufficient in Ze, multiple switching systems, in which m the individual transmission paths only such in each case time channel switches to be operated impulsively are located once per time division multiplex system penode.

In many cases, however, a time multiplex switching system is used more complex and contains in the one -, one OB van in addition to ^ odo j in each case only e.nma C ^ multiplex system period impulsswc.se to actuate. Time channel switches also switches that jcnachde ^ the time division switching system just exist

sev £ n
the au » ^rc « - ⁿ

55

one

group

sh

ils new starting l _hhdt counts and by Adrcssengleichhcit wah ^ aI «« a multiplex the "connecting .vlulti-

_or during the delivery of the _Mu H, plex rails of an over- ' _rbindenden Multiplcx / wij ^ ⁿ _{leichzi; itiger} control e.ner ungen ^g _{MuUi lcv} , _wi , chenleitung angc- ^ ^r gi _hspei c _h einrichtung as well as ^^ η, οη Identical addresses wah ^m _b ^ _{abe the address of} one of the Mult.p ex-Sfenen Sncr supergroup verbm -. ^^^ S ^^ jsihenleitung without gleiclrze.t.ge dendc Multipκ. _{d; e} ^ "^ _{Mult | p} , _ox .

^ enTeifung connected intermediate storage / w'scntme _t t _ß , _connection anciee.uJcs ei nUitun ^ u ^. ^ ^ _[nög , _tch , " _eilKM

upSf rnmeldeverrmittlungsanlagc the e-

given type of undesired double connections, but essentially comes with a 1 '

to avoid or eliminate. It is all for the inclusion in each case only a single coupling ^S1

However, a relatively high storage capacity requirement Punktadressc to be dimensioned circular storage / ■

for the mentioned, to be built up with circulating storage, and a comparator connected to it; /

the counter is necessary, since in the known 5 it is nevertheless capable of the circuit arrangement according to FIG

Circuit arrangement in each time channel position for itself invention periodically all the multiplication lines with '

the occurrence of address equality can count the individual multiplex links connect- ^

got to; in addition, crosspoint contacts must be aware of their participation in I

processing arrangement, the evaluation switching means able to check a double connection and a falsified <

depending on the address with a different minimum double connection

number of occurrences of address equality to be displayed after such a short time and thus their out ':

to cause a signal indicating a double connection that practically no information

give. The invention described below tion exchange between the at an undesirable

is now based on the task of participating participants with a reduced double connection instead of

Expenditure in a time division multiplex telecommunication switch 15 can be found.

The invention is still based on the drawing

to be able to avoid. explained in more detail. _;

The invention thus relates to a circuit arrangement. The drawing shows schematically in a scope time-division multiplex telecommunications, in particular telephone 20, a PCM time-division switching center, in the beivermittlungsanlagen, in which the addresses of the for example L = 8 four-wire operated time connections involved line sections in multiplex lines, each of which is stored in a receive time multi-address circulation memory and in plex line, like the one shown in the drawing, where a counter with a comparison of 45 carried out by a receiving multiplex line and a send / synchronizing device Time division multiplex line, such as the line section addresses shown in the drawing with the transmission time division multiplex line abl provided in such, with other four-wire operated time division multiplexing \ A each written in with i address circulation memories Addresses can be connected to connections of the line lines involved, for example with a line to the line that is shown in sections with repeated occurrences of address equality in the drawing and that emits the signal shown in the drawing. According to the invention, such a circuit arrangement comprising a transmission time multiplex line abL is time multiplex to avoid double iiplex lines; Connections of two time division multiplex connections in line multiplex switching systems, plex lines, such as. B. the two time division multiplex lines in which the individual Zcitmultiplexlcitungen zu- anllabl and anUabL, are brought about with the help of at least one group of incoming time multiplexers, in which pairs of Zwischenplexleilungcn (receive time multiplex lines) can be inserted with storage, like this z. B. from the individual time division multiplex lines at least one of the German laid-open specification 1 946 883 or from a group of outgoing time division multiplex lines of the German patent 1800 726 is known. (Transmission time division multiplex lines) via time division multiplex The individual time division multiplex intermediate lines ZO, Zwischenleitungcn with the aid of each to a time 40 Z6; ...; Z 3. 3Z are connected on the input side with the individual multiples and a time multiplier between receiving time multiples. Coupling point contacts connected to the line can be connected via coupling point switches, which can each be linked in and in which each incoming and outgoing connection is provided in memory, each of which goes through such a coupling point those periodically consecutive time addresses of the relevant time division multiplex intermediate boxes that are transmitted by the. the address given to the connection of the relevant connection on the relevant emp time division multiplex line with a time division time division multiplex line allocated to the cross point contacts in each case in half of the pulse frame of this reception time division multiplex j the line allocated to the connection concerned are given; On the output side, the time-time channel layers are written in, which means that multiplex intermediate lines ZO, Z6; ...; Z3, 3Z also indicates that only one crosspoint address can be connected to the transmission time multiplex lines abl ... abL via receiving circular memory with one of the duration crosspoint switches, each of which is provided in the Rahcinc's time channel time slot corresponding to the cycle time men one via such a crosspoint switch which cyclically one after the other in the 55 routed connection in each of those individual Zcitkanallagcn in the individual address- periodically successive Zcitfächern over circulation storage crosspoint addresses stored by the relevant one contains, and a comparator during such a connection on the relevant transmission time division multiplexed storage of a crosspoint address The time channel allocated to the line within the pulse in each of the remaining address circulation memories in 60 frames of this transmission time division multiplex line given the relevant Zcitkanalllage are stored coupling. Comparing the four-wire operation of the time division multiplex addresses and corresponding to the occurrence of plex lines, a pair of address equivalents is a double connection to time division multiplex intermediate lines in such a delayed signal. binding included.

The circuit arrangement according to the invention 65 for controlling those coupling point sounders,

hem'ti igt: iko not ever /.citkanallagc its own the one and the same Hmpfangszcitmulliplcx- ■

'/.;ihiei h / w. own /.ishler-Speicherkapn/iUit to the line, and those Koppclpunklsclv.ilter, \

/ ühlnug the respective occurrence of addresses - those on the associated · Sendezcitmulliplexleilung

lying is like this. of the German disclosure SI.

, iegen, is like this ^ ₌ ^^^^ ΑΤίΑ ^

Scripture 1 946 883 known -st, each erJS "^ £ r m. ^ ¹ J" _{over the kUsch one after the other}

_{Circulating address memory} provided so for de the gg ^ g ^ ^ _en . "Den cjnzcI.

Actuation of the Koppe point-like ^ »™osters _{5 nen} Address circular storage W ... UL stored-

Receiving multiplex line "/./ mU the individual 5 _R , _ktatlri T _ssen transferrable gate

Time division multiplexing lines ZO, Z6 ,. .., £., ^ F- _ha , _lum / _£ ^l _{with the} input of the circulating memory B

connectable TJ and to ^Ans S? 5Ä 3 'i "D Plldimsetzer can thereby

connectable bt, and for ^^ tliSeSng «SKJ ^ r Pa ^ Kienumseuer can point switches, via which the ^ a ^ m ^ te * e.tung _AND . _{ülicdcr GD} l ... GBA be formed, de

: Ät ^ X is ^ Ä ^ Ä ^ ^transfer -

_fl "L lying crosspoint switch and the ar, the tragung ^^ gg ^ ^ ^ _drawing can be seen,

Transmission time division multiplex line lieidenNopp AND elements Gßl ... fiB4 on the output side

point switch is a common ad »um au t _S ^ J _{n OR} . _{Member summarized} , _{whose out}

spe.cher UL provided. In this address form the output of the parallel serial converter,

are stored in one from the time table M «g * k gang 8 B ^ _{n ljsch one after the other the} in

German per se known manner (see, for. example rarem _{individually and also com} l _ne n time slot positions in the individual

Schriften, 243 247 1207 452) jewe.b «ι renew the IZnZs ^ LU, * ... UL in Para.lc.form

SU, Me de Adres ^ , _{ktadressen in} Scrienform in

cut those crosspoint switches, y _{P f} ^ _g ^ _n . _{also will} n

via which the respective ^F f P ^fan S ^s . ^b '" _he ^ f | c _t . all the parallel serial converter GBl ... GB 4 in n» ^ iplcxleitung in addition to a «innu ^ parallel form fed crosspoint addresses in multiplex lines led ^connection ^ £ ^ _{en 25} series form the one input of the with its other with a Zcitmultiplex Zwischenleilung ^{composites [5} _{£ i} angeschlosist _{to the} circulating memory B. Jec'im the address circulation storage Ul. .. ul. ic e ^ e, respectively. the Speicherist output side in a likewise known per se = We, e '^ J ^^ _si _] _{SL kon} ^g _{nen as} ^P ch in _aU

uiitiM cm l / vruu> - · - ι ·: .. "der ZeicnnunE aarKCbicm im, ιιαν.ιιν.ιιιαιινΐνι *« · ■ * ... «- ..

ΛgJJ

is on the output side ^ J ^^ _si _] _{SL can} , _{like d}

uiitiM cm l / vruu> - · -. .. ι. ·.: .. "der Z.eicnnunE aarKCbicm im, ιιαν.ιιν.ιιιαιινΐνι *« · ■ * ... "- ..

its outputs to the control inputs Λ «gugen the gJJ ^ _{χ ß} ^ _{hold wide} .

Run coupling point switches via which the relevant _{shift registers ZL} are controlled;

Receptiingszcitmulliplexleitung anl ... anL, mn ^^ _Zc ; _c - _inilil g \ _A da ^ u indicated that the Schlcbe-

single -: ... n Zc; iinu! i.plc ^ .oc.icii.c. ^ »6 |"'"·" ^ ' registerZL on the input side via a clock pulse

... / 3. 3Z is connectable: also J tjedemder [Jg _mU | _n 4 _calculating clock pulses

Address circulating memory L · / .. - ^UL . ^u ° r. _{h o {Ten} . _{35 is} struck, which in the example at a distance of

_{Zöguungselement that follow one another} in (from the German Offen 35 sen g. The adressenumfcuf-

Iegungsschrift 1946883) known W _ei se dimensioned ^l _{eic herindividueUen outputs of the} shift register

can be, a second decoder υαοι ■; ■ ._ " _Z L are also with corresponding outputs

switched, the outputs of which to the ^ "'" J? "^ _{of another} shift register LZ via AND

run those crosspoint switches, linked by α _Glicdcr , the output side via an OR

relevant transmission time multiplex line ασ / ··· control input of the already mentioned

the individual Zeitmult.plexzw.schenlcitungerZö, u are connected: this further

ZO. . , 3Z. Z3 is connectable. According to MJgrteder ^ «^,. ^ _{That in its} sliding volume

in L..TI circulating address memories L · / .. · UL · m ^ ^ _{Schicberegister ZL of the} number L of

tan «, in each case by ^{the A} a ^re *« ° «Adrcsscnumlaufspeicher U / ... UL corresponds

given time division multiplex link 45 ^ _the ^^ ^ _{5 pulse frame duration T and}

Coupling point address of the one currently in ™haben ^a ™ *. _{Number L of time} multiplex lines _fl / i // _fl ft / ... anLlabL

Einhc / ogenen crosspoint switch wcraen u _{corresponding} cycle, ie for example in one

Question coming crosspoint switch ewetls time e ^ p ^ ^ ^ _{5 g = iqqq} ^ _{weUergeschaltet der}

kan.lrichtig periodically closed impulsively ^^^ _{is jn the} - _{n deJ}

/ to avoid ^Do PP ^e ! 7 ^r ^ " ⁿ _a ^g J _f ⁿ _n ; _hme ^ drawing shown before

each only one crosspoint _{address : au take ^^ Ve} ⁶ rgleicher y controlled here. Input side

the circulating memory fl with one of the outer one »- ^. ^ _{d {eser comparcicher v} on the one hand by an irr

channel / side compartment corresponding ^to ' ^a "' ^{/ C1} _in7eln ^fc _en z.eitkanalaltakt, ie for example in the distance before

see, the cyclically one after the other de m dtr '«J« ¹ « _{} üs 125 32 s> switched time} channel counter,

Zc.tkanallagen in each ^Adre ** ^en "™. _KZ ^l _and on the other side by a time channel counter ZA

h ul VL ψ ^^^^^ ΧΙ hl d i i dm product of the pulse

Zc.tkanallagen in the. _{KZ and} on the other hand from a time channel counter ZA

secure ul ... VL ψ ^^^^^ ΧΙ- acted upon in one of the product of the pulse

addresses contains: a tn in * ' ⁰ ^ J ₆ J ₂ . frame duration T and the square of the number L de

represented circuit arrangement by a clock corresponding to Aqui a time multiplex lines. ie for link A followed ^{by a leaf} ^? / _r , o, _{chen 6o} playswcise at a distance of 125-64 - M) (K) .. <

Comparator / i. BZ compares while a socnen γ is _halted . The comparator V compar

Storage of a coupling point address | this mrt ac B _{d to iU each} Zcitkanal supplied

in the remaining ^address ₇ ^sse _t f ^^ f '^ ₁ designations and only gives in each case be <C.lcichhei

Ul UL in the relevant ^ «« »^ g, _{wcier straight to} him on the input side Z, i.

... _u ". other addresses "m.au.spjener ■ ^ - ^ _% ^ ^. ^ ^

W. . . w! in the relevant ^ «« »^ g _{,, wcier} him on the input side straight / ugeguu-r _ ..

secured crosspoint addresses and giW oci λ channel designations an activation sign;.! for de.

-, η address equality a a ^ P ^ '^ ¹ ^ _ch ! Time channel selection switch .VK off. on / off signal. Vue dies door uasmuc ^^^^ ^. ^. ^ _Vorstchl . _nik . _{n jn your} sdialtungslech

nung illustratedL · ^Awführ V ^^ ^P J! jJ ^ i _au HrH: icMicr niche structure K-schricK-nc Schaiiungsanordnuni ** ^ " jOt 639/43 '

9 10

then works on the basis of a system with channel position in the individual circulating address memories 32 time channels per pulse limit of 125 | is duration at Ul ... UL about stored crosspoint or L = 8 time multiplex lines . anLlabL how Intermediate Line Addresses has ended. The following now follows: the time channel counter ZK by one step - The time channel counter is switched off by the comparator V , and a test procedure corresponding to the above selector switch SK initially during the time fan, a first step for the second , designated by the time channel counter ZK, follows Time channel location. In the corresponding time channel closed, namely via LLT the other time channel bearings = 8 ms away. During this time span of 8 ms, checked until after 8 · 32 = 25o ms in all, controlled by the shift register ZL , cyclically io time channel positions are the memory selection switches SI ... SL, Ul ... UL just stored one after the other in the address circulation memory - or a total of eight times each, each for the duration of link addresses on double connections 125 μβ, ie for the duration of an address cycle, and the entire cycle of the test before in the address cycle memories U1 . .. UL, aisles can start all over again,
closed. The actual address comparison can, like the opening of a first memory selection switch which is also indicated in the drawing, with the help of a? considered first time channel position in the associated equivalence element A to which the respective circulating address memory about stored coupling addresses to be compared with each other are supplied in each point or link address via the gate series form and that in each case with circuit E in the circulating memory B. transmitted and 20 correspondence of two corresponding to each other from here repeatedly the comparator A, BZ zu-bits of two with each other just to be compared, so that it emits a counting pulse to a subsequent closing of the remaining memory selection switch with bit counter BZ , which with each Address comparison which begins to count again in the first time channel situation under consideration and the counting increment corresponding to the number of bits per crosspoint or crosspoint or link address, which corresponds to the number of bits per crosspoint or crosspoint or link address, when the remaining circulating address memories are reached itts will be the same. If these comparison processes are terminated after a double connection L - T - 1 rns at its output og , then the signal which is now displayed is emitted during this time. From the irioinenianen second closing of a second memory selection position of the shift registers ZL and LZ and the timer in the considered first time channel position 30 channel counter ZK can now be read off which in the associated second circulating address memory MuHiplexlinien (anl / abl ... AnL / abL) in which stored crosspoint or intermediate double connections are involved and in the line address via the gate circuit E in which time channel position this double connection is transmitted to the memory B and is again from here. For their further evaluation and processing the comparator A, BZ is supplied so that they can transfer this information from the shift registers during the subsequent second closure of the ZL and LZ and from the time channel counter ZK in the remaining memory selection switches with those in the register A1 , Rl, A3 are transmitted, as indicated in the attempted first time channel position in the remaining address drawing.

senumlaufspeicher approximately stored crosspoint · In the above, the invention was compared in the context or link addresses. In a manner corresponding to a PCM time-division multiplex switch known per se, the point of the description is repeated, explained; It should be noted, however, that the above processes for the rest of the memory are not limited to such a switching center, but rather generally in multi-time memory, so that after L · L · T = 8 ms the plex switching systems of the above-mentioned kind examination can find all in the considered first time turn.

1 sheet of drawings

Claims (6)

Patent claims: 1. Circuit arrangement for avoiding double connections in multiplex telecommunication systems, in particular telephone switching systems, in which the addresses of the line sections involved in connections are stored in circular address memories and in which a counting device is used when a comparison device compares line segment addresses with those respectively written in such circular address memories Addresses on connections of participating line sections, if address matches occur several times, emits a signal identifying a double connection, characterized in that in time division multiplex switching systems in which the individual time division multiplex lines (anl... AnL) at least one group of incoming time division multiplex lines (F. the individual time division multiplex lines (abl... abL) at least one group of outgoing time division multiplex lines (transmission time division multiplex lines) via time multiplex exzwisehenleitungen (ZO, Z6, ... Z 3,3Z) using jewei. connectable to a time-division multiplex line and a g Zeilmultiplexzwisehenleiti .- connected crosspoint contactor, and in which each incoming and outgoing time-division multiplex line {anl, abl; . . . . ANL, ABL) an address circulating memory (L7 .. UL) is provided in which in each case by the address of the respective time-division multiplex intermediate line (ZO, 76;.. Z3 37.) addresses given of just the time-division multiplex line (anl concerned, abl;. .; anL, abL) with a time division multiplex intermediate line (ZO, Z6; ...; Z3, 3Z) connecting crosspoint contacts are each written in the time channel layers assigned to the relevant connections, a circular memory (B) that takes up only one crosspoint address and has a duration a time channel time slot corresponding circulation time is provided, which contains cyclically one after the other the crosspoint addresses stored in the individual time channel positions in the individual circulating address memories (LU ... UL) , and a comparator (A, BZ) during such storage of a crosspoint address these with the in each case remaining circulating address memories (UI ... UL) crosspoint addresses stored in the relevant time channel position ver equals and emits a signal indicating a double connection when addresses are identical. 2. Circuit arrangement according to claim 1, characterized in that the initial address memory (L '/... UL) on the output side via memory-selection switch (SI ... SL) and a time channel selection switch (SK) with a parallel-serial converter (GB 1 ... GB4 \ are connected, Jer feeds a crosspoint pressure , fed to it in parallel form, in series form to one input Jes with its other input to the comparator (A, 6, <·, BZ) connected to the circulating chip (B). 3. Jdialtimgsanordnung according to claim 2, characterized in that the parallel sericiuimsetzer (GB 1 ... GB 4) via a cyclically in succession for the coupling point addresses stored in the individual ZeitkanaJlagen in the individual address circulation memories (Ul ... UL) transferable gate circuit ( E) yerbunde.-i is to the input of the circulating memory (B). 4. Circuit arrangement according to one of claims 2 or 3, characterized in that the memory selection switches (Sl. .. SL) are controlled one after the other by a shift register (ZL) which is switched on in the pulse frame cycle. 5. Circuit arrangement according to claims 3 and 4, characterized in that the individual address circulation memory outputs of the shift register (ZL) with corresponding outputs in one of the product of the pulse frame duration (7 *) and number (L) of time division multiplex lines (anlIabl ... anLlabL) corresponding clock further shift register (LZ) are linked via AND gates, which are connected on the output side via an OR gate to the control input of the gate circuit (E) . 6. Circuit arrangement according to one of claims 2 to 5, characterized in that the time channel selection switch (SK) is controlled by a comparison ^ K), the input side on the one hand by a time channel counter (KZ) switched on in the Zcitkanaltakt and on the other hand by one in one of the product from the pulse frame duration (T) and the square of the number (L) of the time division lines (.. anliabl. anLlabL) corresponding clock indexed time channel counter (CC) is beaufs'hlagt and in each case only in case of equality on the input side supplied thereto time slot designations, an actuating signal for the time channel selection switch (SK) surrenders.