DE2145702C3 - Circuit arrangement for converting telegraph characters between a single power line and a double power line in teleprinter systems - Google Patents

Description

The invention relates to a circuit arrangement for converting telegraph characters between a Two-wire operated single power line and a four-wire operated double power line in telex systems, in which incoming double-stream characters are the transmission of incoming Single stream characters and incoming single stream characters the transmission of incoming Prevent double stream signs. This circuit arrangement is particularly applicable in telex exchanges, in those subscriber stations operated with two-wire single current via four-wire double current lines are connected to the exchange and the news transmission of these subscriber stations without triggering the established Connections can be interrupted by counter-writing.

Fig. 1 shows a known arrangement for converting telegraph signals between a two-wire operated single power line and a four-wire operated double power line. This known arrangement consists of the subscriber station Tn and the converter circuit US. The subscriber station Tn is connected to the converter circuit US via the single current line Tl. The lines a 1, b 1 and α 2, ft 2 belong to the double current line via which the converter circuit US is connected to an exchange, not shown. Of the subscriber station Tn, only the transmitting contact SA: and the receiving magnet EM of the teletypewriter Fs and the remote switching device Fg are shown. The converter circuit US contains the telegraph transmitter relay A , the winding I of which is arranged in the line circuit and the winding II of which is arranged in the replica circuit which contains the replica resistor Rn. By means of the send contact sa, the double-current signals to be sent out are delivered via the line a 2, b 2 to the switching center, via which they can be fed to a further subscriber station (not shown).

The double current signals arriving from the exchange via the line a 1, b 1 reach the telegraph receiving relay B, which forwards this double current signal to the subscriber station Tn via the receiving contact b via the single current line T1 as a single current signal. In addition, the converter circuit US still contains the Umschal tkontakte / 1 and II of the relay L. The relay L is used to reverse the polarity of the single current line, so that when the connection is established, the motor of the teletype machine Fj is switched on and the idle current flows through the receiving magnet EM and the motor when the connection is disconnected switched off and the idle state is restored; in addition, the relay L switches on the holding resistor Rh , which prevents reflections from occurring. The relay L has a pick-up delay of about 60 ms and a drop-out delay of about 600 ms. In addition, the converter circuit US contains the relay R with the windings I and II and the associated contacts rl and rl. When the connection is established, the relay R responds with a delay, so that the contact r 1 is only moved from the position shown after a delay time of about 60 ms and the winding I is no longer short-circuited. The relay R has a dropout delay of about 300 ms, so that the holding resistor Rh is no longer connected when the final signal is given. If the holding resistor Rh were not disconnected in time from the subscriber station Tn after the terminating signal was issued, a disconnecting current polarity sent by the exchange would trigger a signal which would be transmitted to the exchange via the lines al and bl and interpreted there as a terminating signal.

In the following text, binary signals are often mentioned, with the help of which one of two binary values is transmitted. One of these binary values corresponds to the character stream polarity, which is referred to as a 0 signal. The isolating current polarity, which is referred to as a 1 signal, corresponds to the other binary value. The illustrated position of the contacts represents the state of rest, during which no messages are transmitted and via which the lines al, bl and al, bl are thus each emitted 0 signals (character stream). When the connection is established, i.e. in the write state, a 1 signal (isolating current) is transmitted over the lines al, bl and al, bl. The line current is set with the aid of the line completion resistor R 1. The replica resistance Rn is used to compensate for minimal reception distortion.

The in F i g. 1 shown known arrangement has the disadvantage that it works with several relays, which require maintenance at certain time intervals and are therefore undesirable. To the connection To be able to interrupt by counter-writing, special relays have to be provided with specific Entitlement and dropout delays may be provided.

The invention is based on the object of specifying a circuit arrangement of the A ^ t mentioned at the beginning, which operates with a smaller number of relays and is characterized by low technical complexity. In particular, the invention is based on the object of specifying a circuit arrangement which does not require the relays A, B and R of the known arrangement.

According to the invention, in a circuit arrangement of the type mentioned at the outset, one is in the incoming circuit Four-wire branch arranged logic circuit is provided, which with the simultaneous occurrence of character current state in the outgoing four-wire branch and isolating current state in the incoming four-wire branch the device in the Separating layer.

In contrast to this, in the case of the FIG. 1 dar-

provided arrangement with the simultaneous occurrence of the character current state in the outgoing four-wire branch and the isolating current state in the incoming four-wire branch, the double-current characters arriving via the lines al, bl in single-current

characters are implemented and the device implementing them, i.e. the telegraph receiving relay B, is not held in the separating layer.

The invention is characterized in that reflections are prevented without a time over-

ao monitoring using the relay R according to FIG. 1 must be carried out, which only responds after a delay time of 60 ms and drops out after a dropout delay of approx. 300 ms. The omission of the relay R in the invention results

as thus a simplification of the signaling process. This is particularly advantageous when using the invention in connection with an electronic Switching system that works with higher transmission speeds. The invention enables the withdrawal of the final character at any time.

It is expedient to provide a logic circuit as the device, which has a single-current-side Has input and output and a double-flow input and output each. This logic circuit

contains a trigger stage, the input of which is connected to the tap a voltage divider and is connected to the input and output on the single-current side and the output of which is connected to the output of the logic circuit on the double-current side. Also is a transistor stage is provided, the emitter-collector path in series with the voltage divider to the Pole of the operating voltage source is connected. The input on the double-flow side and the Double-current-side output of the logic circuit connected to the base of the transistor stage via a gate.

The logic circuit is characterized by the use of electronic components in place of the mechanical telegraph relay off. In the invention, only a single relay is used, which the Reverses the polarity of the single current line. This relay works when establishing a connection and when The connection is only disconnected once and is therefore largely maintenance-free.

In the following, exemplary embodiments of the invention are illustrated with reference to FIG. 2 to 4 explained, where Identical objects shown in several drawings are identified by the same reference numerals are. Show it:

F i g. 2 shows a first exemplary embodiment in a basic representation,

F i g. 3 timing diagrams of signals and switch positions, on the basis of which the operation of the in FIG. 2 illustrated arrangement is explained and

F i g. 4 shows a second exemplary embodiment in a circuit diagram.

F i g. 2 shows the logic circuit LOG, which is connected on the one hand via the circuit point c and via the

5 6

Switching contacts u 1 and u 2 to the subscriber station Tm signal Ek = I at the base of the transistor T1 is this

and on the other hand via the circuit point d or e conductive, and the operating voltage Ub is applied to the

to the double current line SD or to the gate G 4, two resistors R 3 and R 4 are shared. It is

connected. The double current line ED is the amount of the resistor R 4 significantly greater

on the one hand with one input of the gate G 4 and 5 as the amount of the resistor R 3.

on the other hand with the input of the time stage L. The states of the trigger stage Tr, in which this

bound. The relay U controls the contacts μ 1 and emits a 0 or 1 signal via its output,

u 2. The logic circuit LOG consists of the trigger, which is referred to below as a 0 or 1 state,

stage Tr, the transistor Tl, the voltage divider The threshold value of the trigger stage Tr is set so that

from the resistors R 3 and R 4 and the NAND ίο that the voltage drop across the resistor R 3 and on

Gate Eq. Collector of transistor Tl with applied 0-Si

If a 1 signal on the input side of the timing stage L is not sufficient to put the trigger stage Tr in its signal, for example a signal with a positive isolating current 1 state. On the output of the Trigpolarität, long or shorter 60 ms applied as then gerstufe Tr and the line SD a 0 Siwird via the output of the time stage L is thus output is a 1 signal 15 gnal so negative sign current polarity, or O -Signal issued. If at the input of At time / 1 the subscriber at the time stage L expresses an 0 signal, as a signal from the negative subscriber station Tn , to send out his wish to send a telex character stream polarity for longer than 600 ms or shorter. The calling subscriber presses a 600 msec, then a 0-signal or a 1-signal is emitted via the output of the timer L arranged in the remote switching device Fg , ao call button, and the "send contact Sk is closed-De ₁ output of the time step L is connected on one side with the so that the remote switching device Fg of the relay U and on the other hand, flowed through with current JM 4OmA is the operating quiescent working winding sen. the contacts the exclusive-OR gate G 4. «1 and« 2 are in the fully marked location.

In the following, the mode of operation of the in F i g. 2 The voltage drop in resistor R 3 increases. arrangement shown on the basis of the in F i g. 3 represents »5 and the trigger stage Tr flips into the 1 state and explained timing diagrams. In FIG. 3, a 1-signal is sent to the switching center via its output. The signals with the same reference symbols are given. The exchange recognizes the call net as well as the lines over which the signals in FIG. 2 of the subscriber and sends its part at the time to be transmitted. For example, the in Fig. 3 ti a selection request pulse ED with a signal ED shown via the in F i g. 2 shown 3 ° duration of about 25 ms. Transferred to the election request line ED. The two binary values of the pulse at time 12 have the effect that the output signal ED is shown in FIG. 3 with the reference symbol 0 of the gate G 1 a 0 signal is emitted, wound 1 is shown. The in Fig. 3 shown Si through the transistor T1 for the duration of the selection signal U relates to the relay U, whereby the demand pulse blocks and the current Jm below the 0-value the switched-off state and the 1-value 35 is broken. The interruption of the current Jm means that the relay U is switched on. is evaluated by the remote sound device Fg as a selection request. The signal Ek characterizes the mode of operation of the evaluated, and a transistor T1, not shown in FIG. At time 1 3, the or 1-value of the blocked or the conducting calling subscriber dials the call number of the desired emitter-collector path of the transistor T1 ent- 40 subscriber. After the exchange spoke to the. The in Fig. 3 has called the called subscriber in the diagram EM shown in FIG. 3, it sends a 1-signal to the ruk, identifying the operating state of the subscriber shown in FIG . According to the The time step L tilts in its 1 state, since a 1-Si-0 or 1 value is the recom- shown in Fig. 2 gnal longer than 60ms is applied, and after a duration capture magnet EM respectively with no current . with current 45 of about 60 ms, at time point 1 5 there is a flow through the outlet. The diagram SK and its 0 or transition of the time stage L emitted a 1 signal. The Re-1 values characterize the open or closed relay U responds and places the contacts u 1 and u 2 in the contact path Sit in FIG. 2. In Fig. 3 below is the position shown in dashed lines. The on-course of the current JM is thus shown with the polarity reversed with the maximum power line Tl. The current Jm flows with amplitudes of + 40 mA and minimum amplitudes 50 from time r5 onwards in the other direction through from −40 mA. the remote switchgear Fg, and the motor of the remote

Up to the time 1 1 and the degraded state typewriter Fi will start. At time / 5 is

the connection between the subscriber station Tn thus the connection between the two subscribers

and the exchange displayed. The lines are built up and the write status is reached. Dei

SD and ED each transmit 0 signals. The motor 55 subscriber at the subscriber station Tn writes. There:

the teletype machine FS is at a standstill, and the first send 0-Signa sent out by the calling subscriber

contact Sk is open. The remote switching device Fg causes a 1-state of the trigger stage Tr, so dat

from a small negative quiescent current Jm through the gate G1 receives a 1-signal and also from

raft. Output of the gate G1 a 1 signal to the Tran

Since a 0 signal is transmitted via the line ED 60 sistor T1 is output, which lei the transistor T1

is also due to the two inputs of the generic power. This interrupts the line ED

ters G 4 in each case 0 signals, and via the output chen, and the transistor T1 remains in

of the gate G 4 is a 0 signal to the gate G 1 conductive state.

transfer. At the time / 6, the called remote part also expresses a call via the SD line

0 signal is transmitted, the two recipients at the remote station have the wish to be in the order

went the gate Gl in each case 0 signals, so that in the opposite direction via the line ED signals zi

whose output is a 1-signal, like that transmitted. The remote participant does not press one

shows signal Ek shown in Fig. 3. Key on his teletypewriter, un <, represented by the Si

7 8

an O signal arrives on the line ED. As long as schineF.v writes. Between the times / 16 the calling subscriber emits a 1-signal, occurs and / 17 the remote calling in this case writes no effect of the subscriber received via the line ED. At the time / 17, the learned part enters the O-signal. Only at the time / 7 is the transmitting party has the clearing signal, so that the Vermittkontakt closed Sk, the trigger stage Tr is responsive, 5 of the subscriber station switching center Tn at the receiving and at the transmitting line SD is a 1 signal exceeds line ED is an O -Signal transmitted. After a contract. At this point in time the gate G 1 is given a delay time of about 600 ms at the time when an O signal is output at the output point / 18 the time stage L is triggered, and the relay U drops and the transistor T 1 blocks. From the point in time / 7 onwards and puts the contacts u 1 and u 2 back into the position, the transmission line SD is no longer fully marked on the transmission cone. At the time / 19 is the clock-SA: connected, and it is degraded regardless of connection, and on the transmission line SD 1 constantly a-Si and on the receive line ED is transferred to the position of the transmission contact Sk respectively gnal 0. The punched tape, not shown, transmits signals.

The transmitter in the teleprinter Fj is indicated if necessary. 4 shows a further embodiment. It stops. From time / 8 onwards, the remote part 15 in FIG. The transistor stage shown in FIG. 2 with the subscriber via the exchange to the calling sistor Tl correspond to the transistor Tl, subscriber in FIG. The transistor 7 "1 opens and closes the resistors R 17, R 18 and the capacitor of the received steps, C 3. The RC element with the resistor R 18 and via the receiving magnet EM becomes the capacitor C 3 attenuates the voltage spikes captured by the message printed 20 at that from the inductance of the teletypewriter

At the point in time / 9, the calling part now gives origin, and thus protects the transistor T 1 from receiving a counter-write signal via the transmission of a destruction. Via the terminals / and g , the point at the remote subscriber (not shown) is available, the subscriber in question with his or her in FIG. 3 shows the remote control device Fg and its teletypewriter Fj connected by actuation of a key and the machine Fj connected by opening the transmission clock Sk. About the Umschaltkonschscht. As soon as the send contact Sk is open via clocks u 1 and u 2 , the single current line around the receive line ED receives a 1-signal, polarized. With the resistor R 36 the line became what is the case at the time / 10, the tran- current, which is blocked by the supply voltage of + 120V sistor T 1. This means that what is generated for the opened one can be set to a certain value. Transmitting contact Sk corresponding to a 0 signal by turning the 30 shown in FIG. 2 trigger level of the trigger stage entspresprechen Tr Tr on the transmission line SD chen in F i g. 4 of the operational amplifiers OP that are given. The conductive connection of the emp- resistors R 5, R 6, R 7, R 8, R 9, R 10, R 11, R 12 interception line ED to the circuit point Ek is under- and R 37, the capacitors C 1 and Γ 2 and which break, so that a Zener diode Zl at the output of gate G1. An out of 1 signal is emitted in front of the trigger stage and transistor T 1 is conducive to resistor R 37 and capacitor C1. From time / 10 onwards, the standing low-pass filter is arranged, which flattens the edges of the calling subscriber to the called remote subscriber - incoming telegraphing steps, so that mer in the remote station. Prevents bruises and the influences of induction

At the time / 11 the calling participant gives the activity of the receiving magnet on the curve shape a final sign. To do this, he presses his final 40 the telegraphing steps are eliminated. With this key in the teleprinter Fs and sends a low-pass filter, dynamic protection is achieved, with a 0-signal. After a period of about 350 ms rend with the resistor R 10 and the Zener diode - at the time / 12 - the switching center recognizes that Z1 has reached static protection. In the locked final signal and in turn sends to the subscriber state of the transistor T 1, a 0 signal arises with the resistance. Here, at time / 13 45, R 37 and the capacitor C1 at the low-pass filter speak for the time stage L to full operating voltage of + 120V after a duration of about 600 ms. The 0 signal via the counter and emits a 0 signal. The residual R 7 becomes the current and with the help of the Zener relay U drops and controls the contacts 1 and u2 diode Z1, the voltage back to a permissible value in the fully drawn position. The single limited, occurring interference voltages direct current line Tl is polarized back again, and it 50 are also limited in time. The resistors R 8, the idle state prevails: the motor of the telex R 9 and R 10 cause positive feedback on the opera machine Fs is switched off and the transmission line amplifier OP, so that the amplifier already at SD and the receiving line ED transmit very small input voltages . With the 0 signals. Capacitor C 2 is the positive feedback of the amplifier

From the time / 13 to the time / 14, the OP was improved dynamically. With the resistors

the diagrams in FIG. 3 on the down- R 5 and R 6 is added to the voltage

established connection. If the remote participant wishes to set a threshold of + 120 V, this is set on the ne

mers, with the subscriber station Tn in a writing input of the operational amplifier OP zui

connecting will come after choosing the effect. Only when the input voltage

Call number of the subscriber station Tn from which Vermin 60 exceeds this threshold value, the Opera speaks

control point sends out a 1-signal, which reacts to the input signal an and ar on the amplifiers OP

bypass line ED occurs at time / 14. After working as a trigger level. The rectangular out

A delay time of about 60 ms gives the timing signal passes through the resistor RIl

stage L at time / 15 via its output on the transmission line SD. The one shown in FIG

1 signal off, the relay U responds, and the 65 gates G 4 correspond in FIG. 4 the transistor T 2

Contacts u 1 and u 2 in the dashed lines the resistors R 13, R 19, R 20 and R 21, ie

ncten situation is reversed the F.infachstromleitung Tl, the zener diode Z 2, the diode D 3 and the contact u '.

so that the motor starts and the teletype machine appears at an exclusive-OR gate at the Au

ίο

output a 1-signal if one of the inputs receives a 0-signal and the other a 1-signal. This means that when relay U responds and thus when contact u3 is actuated, only the voltage on the receiving line with the possible 0 and 1 signals is fed either directly or negated to the second input of NAND gate G 1.

The receiving line ED is connected directly to the diode D 2 via the resistor R 13 when the contact u 3 is in the position shown in dashed lines. In the fully drawn position of the contact u 3, the voltage occurring on the receiving line ED is negated in the transistor 7 3 and fed to the diode D 2 via the resistor R 19. A threshold value is set with the diode D 3 and the Zener diode Z 2, so that, on the one hand, a reliable blocking of the transistor Γ 3 is achieved and, on the other hand, a response in the event of smaller interference voltages is prevented. The input current is limited with the resistor R 20, and the reverse voltage is supplied via the resistor R 21. If there are 0 signals at the two diodes D 1 and D 2 or if the combination of an 0 signal and a 1 signal is present, the gate becomes permeable and the transistor T 2 becomes conductive, which then also the transistor Tl controls in its conductive state. The in F i g. Gates G 1 shown in FIG. 2 correspond to FIG. 4 the transistor 72, the diodes Dl and D 2 and the resistors R 14, R 15 and R 16. With the help of the resistors R 15 and R 16, a threshold value is set that safely blocks the transistor T 2 and its control in the conductive State prevented by small interference voltages. The resistor R 17 enables a safe blocking of the transistor 71. The time stage L shown in Fig. 2 consists in Fig. 4 of the transistors Γ 4, Γ 5, Γ 6, Γ 7, Γ 8 and 7 9, the resistors R 22, Λ 23, Λ 24, R 25, Λ 26, R 27. R 28, R 29, R 30, R 31, R 32 and R 33, from the capacitors C 4 and CS, the diodes D 4, D 5 and D 6 and the contact u 4. The relay U only responds if the in F i g. 2 time stage L shown responds with a delay of 60 ms or with a delay of 600 ms. Switching to one of these two delays takes place with the help of contact u 4 of relay U. The two delay times of 60 ms and 600 ms are formed with capacitors C 4 and C 5 and the associated charging and discharging resistors. The relay XJ is energized in the idle state. When the connection is established, the power supply for the relay U does not need to generate any current.

In the dismantled state, the contact u 4 is in the position shown in dashed lines. A 0 signal is transmitted on the input line ED , which keeps the transistor T 3 in its conductive state. The diode D 4 is conductive and a voltage of 24 V is applied to the resistor R 23. The capacitor C 4 is discharged because the potential of + 12V is applied to both of its electrodes. The diode D 5 and the transistor T 4 are blocked.

When the connection is established, the receiving line ED receives a 1 signal. The transistor 7 4 and the diode D 4 are blocked. The capacitor CA is thus charged to a voltage of -12 V via the resistor R 23. At the base of the transistor T 4, a high-speed value of approximately -5 V is set using the resistors R 25 and R 26, and when this value is exceeded, the transistor T 4 becomes conductive due to the capacitor discharge. The threshold value is reached after a period of about 60 ms. The transistor 74 is in its conductive state, and the charge is held in the capacitor C 4. The two downstream transistors T 5 and 7 6 form a so-called Darlington stage, which causes a current gain equal to the product of the two individual current gains of the two transistors. The transistors 7 5 and 76 are made conductive so that the diode D 6 is blocked. The transistors 7 7, 7 8 and 7 9 are located

ao is now in the locked state, the relay U drops out, and the contact u 4 is switched to the fully drawn position. The capacitor C 4 is thus switched off.

When the connection is terminated, the receiver

»5 interception line ED transmitted a 0 signal, so that the transistor 7 3 and the diode D 4 are controlled to be conductive. The diode D 5 and the transistors 7 4, 7 5 and 7 6 are blocked. Since the transistor 7 6 was previously conductive, the capacitor C 5 is discharged. By blocking the transistor 76, the capacitor C 5 is charged to a voltage of -12 V via the resistor R 28. As soon as the threshold value set with resistors R 31 and R 32 is equal to the capacitor charge, the transistor 7 7 becomes conductive and holds the capacitor charge at the response value. As soon as the relay U drops out and the contact κ 4 reaches the fully drawn position, the capacitor C 5 is rapidly discharged via the transistor 7 6, which is controlled by the input line ED. The high discharge current is applied by the Darlington stage with transistors 7 5 and 7 6. In the write state, the capacitor C 5 is charged during the step duration; however, the response threshold of the transistor 7 7 is not reached. The charged capacitor C 5 must be discharged within one step, so that with an input current of about 100 μ in transistor 7 5, a current gain of about 1000 is required to ensure rapid discharge.

is performing. This is achieved with the Darlington stage. The resistor R 29 is used to limit the current for the Darlington stage with the transistors 75 and 7 6 when the capacitor C 5 discharges. The diode D 7 in parallel with the relay U protects the transistor 7 9 from voltage peaks caused by the inductance of the Relay winding occur. It would also be conceivable, instead of the in FIG. 4 shown timing stages with the transistors 74 and 75, 76, 7 7, 7 8 and 79 to use a differently constructed timing stage without changing the operation of the arrangement.

1 sheet of drawings

Claims (8)

Patent claims: 1.Circuit arrangement for converting telegraphic characters between a two-wire single current line and a four-wire operated double current line in teleprinter systems, in which incoming double current characters prevent the transmission of incoming single current characters and incoming single current characters prevent the transmission of incoming double current characters, especially in teleprinter single current switching systems in which two-wire single current switching systems are operated Subscriber stations are connected to the exchange via four-wire double current lines and the sending of messages from these subscriber stations can be interrupted by counter-writing without triggering the established connections, characterized in that a logic circuit (LOG) arranged in the incoming four-wire branch (ED ) when a character stream state occurs in the outgoing four-wire branch ( 5D) and isolating current state in the incoming four-wire branch (ED) which shows the incoming single current signal hen in the double stream symbol converting device (71) holds in the separating layer (by means of Eq). 2. Circuit arrangement according to claim 1, characterized in that the logic circuit (LOG) has a simple current-side input and output (c) and a double- current-side input (d) and output (e) and contains a trigger stage (Tr) whose input is connected to the tap of a voltage divider (R 3 / R 4) and to the single-current-side input and output (c) and the output of which is connected to the double-current-side output (d) of the logic circuit (LOG) , and that the double-current-side input (e ) and output (d) of the logic circuit (LOG) is connected via a gate (Gl) to the base of the transistor stage (Tl), the emitter-collector path of which is connected in series to the voltage divider (R 3 / R 4) to the poles of an operating voltage source (Ub) is connected (Fig. 2). 3. Circuit arrangement according to claim 2, characterized in that a gate (Gl) NAND gate is provided (Fig. 2). 4. Circuit arrangement according to claim 2, characterized in that the double current line (ED) provided for the incoming signals is connected on the one hand directly to the input of a second gate (G 4) and on the other hand to the input of a timer (L), that the output of the second gate (G 4) is connected to the double-current-side input (e) of the logic circuit (LOG) and that the output of the timer (L) is connected to a relay (U) that reverses the polarity of the single-current line (Te) (F i g. 2). 5. Circuit arrangement according to claim 4, characterized in that the second gate (G 4) an exclusive OR gate is provided (Fig. 2). 6. Circuit arrangement according to claim 4, characterized in that the single-current-side input (c) of the logic circuit and a pole of the operating voltage source via a first and second switching contact («1, u2) of the relay U to a remote switching device (Fg) of one of the subscriber parts (Tn ) are switched on (Fig. 2). 7. Circuit arrangement according to claim 4 and 6, characterized in that a second transistor (T 3) is provided as the second gate (G 4), the base of which is connected to the double-current input line (ED) , the collector of which is connected to a third switching contact (u3 ) of the relay (U) is connected and its emitter is connected to a pole of an operating voltage source, that the normally closed contact of the third switching contact (U 3) is connected to the double-current-side input (e) of the logic circuit (LOG) (Fig . 4) . 8. Circuit arrangement according to claim 7, characterized in that two timing elements are provided as the timing stage (L), which cause different delay times that the relay (U) has a fourth switching contact («4), which is in one position of one of the two timing elements with a first delay time (60 ms) and in the other position the other of the two timing elements switches on with a second delay (600 ms) (FIG. 4).