DE2129268B2 - Control circuit for channel requests - Google Patents

Description

The invention relates to a control circuit for channel memory requests according to the generic term of claim 1. Such a device is known from DE-OS 19 56 604. In the said However, institutions are not priority institutions for assigning a certain priority to the different channels described. It is also disadvantageous if one is common to all channels Channel trunk is occupied by a certain channel for too long.

From DE-AS 11 52 837 a control circuit for channel requests is known which uses a priority device. If call signals from several data channels are present at the same time, the priority circuit selects the data channel for connection that has priority over the other channels that are also calling due to a defined order of priority. For this purpose, each of the channels is associated with an appealing to a call signal of the data unit of the channel data channel flip-flop and the outputs of this data channel flip-flops control a number of "> data channels corresponding number coincidence stages, where the connection of the terms of priority preferable data channel causing Ausgangsflipflops are assigned. The output flip-flop of the selected data channel is reset when the data unit of this channel has ended its data transmission and the next lower priority channel can then be selected in the previous selection

ι · Step into action. There are additional requirements of the selected channel blocked during data transmission.

The speed of operation of the above device is limited by the fact that requests are made one after the other are processed, each time being required as the information transmitted can have any total length. The control circuit with the incoming line remains so throughout the channel request

i- blocked given time.

A blocking device for blocking the remaining channels while a selected one is being operated Channel is also known from DE-OS 14 87 826.

The invention is based on the object of delaying the acceptance of channel requests and to make better use of the collecting lines common to all channels.

This task is achieved according to the features specified in the characterizing part of claim 1

i ^r ) solved.

The invention achieves the advantage that channel requests from different channels in each case can be accepted after a storage cycle. This eliminates the need for storage facilities to be provided for buffering the channel requirements. It also prevents a certain channel the common channel trunk too often used.

Further advantageous developments of the invention

■ 45 can be found in the subclaims. The invention will now be described in more detail with reference to an embodiment shown in the figures. It shows

1 shows the block diagram of a data processing system,

2 shows the channel control and priority logic of the in F i g. 1 shown memory controller and

F i g. 3 shows a time diagram of the functional sequences in the FIG. 1 memory controller shown.

The in F i g. 1, in which the present invention can be used, consists of a memory controller SCL) 10, which is connected to the channels 12 and 14 via multiple channel bus lines, a central processing unit CPE 16, a buffer memory 18 and a main memory 20. The memory controller 10 monitors the data and address paths to the central processing unit CPE, to the I / O channels and to the system console. The memory controller 10 includes

μ in particular a channel control 22 for priority control of the channels and to control the timing of the channel requests as well as a storage bus control logic 24 to control the

Data flow and addressing of the main memory 20.

The input / output channels are connected to the memory controller 10 via multiple channels tied together. Memory addresses and data are transmitted over these bus lines, although it is not it depends on which channel this information comes from. In addition to these multiple manifolds for the flow of information are controls between the channels and the memory control as tu Interfaces provided.

To gain access to memory 20, channel 12 or 14 asserts a signal on a channel request line. The channel controller 22 responds to this request in that the channel with the highest li priority can gain access to the controller, while all channels with lower priority are switched off. The channel which receives priority immediately receives a signal from the channel controller 22 on the respective response line. The channel then gives 2t> the memory address to the outgoing address bus and the data to the outgoing data bus. The address is chert from the channel memory address register CSAR and the data in the memory channel manifold Register CSDB gespei- 2 ^r>. It can happen that at this point in time the main memory is occupied by other requests and that the address and files have to be stored in the registers mentioned for some time. However, it is not necessary for the channel to keep the address available on the multiple bus until access to the memory can be obtained, and the bus is therefore free immediately after the above-mentioned information has been stored in the above-mentioned registers. The greatest delay time that can occur because the memory is occupied. is one storage cycle. This means that the device is able to accept a request in every memory cycle. If a new channel request arrives, the channel controller 22 responds immediately to this request, even if the two registers CSAR and CSDB are occupied for one memory cycle. At the end of this storage cycle, the information of the new request is placed in the two registers mentioned and the channel control is free to respond to 4 ^r > new requests.

The core memory address bus CSAB (FIG. 1) provides the address path for memory operations from the main memory to the central processing unit, as well as for transfers of blocks of Double words from main memory to buffer memory and from store or fetch requests to the or from main memory from the system console or channels.

Via the accumulator collecting line SB! the data for all storage operations are transferred from the central Processing unit CPE and the system console either to main memory or to buffer memory and all store operations into main memory from the channels. Via the output data> o All data from the buffer memory and main memory run through the central bus line SBO.

Channel requests only affect main memory. In the channel memory address register CSAR 30 the address of the channel is kept available until the b ^r> requested memory module is free. In order to prevent the system from being overloaded by channel requests, the channel requests are given the highest priority on the bus lines of the memory controller 10.

Store operations from the channels only go to main memory. In addition, it is determined whether the data of the relevant main memory address are also in the buffer memory. If that's the case. so the block containing the word in question is designated as valid in the data allocator in question and words in this block can then no longer be fetched from the buffer memory before this block has been transferred again from the main memory to the buffer memory and is thus ensured that the latest information is always in the buffer memory. The memory control ensures that blocks of eight double words are transferred from the main memory to the buffer memory.

The channel controller 22 is described in greater detail in FIGS. 2A and 2B. For this purpose will also Referring to the timing diagram of FIG. 3 taken. For the description of a channel. which in the present Embodiment can be used, e.g. B. Reference can be made to U.S. Patent 34 88 633.

A memory request from one of the channels 1- N is e.g. B. is received via the request line 120 of the channel 1 and sets the relevant channel request interlocking circuit 124 via the AND element 122. This interlocking circuit 124 sets the relevant channel request toggle switch 126 . It is assumed that the channel trunk is originally not busy and that the channel seizure toggle switch 128 is therefore not set and the line "block all channel requests" 130 is at logic "1". The output signal of the respective channel request flip-flop reaches therefore via the AND gate 132 to the priority logic 134. If at the same time reach several Kanalanforderungssignaie this priority logic 134, the signal of the channel is assumed to be the highest priority and then the priority logic 134 generates on one of the output lines 138 a signal. This signal then sets one of the flip-flops 140, whereby a response to the request signal of the channel is initiated. The output of the relevant flip-flop 140 also sets a flip-flop 142 which indicates that the request for the relevant channel is being processed. This also switches off the AND element 122, so that no new request can be accepted from the same channel until the request for this channel has been carried out. The output of flip-flop 140 is fed back to the relevant channel via line 144, thereby indicating to the channel that it has been given priority. After a certain switchover delay, the channel responds by putting a memory address on bus 36.

The priority logic 134 also sends a signal to the "channel priority cycle" line 148, which sets the toggle switch 128 and thus prevents further channel requests (via line 130) since the channel trunk is no longer busy. The signal on line 148 also sets the execution counter 150 in operation. This counter controls the operations during a storage cycle and is divided into 12 sections. Said memory cycle can e.g. B. take 780 nanoseconds.

If an original idle state is assumed, the memory controller responds to channel requests.

by placing a signal on response line 144 within approximately 60 nanoseconds. In the case of several simultaneous channel requests, the memory controller always accepts a request every 780 nanoseconds, ie after each memory cycle. However, requests from the same channel are limited by the flip-flop 142 to one request per three memory storage cycles, thus avoiding blocking of the memory as a result of repeated requests from the same channel.

When the channel receives a signal on answer line 144 , it puts the memory address on channel address bus 36. Execution counter 150 is activated and at time 12 generates a signal on output 152 that bus valid timer circuit 154 is operative puts. This timer circuit produces four output signals. The first output 156 brings the channel address from bus 36 to register CSA R 30.

The "I / O valid" line 152 also activates the memory control priority and memory access control 158 , thereby starting the main memory store or read operation. At the same time, the signal on this line resets flip-flop 140 and flip-flop 128 , thereby allowing the channel request to be processed.

The signal on line 144 is fed to an encoder 160 which converts the corresponding channel number into a binary number. This binary number is then stored in a stack 162 for buffering. When this binary number appears at the output of the stack 162 , it is passed on the line 164 to a decoder 168, whereby an output signal corresponding to this channel is generated.

The timing of the main memory also controls the response to the channel requests. At the time of I / O bit position 8 of the main memory timer circuit, the output signal 170 of the decoder 168 is fed to the flip-flop circuit 174 via the AND gate 172. This generates a signal on line 175 "channel N-conductor" which is fed back to the channel. At the same time, a signal on the line "Address check for channel" 180, "Memory protection violation for channel" 182 and "Invalid address for channel" 184 is fed to the channel.

At the time of the I / O bit position 11 , an AND element 186 is switched through and thus sets the interlocking circuit 188, as a result of which a signal on the line "set CSBO" 190 is generated. The signal on the line 190 takes the data on the Speicheraus- transfer bus line 48 to register CSBO 26, which then transfers the data to the channel data bus 32

For a storage operation, the timer circuit 154 advances to position 4 and thus generates a signal on the output line 19Z. This signal brings the channel data to the data bus 34 and thus to the register CSDB 28.

At the time of the I / O bit position 12, one of the AND gates 194 is switched through, specifically depending on which of the flip-flops 174 is set and thus resets the flip-flop 142 corresponding to the channel. This creates the possibility that the next pending request of the same channel is brought to the latch circuit 124 and to the flip-flop circuit 126 . The flip-flop, which indicates that the channel bus is busy, is reset by the signal at output 12 of the execution counter, whereby the request

■ "> on the Promotion of the AND gate 132 can move to the priority logic 134th If a channel request is pending, a channel priority cycle 148 is performed and ählcr 150 in turn set in motion the execution /.

In [ ^r ig. 3 becomes the functional sequence for two

in channel requirements (a). (b) shown. Both requests arrive on channels 1 and 2 at the same time. as can be seen from Fig.3. At the beginning the trunking line is not occupied and therefore the flip-flop 128 is reset (j). The channel memory requests toggle the respective channel request latches 124 (c), (d), thereby setting the respective channel request tumblers 126 (e), (f). The priority logic 134 generates a channel priority cycle

- ° (g). thereby starting the execution counter 150 (m). At the same time, the flip-flops 128 are also set (j). The channel bus remains busy during a memory cycle or during the run time of the execution counter 150 .

One of the two channels is given priority via the priority logic 134. It is assumed that in this example channel 1 has a higher priority than channel 2. The priority logic 134 therefore generates a signal on the line 138, as a result of which the flip-flop 140 is toggled (h). The flip-flop circuit 142 is also set by a signal on this response line, which indicates that a request for this channel is being carried out. This toggle switch remains occupied until a further switching signal (x) is fed to this channel 1. No further requests are accepted from channel 1 until the flip-flop 142 is reset, since the AND element 122 is inhibited.

Channel 1 recognizes the signal on its response line and then forwards the main memory address to the channel address bus 36 (n) and the channel data, in the case of a store operation, to the channel data bus line 34 (u). The I / O valid signal (p) from the execution counter 150 starts the timer circuit 154 (q). The output 156 of this timer toggles a CSAR latch (r). The I / O HI priority output from circuit 158 (Fig. 2B) enables certain gates.

whereby the contents of the register CSAR on the main memory address bus CSAB and a Buffer address bus is given

The output of position 4 of the timer circuit 154 places the data on the channel data sample line into the CSDB register 28 for a store operation (v). In addition, the data is aul the storage input manifold SBl brought (w) (see also Fig. 1).

At the time of I / O bit position 8, a signal on the »Channel 1 Next« line (x). For a retrieval request, the Output data given to the memory output collecting line SBO (see also FIG. 1). At the time 11, a CSBO interlock circuit is switched on and thereby brings the data on the memory output bus SBO to the channel data bus. At time 12, a data verification lock is

control circuit switched on (cc).

The execution of the request for channel 2, which occurs at the same time as the request for channel 1 arrived, the start is made as soon as the execution counter 150 has reached position 12, i. H. as soon as a Storage cycle is over. At this point the trunking toggle switch is reset (j), whereby the output signal (y) "CONTINUE TO CH 2" can be brought to the priority logic 134. It a channel priority cycle (g) then begins, as a result of which an answer signal is fed to channel 2 (i). This sets the toggle switch corresponding to channel 2, which indicates that this channel is busy and the request for channel 2 can now be carried out (I).

Channel 2 then sends an address (o) and the further execution of the request is carried out as follows described above in connection with channel 1.

In summary, it can be said that channel requests as soon as they are received by the memory controller 10 arrive in one of the channel request latch circuits 124 should be kept ready. This creates the opportunity to wait for it until the addressed memory module is free and the

This frees the trunking line to transmit another channel request. The next requirement is accepted within a storage cycle and subsequent requests are also made each accepted within a storage cycle. This provides an adjustment between the main memory channel connection and main memory operation achieved.

When a channel with a relatively low priority is given access to the channel trunk, will the bus is occupied for one storage cycle. In such a situation, a third troublesome channel is created the fourth priority is assigned and this channel must therefore be accessed for a relatively long time Memory waiting. If, in this situation, the basic memory module required by this memory is also available is still busy, the channel overflows. The risk of such an overflow is illustrated by that shown in FIG. 2A Overflow detector logic is detected and a flip-flop is switched on, which accesses the central processing unit to the main memory for a certain number of machine cycles prevented and thus frees the memory for said third drum channel.

For this purpose 4 sheets of drawings

Claims (5)

Patent claims: 1. Control circuit for channel memory requests with a priority logic for resolving conflicts of simultaneous channel requests and with devices for storing the channel request signals and the output signals of the priority logic, characterized by a first register (30) for receiving the memory address requested by the channel, by a second register ( 28) for receiving the data supplied by the channel and by a counter (150 ) triggered by the output signal (148) of the priority logic (134) to count the time of a memory cycle, the output signal (152) of the counter transferring the contents of the two registers to the The memory (20) controls such that a channel request can be processed per memory cycle and a new one can be stored at the same time in one of the channel request locking circuits (124). 2. Control circuit according to claim 1, characterized by a toggle circuit (128) which indicates the occupancy state of the common channel bus lines (32, 34, 36) for all channels (12, 14) , this toggle circuit (128) being controlled by a priority logic (134) set when a channel request is accepted and after the request has been executed, i.e. after a storage cycle, is reset by the counter (150). 3. Control circuit according to claim 1, characterized by logic circuits (122) which are controlled by the flip-flops (142) for storing the output signals of the priority logic (134) and do not pass further request signals from the channels to the priority logic (134). 4. Control circuit according to claim 1, characterized by an overflow detector logic (F i g. 2A) which is controlled by the execution counter (150) and prevents requests from the central processing unit (CPE) to the main memory during a certain number of memory cycles to lower channels Priority to allow access to the main memory. 5. Control circuit according to claim 1, characterized by a timer circuit (154) for controlling the bus lines.