DE2128470A1 - Semiconductor integrated circuit and process for its manufacture - Google Patents

Description

for their manufacture. (Priority: June 15, 1970, Japan, No. 51001)

The invention relates to semiconductor devices, and more particularly relates to semiconductor integrated circuits of the MOS type. In an integrated MOS semiconductor circuit with a plurality of MOSPET elements formed in a semiconductor substrate, parasitic channels were created on the substrate surface directly under an insulating film on which connection layers are provided. The insulating film has usually been made thick in order to prevent such parasitic channels from being generated. As a result of the differences in level of the surface, however, interruption problems arose. Further, in such a device, since the insulated gate parts are not formed by self-aligning methods, the feedback capacitance is caused to be large, so that such a device cannot be used for high frequency signals.

109884/1639

ORlGlHAt

The object of the invention is to eliminate the above errors. To do this, a new method of manufacture is used an integrated MOS semiconductor circuit created, in which the formation of parasitic channels between the individual elements can be prevented without larger ones To cause level differences on their surfaces. In addition, MÖS semiconductor devices are created, in which the feedback capacitance can be reduced by removing the gate parts by self-aligning processes generated v / earth.

In the method according to the invention, an insulation material, that does not oxidize easily, such as silicon nitride, on several parts of a silicon semiconductor substrate, By forming the MOS semiconductor circuit elements v / should be put down; the substrate is heated in an oxidizing atmosphere to form an oxidized surface layer, namely to form a silicon oxide layer on the substrate in those places where the Insulation material has not been applied; then partially in the substrate diffusion zones with a Formed conduction type, which is opposite to that of the substrate wherein the insulating material and the silicon oxide layer are selectively used as masks; and finally, gate insulating films are placed on the semiconductor substrate formed, from which the remaining insulation material is removed.

In detail, the silicon semiconductor substrate is after Application of the silicon nitride film heated to a temperature of 1200 ° C for about five hours to a thick silicon oxide layer using the silicon nitride films as masks to form. Holes are made in the silicon nitride layers for diffusion of the source ... and drain zones are provided. Then the remaining. Silicon nitride layers etched away, and exposed on the th surface parts of the silicon substrate are through oxidation gate dielectric films of a certain thickness

. 109884/1639

ORIGIMAL BATHROOM

educated. Finally, aluminum electrodes are attached. '»

Further details of the invention emerge from the following description of a preferred embodiment " for example with reference to the drawing, in which FIGS. 1 (a) to 1 (e) are sectional views through a semiconductor device are in different stages of manufacture.

As shown in Fig. 1 (a), a monocrystalline N-silicon substrate 1 produced, and applied to certain parts of the substrate v / ground films 2 made of a material, that is sufficiently low compared to silicon. Oxidation rate having. In the exemplary embodiment, silicon nitride is used for the films 2. the Silicon nitride films 2 can be selectively formed by using a metal mask or by first Silicon nitride deposited on the entire substrate surface and then the unwanted parts selectively be etched away. In the substrate under the silicon oxide films 2 the active zones are to be formed by MOS elements. A major rear surface of the substrate 1 can be completely covered with a silicon nitride film (not shown in the figure).

According to FIG. 1 (b), the silicon substrate 1 is heated in an oxidizing atmosphere for about five hours to a temperature of about 1200 ° C. in order to oxidize the substrate surface _{which is not covered with the silicon nitride films 2, an SiO 2 film selectively in the substrate} 3 is formed with a thickness of about 2 to 3 μ. In this step, the silicon oxide film 3 is formed so as to surround semiconductor regions which are under the silicon nitride films 2 and in which active regions are to be formed. The silicon oxide film 3 must have a sufficient thickness. '-

1 Q 9 8 8 4/1639 BAD ORIGINAL

If no silicon nitride film is provided on the rear surface of the silicon substrate 1, * there is a " Silicon oxide film (not shown in this figure) is formed.

Thereafter, the silicon nitride films 2 exceptionally ground the gate ° parts are selectively removed by a photo-etching process = A P-type interfering substance, for example Bov, enters the exposed substrate surfaces through the exposed substrate surfaces 'Silicon substrate 1 diffused, whereby, as in Fig. 1 (c' shown / source regions 4 and drain regions 5 formed F four den '. During the diffusion step, the exposed substrate surface new silicon oxide films 6 formed «

Then, as shown in FIG. 1 (d), the remaining Silicon nitride films 2 are etched with phosphoric acid and removed, and on the gate parts are through an oxidation treatment Silicon oxide films 7, which act as gate dielectric layers, with a certain thickness educated. In order to lower the threshold voltage, it is necessary that the gate dielectric film 7 is made thin "

Finally, in the oxide films 6 on the source and drain zones are engraved by photo-etching treatment and ground by vapor deposition of aluminum or the like Source electrodes S and drain electrodes D that see ohms Have contact with the source and drain regions, and gate electrodes G are generated.

In the case of the integrated circuit device produced by the method according to the invention described above with several MOS elements, the emergence of parasitic Prevent channels almost completely. Furthermore, the gate dielectric parts are made by a method formed in which self-alignment takes place so that

109884/1639

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the feedback capacitance to half Ms to a third of the value in conventional devices can be reduced and the packing density of the integrated circuit can be increased v / ground.

The above description relates specifically to MOS transistors as MOS circuit elements; she is however, it can also be used in the same way in an integrated circuit device which uses other MOS circuit elements, such as MOS diodes or passive elements.

109884/1639

Claims (6)

Claims 1 / Semiconductor integrated circuit device comprising a semiconductor body, a pair of in the. Semiconductor zones formed by the semiconductor body, which have a conductivity type opposite to the conductivity type of the adjacent material of the semiconductor body and form a pair of PN junctions, characterized by a thick semiconductor oxide layer (3) which jumps into the semiconductor body (1) and over it Surface protrudes, a pair of insulation films (6), each of which lies on the semiconductor zones and adjoins the thick semiconductor oxide layer, a dielectric gate film (7) formed on the surface of the semiconductor body between the semiconductor zones, which is attached to the thick oxide layer and the Insulation films adjoins W · a gate electrode (G) provided on the dielectric gate film and at least one connecting layer (S, D) which runs from one of the semiconductor zones to the thick oxide layer. 2. Circuit device according to claim 1, characterized in that each of the PN junctions ends at the thick oxide layer (.3) and the surface of the semiconductor body (1). 109884/1639 2128 ^ 70 3. Circuit device according to claim 1 or 2, characterized in that the thick semiconductor oxide layer (3) is deeper than the semiconductor zones. 4. Circuit device according to claim 1, 2 or 3, characterized characterized in that the gate dielectric film (7) is thinner than the insulating, films (6) on the semiconductor zones. 5. Circuit device according to one of the claims 1 to 4, characterized in that the semiconductor body (1) made of silicon and the thick semiconductor oxide layer (3), the insulating films (6) as well the gate dielectric film (7) made of silicon oxide exist. 6. A method for producing a semiconductor device according to the preceding claims, characterized in that g e that on part of a surface of a "silicon semiconductor substrate . Silicon nitride film is formed that the semiconductor substrate using the silicon nitride film as Mask is selectively oxidized to form a thick silicon oxide layer, and the silicon nitride film is selectively removed to expose a pair of surface areas of the silicon substrate that through the exposed surface areas in the line 109884/1639 type-determining impurities is diffused into the semiconductor substrate to form a pair of semiconductor zones with a conductivity type which is opposite to that of the substrate * whereupon a pair of insulating films is provided on the exposed surfaces
becomes that further the remaining silicon nitride film removed and through a gate dielectric film «
is replaced, on which a gate electrode is applied, and that "finally a pair of holes is formed in the insulating films to expose the respective surface area of the semiconductor zones, whereupon at least one interconnection layer is applied so that one of the semiconductor zones through the relevant Hole through connects with the thick silicon oxide layer. 7 · The method according to claim 6, characterized in that the dielectric gate film and the
Isolatiorisfilme from silicon oxide formed v / ground. 109884/1639