DE2122878C3 - Four-phase delay unit - Google Patents

Description

Kx = -

C,

will assume, see FIG. 2d. In the time interval (U - fs) the voltage at the output Φ _{4 of} the switching voltage source is the same - and this is also the voltage at the gate of the transistor M ₅ . The voltage across the capacitance G ₂ is also - £ The transistor M ₅ will be non-conductive in the last-mentioned time interval, and the voltage across the storage capacitance continues to correspond to -E, see FIG. 2g. The latter only applies if it is ensured that the voltage across the storage capacitance Ci according to relation (1) remains lower than the threshold voltage of the transistor M ₆ . This means that Ci > Cd and the voltage £ must not be too high

may be chosen. In those cases, however, where the capacitance value of the storage capacity Q with remote from the stray capacitance Q is comparable occurs the danger that the transistor M ₆ in the time interval (fr - fc) is conductive. As a result, the capacitance C ₂ will be discharged to 0 volts and that means that the information stored in the capacitance Q (0 volts = binary digit 0) no longer corresponds to the information offered at the input of the delay unit (- £ S = binary digit 1), see Fig.2g dashed line. The capacity value of the storage capacity Q must therefore be sufficiently large compared to the stray capacity Cd for reliable operation, although the latter is largely determined by the structure.On the other hand, the capacity value of the storage capacity determines the speed of the delay unit

The object of the invention is to provide the in the preamble of Design claim 1 specified delay unit so that it can be used for higher switching frequencies is suitable by lowering the minimum allowable value of the storage capacity. This task solves the invention by the features specified in claim 1.

An embodiment of the invention is shown in the further drawings

F i g. 3 shows a delay unit according to the invention

F i g. 4 shows a diagram to explain the mode of operation of the delay unit according to FIG. 3.

The delay unit according to Figure 3 contains two stages I and II. The first transistor from the first stage is formed by the field effect transistor M \ and the second transistor by the field effect transistor M ₂ the output Φ _{2 of} a switching voltage source S is connected The drain of the transistor Mi is connected via the main _{current path of the field effect transistor M 3} to the clock pulse conductor 1, which is connected to the output Φι of the switching voltage source 5. The source of the transistor Mt is connected to the drain of the transistor M. ₂ , whose source is connected to the clock pulse conductor 1 _{via the main current path of the transistor M9 The drain of the transistor M 2} is connected via the main _{current path of the transistor M 4} to the clock pulse conductor 3, which is connected to the output Φ3 of the switching voltage source S. The drain of the The transistor M] is connected to the storage capacitance Q. The binary input signal V, is fed to the gate of the transistor Mi. The first transistor from the second stage is formed by the field effect transistor M5 and the second transistor is formed by the field effect transistor M ₆ . The gate of the transistor Af ₅ is connected to the clock pulse conductor 4, which is connected to the output Φ _{4 of} the switching voltage source 5. The drain of the transistor Ms is connected to the clock pulse conductor 3 via the main current path of the field effect transistor M _7. The source of the transistor M5 is connected to the drain of the transistor Me, the source of which is connected to the clock pulse conductor 3 via the main current path of the transistor Mio. The drain of the transistor M ₆ is connected to the clock pulse conductor 1 via the main current path of the transistor Me. The drain of the transistor M ₅ is connected to the storage _{capacitance C 2} , and the gate of the transistor Me is connected to the storage capacitance C \ . The operation of this delay unit is as follows

It is again assumed that the binary digit 1 (= - £) is offered to the gate of transistor M _{2, see FIG. 4c.} In the time interval (i _t - f ₂ ) the voltage at the outputs Φι and Φ _{2 of} the switching voltage source S is equal to —E, see FIGS. 4a and 4b. In this time interval, the transistor M _{3 is} conductive and the storage capacitance G is charged until the voltage across the capacitance is equal to —E , see FIG. 4d. In the same time interval, the transistor Ma from the second stage is also conductive. As a result, the stray capacitance Cn between the drain and the substrate of the transistor Me is charged until the voltage

Since the charging of the storage capacitance Ci and the capacitance Ca takes place in the same time interval, the voltage across the stray capacitance Ca between the drain and the gate of the transistor Af _{6 will be} equal to 0 volts. In the time interval (i ₂ - * 3) the transistors Mi and M? conductive, as a result of which the storage capacitance Ci is discharged again until the voltage across this capacitance is equal to 0 volts see FIG. 4d. Since the voltage at the drain of the transistor M _b in the relevant interval is equal to - E, see FIG. 4b, the voltage across the capacitance C _{d will be} equal to -E at the end of the said interval. There is therefore no charge distribution between the storage capacitance Ci and the stray capacitance Cd in the interval mentioned. The voltage across the storage capacitance C ₁ is therefore independent of the ratio between the capacitance values of the capacitances C and Cd. This has the consequence that, if one wants to realize a very fast delay!> Ciiiheit, the storage capacity Ci can be made as small as desired, for example 0.01 pF. The further transmission of the information stored in the storage capacity C1 to the storage capacity C ₂ is the corresponding transmission of the _{information stored in the storage capacity C 2} from the known delay unit according to FIG. 1 analog. For the sake of completeness, this is shown in more detail in FIGS. 4e to 4g. The source of the transistor Me is connected to the clock pulse conductor 3 via the main current path of the transistor Mw. This ensures that transistor M ₆ can never become conductive in phases Φι and Φ _{2 of the clock pulse signal.} The source of the transistor M ₂ is connected to the clock pulse conductor 1 via the main current path of the transistor M9 _{, so that the transistor M 2} never becomes conductive in phases Φ3 and Φ _{4 of the clock pulse signal.}

In the exemplary embodiment of the delay unit according to the invention shown in FIG. 3, the drain of the transistor M _{2 is} connected to the clock pulse conductor 3 via the main _{current path of the transistor M 4.} However, it is also possible to connect the drain of the transistor M ₂ to the clock pulse conductor 4 via the transistor M _4. In a similar way, the source of the transistor M _{2 can be} connected via the main current path of the transistor M ₉ to the clock pulse conductor 2 instead of to the clock pulse conductor t. The drain of the transistor M ₆ can also be connected to the clock pulse conductor 2 instead of the clock pulse conductor 1 via the main current path of the transistor Ms. In the same way, the source of the transistor Mö can be connected to the clock pulse conductor 4 instead of the clock pulse conductor 3 _{via the main current path of the transistor Mi 0.}

For this purpose 3 sheets of drawings

Claims (2)

Patent claims: 1. Four-phase delay unit from a series circuit of at least a first and a second stage, each containing at least a first and a second field effect transistor, the source of the first transistor with the drain of the second transistor and with different clock pulse lines for both stages and the drain of the first transistor from the first »stage is connected to the gate of the second transistor from the second stage and to a storage capacitance and the gate of the second transistor from the first stage receives a binary signal, the drain of the first The transistor and the source of the second transistor of the first stage are connected to a first clock pulse conductor and the gate of the first transistor to a second clock pulse conductor and the drain of the first transistor and the source of the second transistor of the second stage to a third clock pulse conductor and the gate of the first Transistor with a fourth clock pulse conductor is connected, characterized in that the source of the first transistor (Mi, Ms) in the first stage (I) with the third (3) or fourth clock pulse conductor (4) and in the second stage (II) with the first ( 1) or second clock pulse conductor (2) is connected, and that a third transistor (M% Mw) is arranged between the source of the second transistor (Mt, Me) of both stages (I, II) and the associated clock pulse conductor, which is blocked when the first (1) and second clock pulse conductor (2) in the first stage and the third (3) and fourth clock pulse conductor (4) in the second stage each have a clock pulse at the same time. 2. Four-phase delay unit according to claim 1, characterized in that the source of the first transistor (M ,, Ms) of both stages via a fourth transistor (M «, Me) are connected to the associated clock pulse conductor (3,1) . 45 The invention relates to a four-phase delay unit according to the preamble of claim 1. Such a delay unit, which is particularly suitable for dynamic four-phase logic systems, such as shift registers, is known from DT-OS Ol 886 and is shown in FIG. ! shown. This known delay unit contains two stages I and II. The first transistor from the first stage is formed by the field effect transistor Mi and the second transistor by the field effect transistor Mt. The gate of the transistor M \ is connected to the clock pulse conductor 2 , which is connected to the output Φ ₂ a switching voltage source S is connected. The drain of the transistor M is connected via the main current path of the field effect transistor M ₃ to the clock pulse conductor 1, which is connected to the output Φι of the switching voltage source 5. The source of the transistor Mi is connected to the drain of the transistor Mi , the source of which is connected to the clock pulse conductor 1. The drain of the transistor M ₂ is connected to the clock pulse conductor 1 via the main current path of the transistor M _4. The drain of the transistor Mi is with the Storage capacity Ck connected. The binary input signal Vi is supplied to the gate of the transistor MT is supplied to the first transistor of the second stage through the field effect transistor M5 and the second transistor is formed by the field effect transistor M ₆ The gate of transistor Af ₅ is connected to the clock pulse conductor 4, connected to the output Φ * of the switching voltage source S is connected The drain of the transistor Ms is connected via the main current path of a field effect transistor Mi to the clock pulse conductor 3, which is connected to the output Φ _{3 of} the switching voltage source 5. The source of the transistor Af ₅ is connected to the drain of the transistor Me , the source of which is connected to the clock pulse conductor 3. The drain of the transistor M ₆ is connected to aem clock pulse conductor 3 via the main _{current path of the transistor M 8.} The drain of the transistor M ₅ is connected to the storage capacity Ci and the gate of the transistor M ₆ is connected to the storage capacity Q. The mode of operation of the known delay unit is illustrated using the diagram in FIG. 2 explained It is assumed that the binary input signal which is fed to the gate of the transistor Mt is the binary digit 1 (-E), see Fig.2a In the time interval (ti - f ₂ ) the voltage at the output Φι of the switching voltage source S is equal to - £ see Fig. 2a. The transistor M ₃ will be conductive during this interval and the memory G is charged until the voltage across it is -E in said time interval, transistor M ₄ at the same time is conductive, whereby the capacitance C _s) between the drain of the transistor MT and the Substrate (earth) is charged until the voltage across it is equal to -E In the time interval (ti -t ₃ ) the voltage at the gate of the transistors Mi and M _{2 is} equal to -E, see FIG. 2b and 2c. As a result, these transistors are conductive, and in this time interval the storage capacity Q is discharged until the voltage across it is equal to 0 volts see Fig. 2d In the time interval (h - Üj the voltage at the output Φ3 of the switching voltage source 5 is the same - £ see Fig. 2e. the transistors M ₇ and M ₈ are thereby be conductive. the storage capacitor C ₂ is charged via the transistor Mr until the voltage across it is equal to -E, see Fig.2g, una the capacitance C _a between the drain of transistor M ₆ and the substrate (earth) is _{charged via the transistor M 8} until the voltage across it is equal to -E . The latter also means that the voltage across the series circuit of the storage capacitance Q and the capacitance d between the gate and the drain of the transistor M. ₆ equals - E. This has the consequence that the voltage across the storage capacitance Ci has the value