DE2110277A1 - Receiver alarm system - Google Patents

Description

PP .

JW / Sp. Or. Herbert Scholi

Patent attorney

Applicant: PYE LIMITED '2110277

Files Na. PP- 1042
Registration from: 3 · 3 · 1 971

"Receiver Alarm System".

The invention relates to means that

in the event of a fault in a receiver on systems in which two receivers are connected in parallel, give an alarm signal.

In wireless communication systems where high reliability is required, it is common to to protect against interference in the receiver or against failure by using two receivers with their audio outputs are connected in parallel, so that in the event of a fault in one receiver, the other still has an output signal gives.

It is desirable that means are provided which give a warning signal of the malfunction in one of the two receivers.

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give catcher.

When the RF signal contains a steady carrier, the placement of an alarm circuit is proportionate simple. In each recipient is from a suitable body, such as e. from the demodulator, one of the available a carrier dependent signal and compared to a reference or threshold level. If the Receiver works properly, the signal level will exceed the threshold, while if the receiver fails or if its gain has largely decreased, the signal falls significantly below the threshold level will.

The comparator gives an output signal with the one or the other of two discrete levels, with a first level if the signal is above the threshold and a second level if the signal is below the threshold.

It should be clear that the noise barrier normally provided in telecommunication receivers is added to this is usable. For the sake of simplicity, the comparators will hereinafter be referred to as noise barriers, es however, it should be understood that the comparators and their associated circuitry are particularly useful for generating a Alarm signal can be provided, and do not necessarily have to have a noise blocking function.

With a steady carrier, the squelch output signals from the two receivers will normally be are at the first level. If one of the two recipients

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If the catcher fails, its squelch output will shift to the other level. It can be a
Alarm circuit can be provided which is energized when either or both of the squelch output signals are at the second level.

With an intermittent carrier effect, the
Carrier at the end of each transmission period. Consequently
switch the two noise specre output signals to
second level. With the simple arrangement described above, an alarm would be given at the end of each transmission.

It is conceivable that the two squelch output signals reach the first level at the same time and tip back to the second level at the beginning and at the end of each transmission. It could then be an alarm system
where the two squelch output signals are compared and an alarm signal is given if at any time either
Output signal is in a different state than the other output signal. ■

It turns out that such a

Arrangement very often gives a false alarm. The threshold setting and the response times of the two noise barriers will seldom be the same. In a similar way will the gain of the receivers will not be identical. Consequently, fluctuations in the received signal strength, especially in mobile equipment, lead to the

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Carrier in a receiver falls below the threshold level, but not in the other recipient. The arrangement is also extremely sensitive to disturbances caused, for example, by thunderstorms.

In order to keep the number of false alarms to a minimum, it is proposed according to the invention that the Noise barrier output signals from the two receivers during to compare each transmission period and to give an alarm if and only if the squelch output signal of one or the other receiver remains in the second state during the entire transmission period is located. Means are also provided to reduce the effect of disturbances.

The present invention relates in particular to telecommunications systems in which a plurality mobile radio stations, for example in motor vehicles, can be in communication with a central fixed station, the fixed station having parallel receivers is provided. In such networks it often happens that several in succession in the fixed station received transmissions originate from one and the same mobile station. When this mobile station is at the At the limit of the range of the system or in an area where the propagation conditions are unfavorable, it may be that the fixed station receives such a weak signal that this signal is due to the inevitable differences in sensitivities

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and / or noise barrier threshold levels the noise barrier of one or both receivers of the fixed station does not work during successive transmissions, although the two receivers are operational are. To reduce the occurrence of alarm signals caused by this, counting means can be provided, no alarm signal is given until one or the other of the noise barriers during a certain Number of consecutive transmissions has failed to work. If before that number is reached, the two noise barriers have become effective at- ^

for example by a signal from a mobile station with a more favorable location, the counting means reset to zero.

On the other hand, each receiver can be provided with a second noise barrier which is set to a higher threshold level than the first noise barrier; an alarm signal is given if and only if the output signal of the second noise barrier of one or the other receiver ύ

is ineffective during the entire transmission period.

The receiving system according to the invention is thereby characterized in that there are two receivers for receiving an HP signal, each receiver having a noise barrier contains to give an output signal when the carrier level at the demodulator of the receiver a threshold value exceeds, with further an alarm device

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is present with a first memory arrangement which only occurs through the simultaneous occurrence of noise barrier output signals both receivers is adjustable, and with a second memory arrangement, which is generated by an output signal the first storage arrangement can be set in the set state, with a reset arrangement the presence of a noise barrier — exit— signals from one or the other receiver during a transmission period responds, and at the end this transmission period can generate a reset pulse, said reset pulse via a first delay arrangement with a delay time which corresponds at least to the length of the reset pulse, is supplied to the first storage arrangement, and which is supplied directly to the second storage arrangement is, wherein the reset pulse does not reset the second memory arrangement at the end of a transmission period can if the first memory arrangement is set during this transmission period. An output signal the second storage arrangement is used to activate alarm arrangements when the second storage arrangement is in the reset state.

Embodiments of the invention are shown in the drawing and are described in more detail below. Show it:

Fig. 1 is a block diagram of the inventive Receiving system,

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Fig. 2 shows a modification of the receiving system according to Fig. 1,

FIG. 3 shows a further modification of the receiving system according to FIG. 1.

In Fig. 1, the squelch output signals * 1 and 2 of the receivers RxA and RxB are fed to the inputs of an OR gate 3 and the inputs of an AND gate k . The output of the gate k is connected to the control input of a memory unit 5. An output of the memory unit 5 is connected to the control input of a memory unit 6.

The output of gate 3 is through a noise suppression unit 7 connected to an input of a reset unit 8. The output of the reset unit 8 is connected to a reset input of a memory arrangement 6 and via a delay unit 9 to the Reset input of the memory unit 5 connected.

The mode of operation * of the system becomes apparent ■ considering the first situation, with the two receivers A and B operational. ■

When a signal is received, the

Noise barrier output signals 1 and 2 are supplied to the inputs of gate 3 and gate h. The gate k will then give an output signal which will bring the memory unit 5 into the "A and B ON-U" state. The output signal from the memory unit 5 will then bring the memory unit 6 into the "error-free" state.

The output signal of gate 3 is the return

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Put setting unit 8 in the "A or B ON" state. At the end of the transmission, the output of gates 3 and h will drop. The memory unit 5 will remain set until it receives a reset pulse at its reset input. The reset unit 8 can, however, fall back into the "A and B off" state and generate a short pulse at its output when its input signal is removed.

This output pulse is immediately the The reset input of the memory arrangement 6 is supplied, but has no influence on it because the memory arrangement 6 by the output signal of the memory arrangement 5 »which is still in the" A and B ΕΙΝ "- r state, remains set.

The output pulse of the reset unit 8 is also sent to the reset input via the delay unit 9 the memory arrangement 5 is supplied. The delay caused by the unit 9 is such that the The reset signal of the memory arrangement 5 is not supplied until the similar one is supplied to the memory arrangement 6 Signal has dropped out. The memory array 5 is in the "A or B OFF" state for the next transmission brought and the hold input signal is from the memory array 6 removed. The latter, however, remains in the "error-free" state, since the reset pulse that the Memory arrangement 6 has received from the unit 8 has already ended.

It is now assumed that during a

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Transmission of the noise lockout signal to a receiver, ζ »Β RxA disappears. This can either be caused by a failure of RxA or by a small signal that temporarily falls below the RxA squelch threshold. Since the two squelch output signals are present together at a moment during the transmission, the gate 4 gives an output signal, the memory arrangement 5 is set to the "A and B on" state and the memory arrangement 6 receives a string input signal * the gate 3 gives an output signal during the entire transmission.

At the end of the transfer, the reset unit 8 a partial jerk pulse which, as mentioned above, is unable to because of the hold signal from the Storage arrangement 5 to reset the storage arrangement 6. The delayed reset pulse then sets the memory array; 5 returns to the "A or B-OFF" state. In no error display is given in this state.

If the disappearance of the sound lock off

gang ^ ssignäls from RxA im; essential to the failure of RxA would be the output signal during not be available for the next transmission period, The AND gate 4 is therefore during this transfer output signal. The memory array 5 is int "A or B Off" ~ status remains and no hold input signal for the storage device 6 generate. The gate 3 will provide an "A or B On" signal after it an input signal from the receiver's noise barrier

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RxB has received, and the reset unit 8 is switched to the "A or B on" state. At the end of the transfer, unit 8 will be in ύ & Ώ. Return "A and B off" status and deliver a reset pulse which will now reset the memory arrangement 6 to the "error" status. An output signal from the memory arrangement 6 is used to light up an error display lamp TO and to excite an external alarm circuit via the line L.

During successive transmissions the memory arrangement 5 is in the "A or B off" state remain operational until the failing recipient is so that the gate * f again input signals from the noise barrier of both receivers.

It should be obvious that there was no alarm becomes, if the noise barriers of both receivers at any time during the transmission period an output signal 1 generate, but at the end of the transmission period an alarm is given if one of the two receivers is during No noise barrier for the entire transmission period — Off— output signal supplies.

XJm the sensitivity of the circuit arrangement to reduce temporary interference is a noise suppression unit 7 between the output of the Gate 3 and the input of the reset unit 8 is provided. The noise canceling unit 7 is such Delay unit that a step function is fed to its input and a step function is fed to its output generated, namely after a delay time t,

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No output signal is delivered, however, if the input returns to its original value before the end of the delay time t. Therefore, a squelch output signal from one of the two receivers RxA or RxB must be present for longer than t before the unit 8 is set. For the sake of convenience, the value t is of the order of magnitude of 25 ms', which is sufficient to make the circuit insensitive to temporary disturbances caused by thunderstorms. The noise suppression unit 7 can, for example, be a resettable mono- M

stable toggle circuit included.

Additional memory arrangements 11 and 12 can be used to display the states of the different receivers are provided. The setting input of the memory arrangement 11 is the noise blocking signal 1 of the receiver RxA is supplied and the reset input is connected to the output of a NAND gate 13. In a similar way will the setting input of the memory arrangement 12 is supplied with the noise barrier output signal 2 of the receiver RxB, and the reset input is connected to the output of a NAND gate ^ 14 connected. When the two receivers RxA and RxB are in operation are set at the beginning of a transmission period the output signals of the noise barriers 1 and 2 the memory assemblies 11 and 12 in the "A on" and "B on" states, respectively. The "A-on" lamp 15 is activated by the output signal the memory array 11 and the "B-On" lamp 16 becomes ignited by the output signal of the memory arrangement Ί2.

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The input signals for the gate 13 are the noise blocking signal 1 from RxA, the noise blocking signal 2 'λ from RxB, which is fed via an inverter I, and a signal from the memory arrangement 5 »which blocks the gate 13 when the memory arrangement 5 is in the" A and B are in a "state. Similarly, the inputs to the gate 14 are the noise blocking signal 2, the inverse of the noise blocking signal 1, and the signal from the memory array 5 *

Assuming RxA fails during a transmission. The squelch signal 1 is removed, but the memory array 11 is not reset because the Gate 13 is blocked by the signal from the memory arrangement 5. At the end of the transfer, the memory array 5 is reset by the delayed reset pulse from unit 8 and that pulse removes the Lock signal from gate 13 · But during this time the absence of the noise lock signal 2 creates a lock for the NAND gate 13. The memory arrangement 11 thus remains in the "A on" state.

At the beginning of the next transmission period, if RxA fails, no squelch signal 1 is received. The return of the squelch signal 2 removed the blocking of the gate 13 and since the memory arrangement 5 has not been set in the "A and B on" state is, no lock signal is received at gate 13. All three inputs for gate 13 are therefore located in the same state and the gate gives an output signal

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which brings the memory arrangement T1 into the "A off" state and the lamp 15 goes out.

It should be clear that the mode of operation of the storage arrangement 12 and the lamp 13 that of the storage arrangement 11 or the lamp 15 corresponds.

When the two receivers are active, the lamps 15 and 16 are lit. The corresponding lamp remains ignited if a squelch output signal is received at any time during a transmission period of the given to one or the other recipient. If one of the two recipients during a transmission period if it fails and remains faulty, the corresponding lamp is extinguished at the beginning of the next transmission period.

If the audio signals from the two receivers were simply connected in parallel, changes would occur occur in the level of the final audio output signal, depending on whether one or the two receivers contribute to this output signal . ■

To maintain a constant level of the output signal, the audio signals from RxA and RxB are separated Inputs of an audio switching unit 17 are supplied. The unit 17 contains a mixer circuit, an attenuator in the path of the combined signal and an electronic switch connected in such a way that im a state of this switch the attenuator briefly-

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closes. The electronic switch * is activated by the Output signal of the gate 4 operated in such a way that he causes attenuation when the two receivers are effective and removes the attenuation when only one receiver is active contributes to the output signal.

A modification of the above-mentioned arrangement will now be described in more detail with reference to FIG. This figure Figure 3 is a block diagram of an alternative means of resetting the memory array 6 to prevent the occurrence of alarm signals when the received signal strength is low is minimized. Units, which correspond to the units described above are indicated with the same reference symbols as in Fig. -1.

In Fig. 2 has a multi-level digital counter unit 18 an input which is connected to the output of the reset unit 8. A reset input of the unit 18 is connected to the output of the memory arrangement 5. The output of the unit 18 is with the reset input the memory unit 6 connected. Arrangements for setting and resetting the memory arrangement 5 and for setting of the memory arrangement 6 are as described in FIG. 1.

It is assumed that during a transfer the memory array 5 in the "A and B on" state and the memory arrangement 6 in the "error-free" state is set. At the end of the transmission, the unit 8 will deliver a reset pulse, but this will

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not counted by the unit 18 by the output signal of the memory array 5 in the zero state is held until the delayed reset of the last-mentioned unit, at which point in time the reset pulse will be finished.

It is now assumed that one or the other receiver does not give a squelch output signal in the next transmission period. The memory arrangement 5 is not set and therefore there will be no hold signal on the counter 18. At the end of the transmission period, the reset unit 8 will deliver a pulse which is counted in the unit 18. In each subsequent transmission period, if one or the other receiver fails again to deliver a squelch output signal, the count stored in the unit 18 is increased by one digit until the counter is full and after η transmissions delivers an output pulse, where η is the Capacity of the counter is. The output pulse of the counter 18 will reset the memory arrangement 6 to the "error" state and an alarm will be given. When M

however, the two receivers give a squelch output signal in one transmission period before the counter 18 is filled, the memory arrangement 5 is in the "A and B A "state is set and this will reset the counter 18 to zero»

In a telecommunications system as described above, the capacity of the counter 18 corresponding to the number of consecutive transmissions

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which are normally done in front of only one remote station. The counter 18 is preferably a multistage binary counter in which means can be provided, for example by means of adjustable elements, for supplying an output pulse after 2, h, 8 etc. input pulses, so that η is the number of successive transmissions for which one or the other receiver fails must provide a squelch output signal before an alarm signal is given, which can be chosen to suit the type of traffic to be handled by the network.

Another modification of the arrangement according to FIG. 1 is explained in more detail with reference to FIG. as well As above, corresponding above-mentioned units are indicated by the same reference symbols as in FIG. 1.

In Fig. 3, a receiver RxA is provided with a noise barrier which gives an output signal 1 when the level of the RF carrier at the demodulator reaches a first threshold level, and with a second noise barrier, which gives a second output signal 19 if the carrier reaches a second threshold level higher than the first level. Returns in a similar way the receiver RxB has a first noise barrier output signal 2 and a second noise barrier output signal 20, which corresponds to the higher threshold level.

As in Fig. 1, the outputs 1 and 2 of the noise barrier are connected to the inputs of an AND gate h

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bound. The output of the gate k sets the memory arrangement 5. The gate 3, however, which excites the reset unit 8 via the delay unit 7, has its inputs connected to the noise barrier outputs 19 and 20.

Consequently, the unit 8 will not generate a reset pulse until at least one of the receivers is on Output signal delivered to its second noise barrier Has. When the memory arrangement 6 has been set in the "error-free" state, it becomes the "error" state reset after a transmission period, i (|

when a receiver does not have any squelch output signals and the other receiver provides an output signal to both the first and second noise barriers has delivered, but not if only the first noise barrier has an output signal from this other receiver By a suitable choice of the first and second threshold level it is possible that a weak Signal that reaches the second squelch threshold of the more sensitive of the two receivers, also at least ^ the first noise level of the less sensitive Of the recipient. This procedure ensures that an error display is only given if a strong signal has been received by one or the other of the receivers, thereby avoiding that if the reception is weak, an Al: ·; msignal occurs, wherein the absence of the first squelch output signal can be attributed to a change in the transfer conditions.

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Claims (6)

pp.? -18- PATENT CLAIMS: 1 .J Reception sys tem, characterized in that two receivers are provided for receiving an RF signal, each receiver containing a noise barrier that has a Output signal is when the carrier level at the demodulator of the receiver exceeds a threshold value Alarm circuit with a first memory arrangement that can only be set if the sound lockout output is activated at the same time signals from both receivers are present, with a second memory arrangement, which is based on an output signal of the first memory arrangement can be brought into the set state, a reset circuit that reacts to the presence a squelch output signal of one or the other receiver during a transmission period responds and which delivers a reset pulse at the end of this transmission period, said Reset pulse of the first memory arrangement via a first delay arrangement with a delay time, which corresponds at least to the duration of the reset pulse, and which is supplied directly to the second memory arrangement is supplied, wherein the reset pulse the second memory arrangement at the end of a transmission period cannot reset if the first memory arrangement was set during this transmission period. 2. Receiving system according to claim 1, characterized in that the second memory arrangement displays an error there when it is reset. 3 · Receiving system according to claim 1 or 2, characterized characterized in that a second delay arrangement the 209841/0190 PP.10 ^ 2 -19- 2 Ί1 0277 Has a delay time that is greater than the possible duration of temporary disturbances between the noise blocking exits the two receivers and the reset circuit is provided so that it is avoided that the latter responds to interference signals with a shorter duration than the delay time. 4. Receiving system according to one of the preceding Claims, characterized in that the second memory arrangement by an output pulse from a counter is reset, which as input signal the pulses ^ of the reset arrangement receives said output pulse is delivered when the count reaches a predetermined number, said counter through an output signal of the first memory arrangement in the set state can be reset to zero. 5 · Receiving system according to claim 1, 2 or 3 » characterized in that each recipient with a A noise barrier is provided which gives a first noise barrier output signal when the carrier level on the demodulator exceeds a first threshold, and the a ^ provides a second squelch output signal when the carrier level exceeds a second threshold level, wherein the first memory array only by the simultaneous presence of the first squelch output signals both receivers is adjustable, and wherein the reset arrangement to a second noise barrier output signal of the addresses one or the other recipient; where the 20984 1/0 1-9 0 PP, -20- second noise blocking threshold level is higher than the first noise blocking threshold level. 6. Receiving system according to one of the preceding Claims including a third memory arrangement which is stored by a squelch output of the one of the two receivers is adjustable and by the lack of this noise barrier output signal at the beginning of a subsequent one Transmission period is resettable, which in the set state gives an indication that one of the two receivers is effective. 7 · Receiving system according to one of the preceding Claims including a third memory arrangement which is determined by a squelch output of the other of the two Receiver is adjustable and due to the lack of this squelch output signal at the beginning of a subsequent one Transmission period is resettable, which in the set state gives an indication that the other of the two recipients is effective. 09841/0190 Blank page