DE1264592B - Circuit arrangement for carrier-frequency transmission of protection signals via high-voltage lines - Google Patents

Description

Circuit arrangement for the carrier-frequency transmission of protection signals The invention relates to a circuit arrangement for carrier-frequency transmission of protection signals via high-voltage lines with Suppression of the transmission of a protection signal via the line system occurring interference pulses, whereby the protection signal on the transmitting side in the high frequency Frequency range transmitted and on the receiving side from the high-frequency to the low-frequency frequency range is implemented and processed.

In the event of protection, the switches must be at the beginning and end of a high-voltage line can be actuated as quickly and simultaneously as possible from one end of the line. to For this purpose, one uses 2.5 kHz wide TFH channels over which an amplitude or frequency-modulated protection signal is sent, which after demodulation on the At the receiving end, the line is switched off, which was previously done by the overcurrent relay was prepared at both ends. The protection signal is on the transmission path influenced by interferers. Of these, it is mainly the impulse noise that has to be taken into account to be pulled. The protection signal receiver should still respond reliably if that Protection signal is superimposed with impulse interferers, the amplitude of which is more than 2.3 Np is greater than that of the protection signal and its repetition frequency is up to 1000 Hz. The protective signaling should ensure that the switch-off criterion is not affected and is passed on as quickly as possible to the end of the line to be protected. aside from that the protective signal receiver must prevent a protective signal from being generated by interference pulses is faked.

In the systems known up to now, a tone is constantly transmitted, which is keyed in the protection case. Both of these are required on the sending side Frequencies in the HF plane generated by two generators. The protective tone is in the receiver implemented twice, limited in the NF position and given on a discriminator, which after rectification and sieving according to the applied tone a polarized Relays in the separating or character position controls. This has a disadvantageous effect System, the overall runtime of the protection signal, which is long in relation to reception reliability the end. It is due to the vigorous sieving. This is essential because the system permanently occupies a TFH channel and suppress any interferers must if there is no protection case.

That is the disadvantage of the FM protection transmission that one of the anyway TFH channels that are already too tight must be constantly occupied (closed-circuit principle), which is the case with an AM transmission is not the case, as the recipient only receives the Responding overcurrent relay in the disturbed high-voltage line to the TFH receiver is switched on (open-circuit principle).

Another disadvantage of all these procedures is that of screening of the protection signal frequency band work from the total bandwidth is that they are mainly can only be used with profit in the NF level. Use in the ZF or HF level is at the expense of the running time with these procedures, because for safeguarding the required narrow band with relatively steep filter edges is an increase the filter value and the associated increase in runtime is necessary. The use the protective signaling in the HF level saves at least one implementation and thus running time.

A circuit arrangement is already known in which the in the generator Generated high frequency modulated by audio frequency transmitter and via the high frequency transmitter is sent out. On the receiving side, the modulated high frequency reaches the High-frequency receiver and then to the demodulator. In this demodulator However, the transmitted signals are not yet processed, but here demodulation, d. That is, the modulated audio frequency must be recovered. These audio frequency signals control the subsequent audio frequency receivers, so that the associated receiver responds according to the tone frequencies and his Output relay actuated. For this, however, it is necessary that the Audio frequency receivers have filters for the selection of audio frequency signals. the Recovery and filtering out of the audio frequency signals are carried out by the receiver thus through filter circuits, creating a propagation delay for the transmitted Signals emerge. Because on the receiving side through the receiver with filter circuits If the frequency is evaluated, this is an analog signal receiving device.

This transmission system is very susceptible to failure, especially in relation to it Interfering signals that are in the vicinity of the high-frequency carrier.

Circuits have already been known which have a greater immunity to interference have ("remote control of circuit breakers with carrier-frequency high-speed switching devices" by Gerhard B ergmann and Bruno Westphal, special print from Siemens trade journal, 33rd year, January 1959; Issue 1, and »Remote tripping of high-voltage switches through carrier frequency signals "by Erwin Schumm, special print from" Electronic Journal " ETZ-B, 11th year, December 1959, issue 12).

A frequency conversion takes place, whereby the distance between the interfering signals of the useful signal in the low frequency band is particularly favorable. Is known here the conversion of the high frequency into an intermediate frequency and only then into an audio frequency. This system has a considerable number of components and a long service life.

The object of the invention is to show a circuit arrangement which avoids the disadvantages outlined above. This happens at the entrance mentioned circuit arrangement according to the invention in that a digital protective signal receiving device the modulated, carrier-frequency protection signal already in. high frequency carrier frequency band processed with the omission of the otherwise customary implementation in lower frequencies.

In the arrangement according to the invention, a new evaluation principle is used used, which requires a very low number of components. In the arrangement no filters are used, so that the protection signal has a short transit time comes. The arrangement works digitally, i. i.e., the carrier frequency is amplitude immediately limited and the zero crossings of the high frequency counted. Occurs in one limited time interval a certain fixed counter reading, so acts it is the protection signal and the counter reading - and not the audio frequency signal - causes the switch to be actuated. The protection signal is evaluated without that a frequency conversion, a frequency limitation or screening of a frequency would have occurred. A demodulation device is also not required for this. the The new arrangement has a greater immunity to interference than the known arrangements. This involves switching units that work very quickly, as they are in digital computers today Find use, used.

By reducing the total transit time of the protection signal, the is mainly due to the omission of the additional filter, that will Protection criterion issued faster than with protection signal receiving devices; which work in lower frequency bands with the same response time. The protection signal is only transmitted in the event of protection (open-circuit principle), where- = for transmission no separate TFH channel is necessary, but a channel is used that is in the normal operation e.g. B. is used as a telephone connection. In the protection case if the channel is busy, the participants are switched off for less than 1 second, and in the protection signal is transmitted during this period. This period does not apply the vast majority on the preparation time of the overcurrent relay. For the transfer of the protection signal according to the circuit arrangement according to the invention becomes the transmission channel at most a few milliseconds long, so that the circuit arrangement itself would also allow use on transmission channels with telecontrol systems conventional design and correspondingly low transmission speed would be. A single oscillator is used as the transmitter, via a modulator is upsampled with a negligibly short runtime. Compared to the known Systems that require two oscillators increase their operational reliability. On the receiving side, the digital protective signal receiver already takes on the HF level or after a one-off implementation in the IF or NF level, a frequency evaluation the discrete interferer and the protection signal, both before the evaluation by a limiter circuit and a subsequent trigger circuit independent of theirs Amplitudes can be shaped into square-wave pulses, the input bandwidth being the Has a maximum value of 2.5 kHz.

The evaluation is carried out by the fact that the output of the trigger circuit resulting square-wave pulses for a given time with an electronic Counters are counted, with only the fast protective signal pulse train exceeding the specified Can reach meter reading. After reaching this: counter reading becomes a protection criterion delivered to the circuit breaker control.

The response reliability of the system increases compared to the known Systems considerably, as the protection signal receiver due to the digital evaluation is insensitive to the interference spectra resulting from the limitation, which with increasing amplitude of the interference pulses in the known systems more and more to make noticable. The maximum response time is when used in the HF-IF level 2 ms.

The runtime of the protection signal is made up of the transient and running time of the TFH transmission system, the transmission link and the response time of the protection signal receiver. When the total runtime of the protection signal is at most Should be 4 ms, this results in the requirement that the response time of the Receiver of the protective signaling may only be up to 2 ms.

Details of the invention are explained with reference to the drawings.

F i g.1 shows the block diagram of the digital protection receiver; F i g. 2 shows the block diagram of the counter with the memory in RCT circuit technology executed; F i g. 3 shows the pulse diagrams in the event of protection. F i g.1 shows a Monitoring circuit used in the IF level, which is activated when a protection signal is transmitted Interference pulses are suppressed via the disturbed line system on the receiving side, which, based on a bandwidth of 2.5 kHz, has an amplitude that is more than 2.3 Np greater than the protection signal and a Have repetition frequency of up to 1000 Hz, the total runtime of the protection signal is a maximum of 4 ms. With this advantageous Embodiment consists of the digital protection receiver essentially from one Limiter B, which is intended to prevent the subsequent stages from being overridden, one Trigger circuit TR, a pulse length shaping stage PLF, which generates the minimum pulse length, a delay element LZG, which the downstream counter only after responding stimulates the timer stages, the electronic counter Z, two timer stages ZG 1 and ZG 2, which release the counter Z for a certain time and the result of the evaluation at the counter output in the subsequent memory SP, one two-stage amplifier V2, which has the necessary power for the protection criterion supplies a deletion stage LÖ to be used if necessary, which deletes the memory SP, if the memory erase is not performed externally by the circuit breaker control , two mixing gates G 1, G 2 and two coincidence gates G 3, G 4 (cf.F i g. 2), with which logical links are made, as well as a two-stage Amplifier V1, which decouples the mixing gate G1 and the coincidence gate G4.

At input E is the composite signal that is derived from the sinusoidal There is a protective tone and discrete glitches. The amplitudes - and here in the stronger The amplitudes of the interference pulses are limited in the limiter B. Because the limiter input is broadband compared to the interference pulse frequency, there is no additional broadening of the limited glitches on, which increases the disturbance energy behind the limiter would bring with it. The subsequent trigger circuit TR, which z. B. as a Schmitt trigger can be constructed, switches with a very steep edge when the at its input lying voltage exceeds a specified, adjustable value. This threshold is set so that noises whose amplitudes are below a certain value with which the protective signal amplitudes are present at input E, the trigger circuit TR cannot steer through. This makes the pulse height primarily of the interferer decisively scaled down, and there will be noises that are below the level with their level Useful amplitude lie, kept away from the subsequent evaluation circuit. Will the threshold is overcome by incoming signals, then the trigger circuit gives TR square pulses.

By the pulse length shaping stage PLF, the z. B. as a monostable multivibrator can be constructed, the smallest permissible pulse length is created, the z. B. is about 95% of the protective pulse distance. This measure prevents that glitches that oscillate in themselves at a frequency that is equal to or greater the protection frequency, the counter can bring to the specified final value. From the rising edges of the pulses that appear at the output of the PLF stage, are the two timer stages ZG1 and ZG2, the z. B. as monostable multivibrators or another timer circuit of conventional design which is capable of the required Adhering to time conditions, can be executed, controlled. The timer level ZG1 gives for a certain period of time, e.g. B. 1 ms, the counter Z free. After expiration During this period of time, the counter reading reached in the meantime is achieved by the timer stage ZG1 is deleted and the counter is reset to zero. The Zeitgeherstufe ZG 2, activated at the same time as stage ZG 1, asks shortly before the meter is cleared, z. B. after 950 #ts, the counter output., And saves the result in the memory SP, the z. B. can be designed as a bistable multivibrator. Before the count starts the delay element LZG ensures that the first received pulse only then. in the counter Z is counted when the timer levels ZG 1 and ZG 2 have already started are. Its running time is short compared to the response time of the protective signal receiver. The counter Z, the z. B. in RCT technology with bistable multivibrators or in magnetic core technology can be constructed, counts the incoming pulses in this application example on a binary basis. The number of counter units required, e.g. B. flip-flops calculated one according to the formula n = log) lb z -I- 1, where z is the desired counter reading and n is the number of counter units to be used. You get a broken one Numerical value for n, this is rounded up to the next higher integer value. The redundant counter stage (the summand -! - 1) serves to protect against overflow. During operation, the outputs of the penultimate and the last counter level. combined via a mixer G1. Should a defined counter reading be tapped the corresponding outputs can be combined via a coincidence gate G3 which takes the place of the mixing gate G 1 (see FIG. F i g. 2).

F i g. 2 shows an advantageous circuit arrangement of the counter Z. with downstream storage stage SP, based on five counter stages, a maximum of fifteen pulses, corresponding to 2-n-1, can be counted. It deals is a four-stage counter with bistable multivibrators I to IV and the redundant level V for protection against overflow. All illustrated bistable flip-flops, whose input is marked with e and the output is marked with a, are located in the Zero position. If a defined counter reading, e.g. B. 12, can be achieved the outputs of the relevant counter stages instead of via the mixer G 1 via a Coincidence gate G3 switched to the storage stage SP. The two-stage amplifier V 1 is used to decouple the downstream gate G4. The storage level SP contains the storage pulse from the timer stage ZG2. With this memory pulse the bit present at the counter output az is transferred to the memory SP. Will If a "1" is stored, then the amplifier V 2 and the line A (F i g. 1) The protection criterion is passed on to the disconnector control.

In Fig. 1, an erasure stage LM is connected in parallel to the output of the amplifier V 2, which erases the memory after a predetermined period of time, ie brings it into the zero position, if no memory erasure is provided by the circuit breaker control via the line T. The erase level can be, for. B. be constructed so that a capacitor is charged by the protection criterion via a diode and a voltage divider made of resistors, which can respond to a relay connected in parallel when a certain voltage is reached at the capacitor terminals. A normally open contact of this relay clears the memory SP via the clearing line and the clock line from ZG2 through the mixing gate G 2. In order to ensure that the inverse erase pulse is applied to the other memory input during erasure, the counter output az is blocked by the coincidence gate G4. In the event of deletion by the disconnector control via line T, the extinguishing stage LÖ can be disconnected by a switch S and thus rendered ineffective.

F i g. 3 shows two pulse diagrams as they can occur in the event of protection. Diagram a shows the pulse sequence of protection signal S and interferer St behind the trigger stage TR, diagram b shows the rising edges of the pulses after differentiation by the first counter stage. The protection signal frequency was assumed to be 10 kHz and the system bandwidth to be 2.5 kHz, resulting in an average interference pulse duration of 400 Fis. The interferer's pulse repetition rate was assumed to be 300 Hz. The interference pulse should oscillate within itself at a frequency that is above the protection signal frequency.

As can be seen from the diagrams, four counting pulses Z are simulated by the interference pulse St. However, if the counter reading is set to at least 8, the protection criterion can only be taken when there is protection signal S at the counter output. The response time of the digital protection signal receiver is accordingly 1 ms, with the counter being queried at time A and the counter reading being deleted at time ZL. In the worst case of protection signal transmission, the digital protection signal receiver is started by an interference pulse, the protection signal follows at such a time interval that the counter is not filled in the existing counting period. The digital protection signal receiver then needs a counting period to recognize the protection signal. In this worst case, which is not the rule, the response time of the digital protection signal receiver is 2 ms.

Claims (14)

Claims: 1. Circuit arrangement for carrier-frequency transmission of protection signals over high voltage lines with suppression of the transmission of a protection signal over the line system occurring interference pulses, wherein the Protective signal sent out on the transmitting side in the high-frequency range and on the receiving side from the high-frequency to the low-frequency frequency range is implemented and processed, characterized in that a digital protective signal receiving device the modulated, carrier-frequency protection signal already in the high-frequency carrier frequency band processed with the omission of the otherwise usual conversions in lower frequencies. 2. Circuit arrangement according to claim 1, characterized in that the carrier frequency Protection signal and the interference pulses are limited in a limiter stage (B), whereby the limiter input is broadband compared to the available frequency band, and that a downstream trigger circuit (TR) converts the limited signals into square-wave pulses forms a pulse length shaping stage (PLF) and the downstream evaluation circuit are fed. 3. Circuit arrangement according to claim 2, characterized in that that in the evaluation circuit one controlled by a timer circuit (ZG1) Counter (Z) is used, where. one received and one at the output of the pulse length shaping stage (PLF) pulse train present in the counter in a rectangular pulse form of the same duration is counted, the counter reading of a second timer circuit (ZG2) after is queried a specified time and then deleted. 4. Circuit arrangement according to claim 3, characterized in that the predetermined value for the counter (Z) Counter reading or the duration of the count is chosen so that only the protection signals alone are able to fill the counter (Z) in the given time and enter Submit protection criterion to the circuit breaker control (A). 5. Circuit arrangement according to claim 4, characterized in that the counter (Z) with an additional Counter stage, which serves to protect against overflow, is provided. 6. Circuit arrangement according to claim 5, characterized in that the counter (Z) has a delay element (LZG) is connected upstream so that the pulses emitted by the pulse length shaping stage (PLF) first start the timer levels (ZG1, ZG2) and only then get to the counter (Z). 7. Circuit arrangement according to claim 6, characterized in that the pulse length shaping stage (PLF) emits pulses of a certain duration at its output, which are slightly less than is the protection signal pulse duration. B. Circuit arrangement according to Claim 2, characterized marked, .that the trigger circuit (TR) has an adjustable response threshold possesses to signals the level of which is below the useful amplitude of the Keep evaluation circuit away. 9. Circuit arrangement according to claim 6, characterized characterized in that two timer stages (ZG1 and ZG2) are used, both of which started together, with the first setting the counter for a certain period of time (Z) releases, while after this time period the second (ZG2) releases the meanwhile and the counter (Z) returns to the zero position. 10. Circuit arrangement according to claim 9, characterized in that the second Timer stage (ZG2) stores the count reached in a memory before deletion (SP), and according to this value, the circuit breaker control is activated via an amplifier (V2) (A) affected. 11. Circuit arrangement according to claim 10, characterized in that that an extinguishing device (LÖ) is switched on at the output of the amplifier (V2), which clears the memory (SP) after a predetermined period of time, if from the circuit breaker control (A) the memory (SP) has not been deleted. 12. Circuit arrangement according to Claim 11, characterized in that the extinguishing device (LÖ) consists of a capacitor consists of resistors from the protection criterion via a diode and a voltage divider is charged and when a certain voltage is reached at the capacitor terminals a relay connected in parallel can respond. 13. Circuit arrangement according to Claim 7, characterized in that the pulse length shaping circuit (PLF) is designed as a monostable multivibrator. 14. Circuit arrangement according to claim 9, characterized in that the timer stages (ZG1 and ZG2) as monostable Flip circuits are formed. Documents considered: V en z k e: "Remote control systems in the energy supply company", Essen 1950, pp. 160, 161; Reprint from the Siemens magazine »Carrier-frequency transmission of selective protection signals in high-voltage systems «, SH 8072/12601, p. 3.