DE2065593C3 - Reading device with testing device for data from a recording medium in the form of a punched card - Google Patents

Description

The invention relates to a reading device with a test device for data from a punched card-shaped recording medium, in which the perforations in different, parallel decks are arranged in columns are, with a keypad for entering comparison data, a comparison device for the read and keyed characters as well as a test notch, which is generated by the comparison device in the event of a match of all read and keyed characters can be actuated

A reading device with a testing device of the type mentioned at the beginning is, for example, from the DT-PS 6 10 201 known This contains an arrangement for checking punch cards, the perforations in several parallel Contains perforated decks. A keyboard is provided for keying in the comparison characters, for each individual deck a separate sensing device and a switch so that that for all common keypad one after the other with the sensing devices the various perforated decks is brought into working connection. Sensing, testing by comparing the character read and typed in, it is carried out in columns, initially within the first Hole decks whose separate sensing device just passed through the switching device with the keyboard is connected and then the test is carried out in a corresponding manner by switching to the other hole decks. After all perforated decks have been successfully checked, one after the other, column by column Notching by the test notch if the test was successful, d. H. if no error between the comparison data and the punched data has been established. In this known arrangement The keyed and punched data are compared directly without any intermediate storage takes place and an error may be shown in each individual column if the Fields created by two turns of magnets do not cancel each other out. Except for the Considerable mechanical effort, which is necessary with this known arrangement, is the test relatively slow, because the comparison is made in columns one after the other and in each case directly in the addressed Column takes place. Reading and checking takes place in principle with this arrangement, although the perforated decks are parallel contains, however, as with the examination of conventional punch cards, in which the punchings are only in one hole area are arranged in columns one behind the other.

For example, one arrangement for examining punch cards column-by-column that does not contain parallel decks is known from DT-PS 5 61579. This is done by reading the perforation and keying in at the same time of the comparison sign from a keyboard checked whether the information in the read hole column match the coding of the entered comparison sign. If this is the case, then the The carriage carrying the punched card is pushed forward one column and the next punched column can be opened again can be read and compared by keying in the next comparison character. If in the end of all Perforations checked column by column Correspondence between the perforations and the keyed in column by column There is a comparison sign, then a test notch is activated, which a visible notch on the card to indicate successful testing. This arrangement is column-wise simultaneous reading and checking of the perforations with the typed character and the checking of normal punch cards that do not have holes in different, parallel decks. The test takes place step by step or column by column, without intermediate storage of the read and / or keyed in Comparison data takes place. Here is the one too

mechanical effort quite considerable and the speed with which the device works, very limited

From the German patent application 1 2224 IXb / 43a, published on October 27, 1955, there is a device known for sensing punch cards, which contains several decks, and a sensing device for each deck of cards intended. There are levers above the feeler pins, which all fall into the card holes at the same time provided that make electrical connections according to the positions of the feeler pins. Means An additional set of levers can be used to generate special impulses for special purposes are storable. This known arrangement relates to the normal scanning of punch cards, without anyone Indication of a review of the data. This known device for reading punch cards is about it in addition, nothing in the direction of a test or intermediate storage of data and comparative data can be obtained.

For the creation and processing of recording media in the form of punched cards, which are then subsequently stored in a data processing system processed in different ways and according to different points of view it is necessary to be as simple as possible, easy to use and fast working Machine to have. This should in particular also be able to be operated by workers who have been trained in a short period of time. the As an independent unit, the machine should, in particular, also offer the possibility of recording the created / recording cards to check for their correct execution and also to note this.

The object of the present invention is to meet these conditions and requirements, and in particular to design a reading station with testing device of the type mentioned in such a way that the already created punch card read in a simple and clear manner and in the shortest possible time and with the comparison data to be entered can be compared and checked. In particular, the possibility be given that reading the already created punch card with the usual speed of the reading station he follows.

This object is achieved according to the invention in that the perforated in the mutually parallel decks Time-division multiplexed characters from the reading station in columns for all decks essentially at the same time are readable that a memory is provided for receiving the read characters, that an input register is provided in which the entered from the keypad by successive actuation of data keys Data can be stored, and that the comparison device stores the stored, mutually associated Compares characters.

With the help of this solution according to the invention, punch card-shaped recording media containing several contain parallel areas of decks, in which perforations are made in columns, in very short Time is first read and the read data is stored in a memory. For testing the comparison data from the original are keyed in again and depending on the position or column in which the to comparative information is available, the keyed-in information is matched with the previous one in the memory read information compared. If errors do not occur, this procedure applies to the entire recording medium card until finally at the end, after all in perforated on the card and read by the reading station as well as data entered from the keyboard Comparison data by the Prüfksrber on the card a visible sign is noted, namely that the punched data completely match the gene desired.

According to an advantageous embodiment of the reading device according to the invention with a test device provided that the reading station time division multiplexed columns substantially at the same time reads that the reading station is connected to the memory in such a way that that of the various decks read characters are entered in different, spaced apart areas of the memory, so that after the reading process is complete, all characters in the first deck before the characters in the next Decks are stored in the memory, and that the comparison means characters which are determined by the successive Actuation of the data keys in the input register occur, with successively occurring, compares characters circulating in memory.

According to a further advantageous embodiment of the The device according to the invention is provided that in the reading station in each hole position of a deck Phototransistor is provided that these in a line, corresponding to the hole positions lying in a line several columns of different decks are arranged and that on the other side of the card a lamp is provided.

According to a further advantageous embodiment of the reading device according to the invention with a test device it is provided that the comparison between a keyed in character and one from the data card characters read and contained in the memory if they do not match by entering the again Comparison sign can be repeated several times. This can be advantageous in the event of incorrect keying of the comparison symbol a repetition can take place immediately without the entire map being repeated by The beginning would have to be read and accordingly the data to be compared would have to be entered again would have to be.

With reference to the following specific description and the preferred embodiment shown in the figures the reading station according to the invention with testing device, which is in connection with a data recording device is shown, the structure and mode of operation of the invention is explained in more detail. The figures show in detail

F i g. 1 shows a plan view of a data card which is connected to the reading station according to the invention with a test device is read and checked,

F i g. 2 is a perspective view of a device in which the reading and testing device according to the invention is usable,

F i g. 3 is a plan view of the keypad of the data card processing device;

F i g. 4 is a diagrammatic illustration showing the relationship between the bits, the characters and the columns, which are stored in a memory of the data card processing device revolving data shows

Fig. 5 is a plan view of the data card transport device, in the course of which the inventive Reading and testing station is arranged,

6 shows a side view of the card transport device according to FIG. 5,

F i g. 7 is a partial view taken along line 7-7 of FIG

F i g. 8 the way in which the F i g. 8a to 8h composed need to be to complete a F i g. 8 to form. The F i g. 8 shows the data input part of the electrical Control circuit for the data card processing device, the memory and control part of the circuit, the test part of the circuit and the reading part of the circuit, the data input circuit in particular in the F i g. 8a, 8b and 8d, the storage and control circuit is shown in particular in FIGS. 8c and 8d, the test circuit in particular in FIGS. 8d and 8e and the reading circuit in particular in FIGS. 8f, 8g and 8h is shown,

F i g. 9 the circuit for generating control signals corresponding to the individual decks of the dalenkarte,

Fig. 10 the clock, which is part of the electrical Forms control for the data card processing device.

F i g. 11 the relationship between the cycle times, the Bit times, the character times and the column times that form the output of the clock.

The F i g. 1 shows a data card 100 that can be used with the data recorder or punch. In its lower part, the data card 100 has a perforated field which has three decks 102, 104 and 106 into which holes can be punched. The first deck 102 contains 32 columns for receiving holes; the second deck 104 contains columns 33 to 64 and the third deck 106 contains columns 65 to 96. Each of the decks 102, 104 and 106 contains six horizontal rows 1, 2, 4, 8, A and B. Therefore, up to six holes are punched in each of the columns of each deck 102, 104 and 106.

The upper part of the data card 100 forms a print field which has three print lines 108, 110 and 112 . The print line 108 contains the print positions 1 to 32, the print cell 110 the print positions 33 to 64 and the print cell 112 the print positions 65 to 96. The print positions in the different print lines correspond to the columns in each of the decks 102, 104 and 105 of the card shown, the letters TOM in printing positions 11, 12 and 13 in the perforations in columns 11, 12 and 13 in deck 1.

The data card 100 can be relatively small compared to previous conventional data cards and can be about 8.25 cm long and about 6.67 cm wide. The upper left corner of the card is cut off to have a diagonal corner 114 for quick stacking of the cards 100 . This allows the cards to be easily and securely arranged in the same position within the stack.

The data card recorder or punch is shown in FIG . 2 This contains in particular a keyboard 128 for operating the device, a device arrangement 126, an arrangement 140 in which a number of several switches is housed a card storage compartment 144, a card transport which is generally designated 142 and the fiction, contemporary reading station 158 as well contains the associated test notch 160 and also a storage compartment 166 for the finished data cards 100.

In Fig. 3, the keypad 128 is shown containing a number of data keys 132, a space key 134, an upper shift key 136, a lower shift key 138 and other function keys The pre device assembly 126 further includes a number of switches 140 (see. Figure 2), the are arranged above the keypad 128.

The device arrangement 126 contains a card transport device 142 for the cards 100 (see FIG. 5). The transport device essentially includes a storage compartment 144, a take-up roller 146, a transport roller 148, a card sensor 150 with a lamp 198 and several card sensor optical fibers 200, a punch 152, a step scarf trad 154, a lock 156, a reading station 158, a validator 160, a printer 162, and a storage bin 166.

The index wheel 154 is driven in increments of partial rotation by any selectable drive mechanism.

• Mechanism driven to thereby advance a card 100 by the distance of one column (such as from column 10 to column 11) . An upper pulley 226 is disposed over the indexing wheel 154 and is rotatably mounted on a lever 228 which in turn is rotatable about a rotatable flexure mount 230. A magnet 232 is provided for vertical movement of the lever 228 .

The reading station 158 includes 18 phototransistors 234 mounted in a row on a circuit board 236 in an upper reading station 238. The reading station 238 is mounted above a lower reading station 240 which in turn is positioned directly above the lamp 198 .
The test notch 160 contains a punch 242 which is actuated by a lever 244. For this purpose, the armature 248 of a magnet 246 is connected to the lever 244 by a connecting rod 250 (see FIG. 7).

The in the F i g. The control system shown in FIGS. 8 and 9 for the machine essentially comprises a data input part 350. a storage and control part 35Z, a card transport part 356, a reading part! 362 and a test part 364.
The storage and control part 352 contains a magnetic

strictive delay line 366 in which data bits circulate from end to end and also includes an A register 368 through which these data bits also pass from end to end. The A register 368 is a series of flip-flops shift register and various signals are derived from this register. For this reason, the preferred arrangement of the data bits passing through the delay line 366 and the A register 368 is described below.

The data circulating through the delay line 366 and the A register 368, for example, have the form as shown in F i g. 4 and consists of 96 columns (one column in the circulating memory system corresponds to one column on the punched SS card 100), each of which contains the characters Fl, PZ PA. PZ, TAF, Lö and DR has Each of these characters is built up in sequence from bits 1, 2, 4, 8, A, ß, C and D. Each of the characters can have a duration of eight microseconds, for example. That is why every-

des of the bits a microsecond duration if the bits and characters at any point in either the delay line 366 or the A register 368 walk past.

The system uses different time signals and ⁶ S is under the control of a clock 370 (see FIG. 10) which controls the timing as shown in FIG. 11 is shown indicates according to the Fi g. 10, the clock 370 sees the BH times (BZT) 1, 2, 4, 8, A, B, C and D

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each of which has a duration of one microsecond. Each of the bit times is divided into the A and B clocks. A cycle A has a duration of 500 nanoseconds for each of the bit times and a cycle fl also has a duration of 500 nanoseconds and begins after a quarter of a bit time, whereas cycle A is present at the start of a bit time. The clock generator 370 also generates the character times P1, P 2, P4. P3, TAF. LO and DR. Each of these character times has a duration of eight microseconds and includes all bit times. Furthermore, the clock generator generates column times, each of which has a duration of 5b microseconds. (Each of these column times includes all times of the various signs.

The data entry part 350 shown in FIG. 8a and 8b includes the keypad 128 connected to an input register 372 via a data bus 373. The input register 372 contains a series of six latches, namely latches 1, 2, 4, 8, A and B. These latches are connected to AND circuits 374, 376, 378, 380, 382, and 384 via the Lines 386, 388, 390, 392, 394 and 3% connected. The AND circuits 374, 376, 378, 380, 382 and 384 also have the input lines 398, 400, 402, 404, 406 and 408. These lines carry the time signals “bit time 1” or “bit time 2” or “bit time 4 "or" bit time 8 "or" bit time A " or" bit time ß ", which are derived from the clock generator. The AND circuits 374,376. 378,380,382 and 384 are connected to an OR circuit 340 which has an output line 412 . The line 412 forms an input to an AND circuit 414. The AND circuit 414 has two additional inputs, namely the lines 416 and 418. The line 416 carries the time signal "TAF", which is derived from the clock generator 370 , and that Represents the area (characters) of a column in which the information from the keypad 128 is stored.

The line 418 also forms an input to an AND circuit 420, which also has the line 416 as an input, which has the time signal "TAF". The line 418 also forms an input to another AND circuit 422, which has the additional lines 424 and 426 as inputs. Lines 424 and 426 carry the time signals “P3” and “Bit time /><, which are derived from clock generator 370. The AND circuits 420 and 422 are connected to an OR circuit 428 to which an inverter circuit 430 , which has the output line 432 , is connected.

The keypad 128 is connected to a keypad controller 434 via line means 436 . The keypad control 434 has two outputs in the form of lines 438 and 440. Line 438 carries an "any data key" signal which occurs when any of the data keys 132 or the space key 134 is depressed. The line 440 is connected to a keypad reset magnet 442 which acts on the keypad 128 in such a way that the keypad is reset to the working condition after each actuation of a key on the keypad 128.

Line 438 is connected as an input to an AND circuit 444. This AND circuit 444 has additional inputs in the form of lines 446, 424 and 448. Line 424 carries the time signal "F3" as described above, and line 446 carries this Signal »A REG B Bit«. The “A REG B bit” signal is derived from the A register 368 and forms the special bit that is present in position B of the register 368 . The line 448 carries the signal "bit time 4 and clock β" and this signal is a time-determining signal which is derived from the clock generator 370 and appears when bit time 4 and clock B coincide.

The AND circuit 444 is connected on the setting side to an interlock circuit 450 , which can be referred to as a keypad ready interlock. This interlock 450 has the line 418 as an output, so that the line 418 carries the signal "keypad ready". An OR circuit 452 is connected to the reset side of the interlock circuit 450 and has two inputs in the form of lines 454 and 456. Line 456 carries the "EAS signal", which occurs to reset all interlock circuits immediately when the engine is started, and line 454 forms the output of an AND circuit 458. The AND circuit 458 has the lines 424 and 400 as inputs, which carry the time signals "P3" and "bit time 2" (BZT 2), as already described above.

Line 418 forms an input line to an AND circuit 460 which has additional inputs in the form of lines 402, 462 and 464 . Line 402 carries the “bit 4” signal, as already mentioned above, and lines 462 and 464 carry the time signals “LOa (punching) and“ column 96 ”, which are derived from the clock 370. The AND circuit 460 is connected on the setting side to a latch circuit 466 , which can be referred to as a K to P transfer latch. The latch circuit 466 has a line 468 as an output which carries the signal "K to P transfer latch". An OR circuit 470 , which has the input lines 472 and 456 , is connected upstream on the reset side of the latch circuit 466. Line 456 carries the "EAS" signal and line 472 forms the output of an AND circuit 474. AND circuit 474 has three inputs. These are the lines 400, 462 and 464 which carry the time signals “bit time 2” or “L0” or “group 96”.

Two AND circuits 476 and 477 are connected upstream of an OR circuit 478 , which in turn is connected to a column display controller 479 . AND circuit 476 has three inputs. namely the line 418, which carries the "keypad ready" signal as mentioned, the line 480, which carries a signal "not keypad test lock" and the line 481, which carries the signal "test switch". The “test switch” signal is derived from a test switch 482 which is arranged on the switch strip 140. The AND circuit 477 has two inputs, one of which is the line 418 with the "keypad ready " signal and the second of which is a line 482 which is connected to the line 481 via an inverter 484 but conduit means 485 connected to a column indicator 486 which is of a conventional type with a

Plurality of luminous stripes 487 is

The memory and control part 352 (see FIG. 8c) contains the delay line 366 and the A register 368, as mentioned earlier. A line 488 forms the output of the delay line 366 and this line is connected to an AND gate 490 as one of two inputs. The other input of the AND circuit 490 is an inverter circuit 49Z which has the line 494 as an input

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The AND circuit 490 is connected upstream of an OR circuit 496 which has an output in the form of a line 498 which forms the input to the / t register 368 . Another AND circuit 500 is connected upstream of the OR circuit 496. This AND circuit 500 has two inputs, one of which is the line 494 and the other is the line 502 , which also forms the output line of the Λ register 368.

An AND circuit 504 has line 502 as one of five inputs. The other inputs are the lines 432, 50 (5, 508 and 510. The lines 506 and 510 carry the signals “Not EAS” and “Erase markers”, respectively, which are derived in a manner to be explained. The AND circuit 504 has its output in the form of a line 512, which forms one of the inputs of an OR circuit 514. The OR circuit 514 has five additional inputs, these are lines 516, 518, 520, 522 and 524. Line 518 forms the output the AND circuit 414. The lines 516, 520, 522 and 524 carry the signals “write read marks” or “read data” or “write marks” or “write error marks”, the origin of which is described below.

The output of the OR circuit 514 is formed by a line 526, which is at the same time the input to an AND circuit 528 . The AND circuit 528 has an additional input in the form of a line 530. The line 530 carries the time signal “Not clock A”, which is derived from the clock generator 370 and forms the inversion of the signal “Clock 4”. The output of AND gate 528 is line 532 which forms the input to delay line 366 .

The storage and control section 352 also contains a start control 534, which has two outputs in the form of lines 456 and 536. Line 456 carries the "EAS" signal previously mentioned and an inverter 538 is connected to EAS line 456 to generate the "Not EAS" signal on line 506? U. An OR circuit 540 has lines 536 and 468 as inputs. This OR circuit 540 is connected upstream of an AND circuit 542 as one of three inputs. The other two inputs of the AND circuit 542 are the lines 534 and 426, which carry the time signals "P3" and "Bit time £ λ". The AND circuit 542 is connected upstream of an OR circuit 544 , the output of which in the form of a line 522 carries the signal “write markings”.

Another AND circuit 548 is also connected upstream of the OR circuit 544 and has three inputs, one of which is the line 426 which carries the signal "bit time Dt" . The second input is the line 468, which carries the signal "K to PÜbertragungsverriegelung" and the third input is a line 550 which carries the time signal "P2" which is derived from the clock 370. A third AND circuit 532 has three inputs, one of which is the line 550 which carries the time signal "P2". The others the two inputs are lines 554 and 556. Line 554 carries the signal “bit time Ck, which is derived from clock 370 and line 556 carries the signal“ start of printing ”, which, as described below, is derived from this third AND Circuit 552 is also connected upstream of OR circuit 544

Line 468 is connected as one input to an AND circuit 558 , which has two inputs. The other input is line 416, which carries the "TAF" signal. The AND circuit 558 is connected upstream of an OR circuit 560. The OR circuit 560 has an output in the form of the line 494. Another AND circuit 562 is connected upstream of the OR circuit 560 and has two inputs, namely the lines 556 and 462. As already mentioned, the line 462 carries the time signal "LO" and the line 556 carries the signal "start of printing".

According to FIG. 9 are deck locks 694,696 and

ίο 698 provided in accordance with decks 1, 2 and 3. The deck 1 latch 694 is connected to an AND circuit 702 by a line means 700 . This AND circuit 702 has three inputs, namely lines 464, 648 and 402, which carry the time signals “Column 96” or “DR” and “Bit time 4”. The deck 1 latch 694 has its output in the form of a line 704. On the reset side, the latch circuit 964 is connected to a line 706.

The deck 2 latch circuit 696 is connected on its setting side by line means 706 to an AND circuit 708 . This AND circuit 708 has three inputs with lines 648 and 402, which carry the signals "DR" and "bit time 4", respectively. The third input to the AND circuit 708 is formed by a line 710 which carries a "column 32" signal. derived from the clock 370 carries. The latch circuit 6% has a line 712 as an output. A line 714 is connected to the reset side of the latch circuit 6%.

The deck 3 latch 698 is connected by line means 714 to an AND circuit 716 which has three inputs. Two of these inputs are lines 648 and 402, which carry the time signal "DR" and "bit time 4". The third input to the AND circuit 716 is formed by a line 718 which carries a signal “column 64” which is derived from the clock generator 370. The output of the latch circuit 698 is a line 720 and the reset side of the latch circuit 698 is connected to the line 700

The reading part 362 (see FIG. 8, in particular FIGS. 8f, 8g, 8h) is under the control of the reading button 570, which generates a signal “reading button” on the line 568. The set side of a read operation interlock circuit 822 is connected to the line 568 , and an OR circuit 824 is provided on the reset side of the interlock circuit 822 . The OR circuit 824 has two inputs, one of which is the EAS line 456 and the other is a line 826 which carries the "read complete" signal. The latch circuit 822 has two outputs, namely a line 828 which carries the signal "read operation" and a line 628 which carries the inverse signal "no read operation".

The line 828 is led as an input to an UNP * circuit 832. This AND circuit 832 has a second input in the form of a line 598 which carries the signal “hole start”. The AND circuit 832 is an OR circuit 834 connected upstream

The second AND circuit 836 is also connected upstream of the OOWSr circuit 834. This AND circuit 836 has two inputs, one of which is the line 826 and the other is the line 481 which carries the signal “prefwitch”

⁶ S The OR circuit 834 has its output m in the form of a line 840 which carries the signal "read counter start" and this line 840 is connected to a counter 8 * 2 a The counter 842 is mh the line 590. de

a si C ti S ν E d h r il d a s>

the signal "Loche weiter" carries, connected and the counter counts the pulses of the Loche-weiter line 590, which serves as a driver for the counter.

The counter 842 has a line 844 as an output and a signal through the 13th counter step is on this line generated after the start of counting of the counter 842. Line 844 is used as the input of an AND circuit 846, which on the setting side of a Schrcib / Lcse mark locking circuit 848 is upstream. AND circuit 846 has two inputs, the second of which is line 682, the carries the time signal »column 1«. The interlock 848 has the line 464 with the time signal "column 96" of its Reset side fed. The latch 848 has its output in the form of a line 850 which is one of three inputs of an AND circuit 852 forms. The other two inputs of this AND circuit 852 are the lines 736 and 554, which carry the time signals "PI" and "bit time C". The AND circuit 852 has the line 516 as an output with the signal "write / read marks".

The line 844, which forms the output of the counter 842, is also connected to the setting side of a read start interlock circuit 854 connected. The latch circuit 854 has an OR circuit 856 on its reset side. This OR circuit 856 has has two inputs, one of which is EAS line 456 and the other is line 826 with the signal "Read completely".

The start of reading latch circuit 854 has its output in the form of a line 860 which forms one of the outputs of an AND circuit 862. The AND circuit 862 also has inputs from lines 648 and 638, which carry the time signal “D /?” And the signal “synchronous transport” and the AND circuit also has inputs from lines 864, 866 and 868. The line 864 carries the signal »A REG D«. which is derived from the D flip-flop in the A register 368, and the line 866 carries the time signal "bit time D and clock β". which is an impulse when bar B and frame D meet. The line 638 carrying the signal "synchronous transport" forms the output of a synchronous transport latch circuit 870 which has an AND circuit 872 on its setting side. The AND circuit 872 has two inputs, one of which is the line 590 that carries the signal “holes further” and the other of which is the line 682 that carries the time signal “column 1”. The line 464, which carries the time signal “column 96”, is connected to the interlock circuit 870 on the reset side.

The AND circuit 862 is connected upstream of a read mark on the setting side. The interlock circuit 874 has an OR circuit 876 on its reset side. The EAS line 456 and a line 878 have the two inputs. The line 78 forms the output of an AND circuit 880. This AND circuit 880 has two inputs, namely from the lines 648 and 554. which carry the time signals »Dft« or »bit time Cn.

The VerriegehingsschaltUTig874 has its output in the form of a line 882, which forms one of three inputs of an AND circuit 884. The AND circuit 884 also has inputs from lines 5S4 and 736, which carry the time signals "Bitzelt Cn or" P! " carry. The AND circuit 884 is connected on the setting side of a seeker latch circuit 886. The latch circuit 886 is connected to the deck reset line 646 on its reset side. The line 646 forms the output of an AND circuit 888. The AND circuit 888 has two inputs, one of which is the line 648 with the time signal “DR” and the other of which is a line 890. Line 890 forms the output of an OR circuit 892. This OR circuit 892 has three inputs, which are lines 710, 718 and 464, which carry the time signals "Column 32", "Column 64" and "Column 96". carry. The output of the seeker latch 886 is a line 868 which is connected to the AND circuit 862 and forms the fifth input to the AND circuit 862.

■ 5 The line 882 also forms the input to one AND circuit 894. This AND circuit 894 has a second input in the form of line 464 with the time signal "Column 96". The output of AND circuit 894 is line 826 with the "read complete" Signal.

Furthermore, the line 882 forms an input to an AND circuit 8%. AND circuit 896 has two further inputs, namely from lines 736 and 554, which carry the time signals "PI" and "bit time C". The AND circuit 8% is connected upstream of an OR circuit 898 and an inverter circuit 900 is connected to the OR circuit 898. The output of inverter circuit 900 is line 508, which forms an input to the AND circuit 504.

Furthermore, the line 882 forms an input to another AND circuit 902, which is also the OR circuit 898 is connected upstream. The second input to this AND circuit 902 is line 462. which carries the signal »LO«.

Furthermore, the line 882 forms an input to an AND circuit 904. The AND circuit 904 has two additional inputs, namely from a line 906 and from line 462, which carry the time signal »LO« wearing. The output of AND circuit 904 is line 520, which is an input for the OR circuit 514 forms and carries the signal "read data in".

The reading station 158 contains 18 phototransistors 234i to 234i8 (see FIGS. 8f and 8g). These phototransistors are in a row at right angles to the direction of movement

of cards 100 arranged so that they form the openings in the three lined up columns of a deck can sense, for example to simultaneously sense the openings in columns 2, 34 and 66 of a Card 100. The phototransistors 234i to 234s are arranged to detect holes in the deck 1 which Phototransistors 2347 to 234 ″ are arranged to discover holes in deck 2 and the phototransistors 234i3 through 234i8 are for hole detection arranged in deck 3 The emitters of the photo

^S5 transistors 234t to 2346 are connected to the collector of a transistor 908, the base of which is connected to line 704, which carries the signal "Deck 1 lock". A transistor 910 is connected in the same way to the emitters of the phototransistors 2347 to 234u. The base of this transistor 910 is connected to the line 712, which carries the signal "Deck 2 Lock". The emitters of the phototransistors 234i3 to 234 "are connected in the same way to a transistor 912 whose base is connected to the line 720, which consists of the signal" The collectors of the first phototransistors of each deck are connected to a line 914 and this line is connected to a sense amplifier 316.

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which is excited when a hole in one of the first rows of the particular sampled columns is present in a corresponding manner are the phototransistors of the second, the fourth, the eighth, the A and ß-series with lines 918, 920, 922, 924 and 926, which in turn are connected to sense amplifiers 928, 930,932,934 and 936.

The sense amplifiers 916, 928, 930, 932, 934, and 936 are connected to AND circuits 938, 940, 942, 944, 946 and 948, respectively. Each of these AND circuits has two inputs, one of which comes from the sense amplifiers just mentioned and the others are the lines 398, 400, 40Z 404, 406 and 408, which carry the time signals "bit time 1" and "bit time 2" and Wear "bit time 4" or "bit time 8" or "bit time A" or "bit time ß". The AND circuits 938, 940, 942, 944, 946 and 948 are connected upstream of an OR circuit 950. The output of this OR circuit 950 is the line 906, which forms one of the inputs to the AND circuit 904.

The test part 364 (cf. FIG. 8, in particular FIG. 8e) contains a test comparison circuit 952. The comparison circuit 952 has inputs in the form of the / 4 register bus line 784 and from an input register bus line 954. The comparison circuit 952 has an output in the form of a line 956. The line 956 is connected as an input to an inverter circuit 958, the output of which forms a line 960. AND circuit 962 has four inputs, one of which is line 960. The other inputs are lines 418 with the "keypad readiness" signal and lines 462 and 670, which contain the time signals "Lft" or "bit time 2 and clock B". carry.

The AND circuit 962 has its output in the form of a line 964, which at times a signal "No test comparison" carries and the line 964 is connected to a latch circuit 966 on the setting side. The latch circuit 966 has an OR circuit 968 on its reset side. This OR circuit 968 has two inputs, namely lines 970 and 972. The line 970 carries at times an "error reset button" signal and this signal is activated by the error reset button 974 on the Keypad 128 generated.

The latch circuit 966 has two outputs, namely in the form of lines 976 and 480. The line 976 carries the signal “Check keypad lock” and this is fed to keypad control logic 434. An error lamp 977 is also connected to line 976. Line 480 carries the signal “Don't Check keypad lock "and this signal is fed to AND gate 476 which controls the column display 479 controls. Line 964 is also connected to an error counter 978. The error counter 978 has two outputs in the form of lines and 982. Lines 980 and 982 form the two Inputs of an AND circuit 984, which has its output on line 972.

Line 972 is the input of a third-party attempt failure latch on the setting side of this interlock circuit. The reset side of the interlock circuit is the line 416 with the time signal »keypad«. The output of latch 986 is in Form of a line 988 which forms one of three inputs of an AND circuit 990. The other two One of this AND circuit 990 are the line ".. 4,4 and 554, which the time signal »P3« and »Bitzejt S trSen. The output of AND circuit 990 is fe Line 524, which carries the signal “Write error message.

35

40

45 he rrimc. further includes a three-input AND circuit 994. One of these inputs is connected in the form of a line 850 to the write / read marking interlock 848 and the other inputs are in the form of lines 424 and 5 * which carry the simultaneous signals "P3" and "B.tze.t C", respectively. The AND circuit 994 is connected upstream of an inverter circuit 996, which has its output in the form of a line 5? 0 with the signal "delete marking"

The test part 364 also contains ewie Fehlkarte-VeSgefcng 998. which is preceded by an AND circuit 0001 on its setting side. The AND circuit "WO" has five inputs, the line 481 with the Sa "" Prefect ", the line 468 with the signal "K to P transmission lock", the ^ line _730 with the signal "A REG A", the line 424 with the target signal "P3" and finally the line 448 with the "time signal" bit time 4 and clock ß The Verne signal circuit 998 has the line 746 with the signal "print complete" on its reset line.

^fÜ The output of the faulty card locking circuit 998 is formed by a line 1002 which bidet one of the inputs of an AND circuit 1004. This AND circuit 1004 is connected upstream of a notch lock 1006 on the next page and has four lengths. One of these inputs is the line 481 with the "test switch" signal. Another of the inputs is line 468, which carries the signal "K to PÜbertragungsverriegelung". The fourth input is a line 1008 with the signal "Column 20". which is derived from the clock 370. Line 464, which carries the "column 96" signal, is fed to latch circuit 1006 on the reset side. The output of the latch circuit 1006 is connected to the test notch magnet 246 in the form of a line 1010.

The test part also contains a second Tverrieeelung 1012, which has an AND circuit 1014 on its setting side. AND circuit 1014 has two inputs, one of which is line 481 with the "test switch" signal and the other of which is line 1016. which is connected to the reading counter 842 and which carries a signal "Ten steps after reading complete". The output of the blocking circuit 1012 is connected to the second stepping magnet 274 via a line means 1018. The reset side of the latch circuit 1012 is connected to the K to P transfer latch line.

When the system is in operation, the start control is initially used 534 suggested to prepare the machine for operation. The commissioning of the start control 534 causes an "EAS" signal on line 456. That line 456 is. as previously described, connected to the reset side of various interlock circuits in the system. The »EAS« signal thus has the effect of resetting the various latch circuits. the For example, "EAS" line 456 is with interlock circuit 450 and interlock circuit connected via the OR circuit 452 and 470, respectively.

After the machine has been made ready for operation by switching on the start control 534, one of the data keys 132 or the space key

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134 on the keypad 128 may be depressed to make the appropriate entry in the data positions of column 1, which circulates through the delay line and the A register 368. The keypad 128 contains encryption logic for the purpose of activating one or more of the 1, 2, 4, 8, Λ and B bits. For example, bits 1, 2 and A are activated for the letter "7" (see FIG. 1). These activated bits are transmitted over bus 373 to input register 372 and input register 372 stores these bits in its various latches. Incidentally, the depression of the space key 134 advantageously does not cause any of bits 1, 2, 4, 8, A and β to be activated.

The keypad 128 contains a conventional system of locking balls that allow simultaneous depressions from more than one data key 132 or space key 134 at the same time. This The ball lock system is also under the control of the keypad reset magnet 442 in FIG Way that with magnet 442 energized, the keypad is normally used to depress a data key 132 or the space key 134 is ready for operation.

In normal operation, the keypad 128 and keypad controller 434 cooperate so that first the magnet 442 is de-energized to cause a temporary lock of the keypad 128, thereby on thus prevented any of the data keys 132 or the space key 134 from being depressed if one of these buttons has already been pressed. Immediately afterwards, the keypad controls 434 the re-excitation of the magnet 442, so that the keypad 128 is reset to the operational readiness, so that one of the data keys 132 or the space key 134 is actuated in this way can be.

After a recording card 100 has been punched and printed, the machine is used for checking the Card can be used especially for determining whether the correct characters are punched in the card were or not. This is done by placing the card in the supply bin 144 as the top card will. After the card is advanced from the supply bin 144 into the card transport mechanism has been, the operator can use the original document to key in the characters again. When the characters re-keyed in the verification operation are the same as those punched in the card the test /.u is over. A test notch 160 is then effective to make a small test notch on the To affix the card to show that it has been checked.

After a punched card 100 has been placed in the storage container 144 as the top card to the To begin the test operation, the read key 570 is depressed. The reading button gives the signal »reading button« on the Line 568 is off and this signal has the effect of advancing the card as in a punching operation will.

Depressing the read key 570 also has the effect that the read operation interlock 822 (cf. Fi g. 8g) is set, which the reading key line 568 is fed on their setting page. to indicate that a read operation is to be performed. A The "read operation" signal is generated on line 828 and this signal is sent to AND circuit 832 The AND circuit 832 continues to be supplied with the "start of hole" signal via line 598

The "beginning of hole" signal indicates that the card has arrived at column 0 in the hole station the reading operation that is now to take place, the operation on the card must begin with this position. In the case of punching the card, the punching starts at this station. However, in the case of reading, the Card can be advanced by 13 columns before it reaches the reading station 158

For this reason, the AND circuit 832> has fulfilled two inputs at this time and sees a signal "Read counter start" on line 840 via OR circuit 834. The read transport counter 842 is stimulated in this way and begins to work. The counter 842 is originally a binary counter, the Steps counts As already described, it is driven by the "continue punching" signal on the line 590, which is a signal. each time indicating that the card 100 is reaching a dwell.

After the counter 842 has counted 13 dwell times, it gives the signal »13. Step after the start of the hole «on line 844. This signal is fed to the AND circuit 846 together with the time signal “Column 1” on the line 682. The read-write mark interlock circuit 848 is set at this point in time, namely 13 steps after the card has left its column 0 position, and this interlock circuit 848 generates a signal on the line 850 which is fed to the AND circuit 852. The AND circuit 852 is also supplied with the time signals “P1” and “Bit time C” as inputs via lines 736 and 554. Therefore, a "write read mark" signal is generated on line 516 at time P1 and bit time C. According to FIG. 4 read marks are accommodated in bit position C in the characters P \ in each of the columns of the data circulating through the delay line 366. The "write read markers" signal on line 516 has the effect of writing such a mark in column 1, the signal on line 516 being transmitted via OR circuit 514 to line 526 and thus into the data loop. Similarly, read marks are written in columns 2 to 96 at bit position C in the character P1 in the data circulating through delay line 366 by the operation of AND circuit 852 which operates at each bit time C and time P1. At the end of a memory cycle, the time signal "column 96" is fed to the reset side of the read / write marker interlock 848 via a line 464 in order to reset the latch 848, so that at this point in time the AND circuit 852 becomes ineffective for writing read markers.

After reading marks have been written in this way in the 96 columns of data circulating through delay line 366, the system is now ready to read the data from card 10O. The signal »13. Step after LO start "on line 844 is also fed to start-of-read latch circuit 854 for setting this latch circuit. The latch circuit 854 outputs a “start of reading” signal on the line 860, which is fed to the AND circuit 862. Therefore, the AND circuit 862 is prepared for searching for reading marks. The AND circuit 862 is also a signal "not end of search interlock" on the line.

device 868 and this signal occurs at this time. In addition, the “synchronous transport” signal is fed to AND circuit 862 on line 638. This signal appears at this time after a step movement of the card 100. The time signals "DR" and "Bit time D and clock Β" are also sent to the AND circuit 862 via lines 648 and 866 together with the "A REG D" signal on the line 864 which is derived from the D flip-flop in the A register 368 is supplied to a printing mark is in the D Kippstufenposition of / t-register 368 to the DR time, the bit time D and the time of 1 akts B exist Therefore, the AND circuit 862 in its search for a read mark will determine such a read mark and have fulfilled all inputs at this point in time. This search operation by U NO circuit 862 begins in column 1 of the data circulating through delay line 366.

Upon the detection of a reading mark at position C of the character P 1 in column 1 of the data circulating through the delay line 366, the AND circuit 862 sets the reading mark latch circuit 874. A "reading mark lock" signal is generated in this way ² S on line 882 and this signal is fed to the two AND circuits 896 and 902. The task of these two AND circuits is to erase the read mark in column 1 and also to erase the old indication in the hole part of column 1 of the data circulating through delay line 366 in view of the fact that it is the hole part of the circulating data into which data is read during the read operation.

The AND circuit 8% outputs a signal to the inverter circuit 900 via the OR circuit 898. The AND circuit 896 is supplied with the time signals “PI” and “Bit time C” from lines 736 and 554. Therefore, while the read flag latch circuit 870 is set, the AND circuit 896 outputs a signal through the OR circuit 898 to the inverter circuit 900 during the time PI and the time for the bit Cab. The output of the AND circuit 900 is im general activated. However, when the AND circuit is 8% effective in this way, the signal on line 508 is removed so that the AND circuit 504 is inhibited during PI time and bit time C. The AND circuit 504 blocks in this way the output of the A register 368 at the time P1 and bit time C and in this way inhibits and deletes the read marking in column 1 which exists in this column at bit time C in the character P1.

The AND circuit 902 has the same effect as the AND circuit 896, except that it operates in place of the PI time and the bit time C during the LO time. The AND circuit 902 therefore causes all of the data in the LO character of column 1 of the data circulating through delay line 366 to be erased and invalidated, thus erasing any old data in the LOT part of column 1.

The "read tag lock" signal on line 882 is also operative using AND circuit 904 to read the data from the punched holes in column 1 of card 100 into the LO portion of the data circulating through delay line 366 . At this time the line I of the card 100 is localized via the phototransistors 234ι to 234e. A signal is provided to trai. Sistor 908 from deck 1 latch 694 via line 704. Therefore, if punched holes in column 1 in any of the 1,2,4.8. A and B positions appear, the corresponding phototransistors 234i to 234e are excited. As a result, the corresponding sense amplifiers 916, 928, 930, 93Z 934 and 936 are controlled via lines 914, 918, 920, 922, 924 and 926.The activated amplifiers of these sense amplifiers give signals to the corresponding AND circuits 938, 940, 942, 944, 946 and 948. These AND circuits are blanked on line 906 via OR circuit 950 at bit time 1, bit time 2, bit time 4, bit time 8, bit time A or bit time B , depending on the fact that these time signals these AND circuits are supplied via lines 398 or 400 or 402 or 404 or 406 or 408. These AND circuits arrange the data which are read out from the card 100 and which exist in these amplifiers in series on the line 906.

The AND circuit 904 is fulfilled when the reading marker interlock circuit 874 is set and during the LO time, which is present as a signal at the AND circuit via the line 462. Therefore, the data arranged in series on line 906 passes AND circuit 904 and line 520 to OR circuit 514 and to line 526 in the data loop with delay line 366. The stamped content of column 1 on card 100 is has been read into delay line 366 in this way, specifically into the LO character of column 1 of the data circulating through delay line 366.

Shortly after the reading marker interlocking 874 has been set, the seeker lock circuit becomes 886 is effective to terminate the scanning of the memory by the AND circuit 862 for read marks. The AND circuit 884 is fulfilled when the

Read mark latch circuit 870 is set and at bit time C and time P !, because these signals are fed to AND circuit 884 at these times via lines 554 and 736, and then seeker latch circuit 886 is set. This setting interrupts the "no end of search interlock" signal on line 868 which is fed to AND circuit 862, which then also inhibits AND circuit 862. Immediately thereafter, the read mark latch circuit 874 is reset at time DR and bit time C, which are fed to the AND circuit 880 via the lines 648 and 554 as signals. Seek end latch 886 is reset by the "deck reset" signal on line 646. This signal appears at the time for column 32 and is fed to the OR circuit 892 as a signal. The signal on line 868 appears in such a way that AND circuit 862 is able to find a read mark at bit position C in character P1 of column 33 of the data circulating through delay line 366. The circuit is then able, as in the case of the information perforated in column 1 of card 100, to read the holes in column 33 of card 100. The AND circuits 896 and 902 are used for erasing the reading mark in column 33 and for erasing any indication in the hole character in column 33 and the

AND circuit 904 is used for the subsequent writing of new data in column 33 of FIG data circulating through delay line 366 is read by phototransistors 2347-134i2 for the second deck due to the effectiveness of the "Deck 2 locking" signal on line 712 are effective. Reading the punched information in column 65 is carried out in a similar manner to that of the punched information Information in column 33, except that in this tall the phototransistors 234u to 234ie are effective through the appearance of the "Deck 3 lock" signal on line 720.

In this way the reading of a complete column is completed, namely the reading of the punched data from the in-line columns 1,33 and 5 65 of the card 100. At this point in time, the synchronous transport lock 870 is reset by the time signal "Column 96", which acts on the reset side of this interlock circuit via line 464. The "synchronous transport" signal on the line 638 is therefore interrupted and the AND circuit 862 is thus inhibited, so that at this point in time it can no longer be effective for the search for further reading marks. The AND circuit 862 then becomes effective again when another stepping movement of the card 100 takes place. At this point in time another "continue punching" signal appears on line 590, so that synchronous transport lock 870 is set again. The setting of the latch circuit 870 indicates that the card 100 has been advanced another step, that another "column" comprising columns 2, 34 and 66 of the card 100 are positioned in correspondence with the phototransistors 234i through 234i8 and thus can be read. _{The reading of the perforated information in columns 2,} 34 and 66 takes place in the same way as that of the perforated information in columns I 1 33 and 35 of the card 100. The reading of the perforated information in the remaining columns of the card takes place in the same way . At this point in time when the punched information in column 96 has been read, reader tag latch circuit 874 is set to output a signal on line 882. The "column 96" signal is present on line 464 and both signals are fed to AND gate 894 to generate the "read complete" signal on line 826. This signal is supplied to the reset side of the read operation latch circuit 822 through the OR circuit 824, and the read operation is terminated when this latch circuit 822 is reset.

The verification process consists essentially of re-keying the 96 columns of data from the original document, which should contain the same data as the card 100 that was just read, but assuming that no mistake was made, either in the initial key-in or in the new one Keying in. The new information, namely the data that is entered by re-keying on the keypad 128, is compared with the data that is read from the card and is now present in the LO character of the data circulating through the delay line 366. If the two pieces of data match, then no error in the original keying or in the overall Ncueintastung ⁶ - ^s makes Service. The card 100 is then scored by a check notch 160 so as to provide a visible indication that the card is checked point by point and is considered valid. The operator can then try again to key in the data. If a persistent error is made, even on the second keystroke, which is indicated by the continual lighting of the error lamp 977, the operator can then key in the data again with a third keystroke in order to cause the data in this particular column to be replaced by the Delay line 366 circumferential indication is changed. The simultaneous display is made because this recording card 100 has an error in attempting to check it, and the system therefore writes an error mark in the memory. This special card can be addressed as a faulty card and is not provided with the test notch.

The 96 columns of information were transferred from card 100 to those circulating through delay line 366 Information is read in as described above and the recording card is stopped at the check notch station, in which the card is below the notch 160, so that the notch 160 the card when it is applied notch back edge when the card is fully checked. The AND circuit 836 in the reading part 362 (see FIG. 8) receives the signal "test switch" supplied from line 481 and continues to receive the "Read complete" signal supplied from line 826 at this time. This is how the AND circuit is 836 is able to send a signal to the counter 842 via the OR circuit 834 and the line 840 give. At this point in time, the counter 842 generates a signal on the line 1016 which is called »10 steps after reading completely «can be designated. This is a signal that is then generated by the counter 842 is after the recording card 100 by 10 positions advanced past the point at which the reading of the card was finished. The signal "10 steps after reading complete" on line 1016 is followed by AND circuit 1014 along with the "test switch" signal on line 481 and AND gate 1014 is that way satisfies and sets the second stepping interlock circuit 1012. The switched on Latch circuit 1012 outputs a signal on line 1018 and the second stepping solenoid 274 is energized in this way, so that it lifts the second indexing pressure roller 266 from the card 100, in order to thereby stop the card 100 with its rear edge under the test notch 160. The card 100 remains in this position, which can be referred to as a test station for the complete test operation, in which the operator tries to re-key in all 96 columns of data, and so long until the test has been carried out in full. At this point in time, the test notch 160 is either actuated, to notch the card 100 or it remains unactuated in the event of a faulty card.

With the card 100 in its checking position within the card transport, the operator proceeds to the first Re-key in the column of the data from the original document. The encrypted information, accordingly the actuations of a data key 132 or the space key 134 are entered in the input register 372 is entered as described earlier. The keystroke has over keypad controls 434 also the effect, a signal “Any-

Appear a data key "on line 438 and cause AND gate 444 to look for keypad marks. This has already been described. When the keypad marker is located in the first column of data circulating through delay line 366 , AND gate 444 causes keypad ready latch 450 to be set to generate a "keypad ready" signal on line 418.

Bits 1, 2, 4, 8, A, and B from input register 372 are provided to compare circuit 952 over bus 954 . Bits 1, 2, 4, 8, A and B, which are present in the Λ register 368 , are also applied to the comparison circuit 952 via the bus 784 . In view of the fact that the 96 columns of data circulate through the A register 368 , these bits of data passing from the A register 368 to the comparison circuit 952 change continuously.

If the data from the input register 372 and from the / 4 register are compared, that is to say if both indications are the same, then the comparison circuit 952 outputs a signal on the line 956 . At this point in time, the inverter circuit 958 has no signal on its output line 960. On the other hand, if the data supplied by the / 4 register and from the input register 372 by the comparator 952 do not match, a signal appears on the line 956. The inverter circuit 958 sees a signal on line 960 . The "keypad ready" signal is effective when a keypad marker is located in column 1 of the data circulating through delay line 366. With LO Zeh and with bit time 1 and clock B. Signals that are fed to the AND circuit 962 via the lines 462 and 670, the AND circuit 962 provides a "check not equal" signal as the output signal on the line 964 . The use of the time signals "LO" and "Bit time 1 and clock £ fc" ensure that the AND circuit 962 is only effective in this regard with regard to the indication in the LO character of the first column of the data circulating through the delay line 366 which is the information that has been read in from column 1 of card 100.

The "check not equal" signal on line 964 is applied to the setup side of the keypad lock interlock 966 to set that interlock circuit and causes the "check keypad lock" signal on line 976. This signal on line 976 becomes the keypad control logic 434 supplied, which causes the signal on the line 440 for the de-energization of the keypad reverse steep magnet 442 is interrupted in order to block the keys 132 and 134 of the keypad. The "check keypad lock" signal on line 976 also has the effect that an error lamp 977 lights up, which indicates to the operator that an error has occurred and is recorded in the error counter 978. The counter 978 then causes an output signal to be output on the line 980.

The keypad lock interlock circuit 966 can be reset using the error reset button 974, the error reset button 974 emitting a signal "error reset button" on the line 970. When the interlock circuit 966 is reset, the keypad 128 is unlocked and the error lamp 977 is switched off Re-enter column characters using the correct data key 132 or space key 134. Assuming the mistake was made on the first re-keying, a comparison is made by comparison circuit 952 so that there is a signal on line 956 but none on line 960 which acts on AND circuit 962.
Assuming, however, that also with the second

ίο If another discrepancy is present when the first column is re-keyed, the inverter circuit 968 carries a signal on the line 960. The AND circuit 962 is then active as before to generate a signal "check not equal" on the line 964 for setting the keypad Output lock lock 966 , with the same results on keypad 128 and error lamp 977. The "check not equal" signal on line 964 also affects error counter 978 and the error counter then gives a signal on line 982 but not at this time on line 980 .

If, on the third re-keying of the information in column 1 from the original document by the operator, a noncomparison is still performed by the comparison circuit 952 , the "check not equal" signal will appear on the line 964 to the interlock circuit 966 with the same consequences as above set as described. The third "check not equal" signal on line 962 has the effect of advancing counter 978 to its third step position. At this point in time, the counter 978 provides an output on both lines 980 and 982 . The AND circuit 984 is then satisfied because its two inputs are satisfied and it provides a signal on the line 972 . This signal resets the keypad interlock lock 966 and continues to set the third attempt error lock 986. The lock 986 provides an output on line 988 and the AND circuit 990 is then satisfied at bit time C of the drawer P 3 so as to write an error flag in the memory at bit position C of the P 3 character of column 1 of the data circulating through the delay line 366. The AND circuit 990 emits the signal “disc defect marking” on the line 524 . which is supplied to the OR circuit 514 for this purpose

Before the test operation, the AND circuit 994 is operative to ensure that all bit positions C of the character P 3 of the circulating through the delay line 366 data is empty in all columns, so that the error flag are both in the position of the column 1 as well as in Circular information in the other columns can be entered. It should be noted that the AND circuit 994 has an input from the lines 424 and 554 with the time signals "P3" and "Bit time Cu" . Therefore, if the write-to-read tag interlock circuit 848 is set, the AND circuit 994 and those on it are indicated The closed inverter circuit 996 does not have the "Erase markings" signal on the line 510, because the uter "conditions" are responsible for making the WSj® circuit 504 active, so do that! JF

in turn running data from the tion 366 through them. AND gate 984 sees one of line 972 on the third WieöeRäsS and has the effect of the IffiSfeea »» «« *

Keypad lock interlock 966. Therefore, under these conditions, keypad control 434 unlocks keypad 128. The "Do not check keypad lock" signal on line 480 appears under these conditions and this signal acts on AND circuit s 476 together with the "test switch" signal line 481 and the "keypad ready" signal on line 418 to energize column display controller 479 via OR circuit 478 , thereby causing column indicator 486 to be updated so that digit 2 appears on the column indicator. The subsequent actuation of one of the data keys 32 or the space key 134 has the effect that a comparison takes place with regard to the information in column 2.

The comparison operation with regard to the data of column 2 and the subsequent columns circulating through the delay line is carried out in the same way as the comparison operation was carried out between the data of column 1 circulating through the delay line and that in the input register 372 by the first actuation of a data key 132 was intended. The comparison operations may have been performed on the entire record. As described above, the K to P transfer interlock circuit 466 has been set in conjunction with initial data entry prior to punching to generate the "K to P transfer interlock" signal on line 46P . The AND switch 1000 is the signal “K to P transmission interlock” on line 468, the signal “test switch” on line 481, the signal “A REG A” on line 730. The signal from the / 4 flip-flop of the / 4 register 368 is derived, and the time signals "P3" and "Bit time 4 and clock ß" are fed to lines 424 and 448. AND circuit 1000 now looks for any error flags in memory during the K to P transfer cycle. As described above, the error flags appear in the bit position C of the character P3 in those of the 96 columns of the data circulating through the delay line 366. for which bugs have been discovered. These errors are present in the / 4 flip-flop of 4 register 368 at time P3, bit time 4 and clock B. so that AND circuit 1000 is successful in this way in finding any error flags in the circulating data is. When AND circuit 1000 is satisfied, it indicates that the card under test contains at least one fault and possibly others. The AND circuit 1000 is connected to a defective card latch circuit 998 on the setting side. If a card with such an error occurs, the interlocking circuit 998 is set and interrupts the Signa! from interlock circuit 998 on line 1002. The primary purpose of bad card interlock 998 in setting is to indicate that that particular card being tested is a bad card and should not be scorched.

Under the assumption; that no errors were found in the card to be tested, the AND circuit 1000 is not satisfied during any time of the test of the recording card 100. Under these conditions , the Fehlkarlen interlock circuit 998 remains in its non-set state. Under this condition, a continuous signal is carried on line 1002 . Therefore, when the "test switch" signal is present on line 481, AND circuit 1004 is fulfilled in all inputs, namely at the time for group 20 during the K to P transfer operation. The “test switch” signal, the time signal “column 20” and the “K to P transmission lock” signal are fed as inputs to the AND circuit 1004 via line means 481 or 1008 or 468 . Therefore, after the complete card 100 has been tested, the notch lock 1006 is set and this provides a signal on its output line 1010 , which is connected to the test notch magnet 246 . The notch punch 242 is driven through the card 100 in this way in order to notch the card and to make a visible mark on the card that the card has been checked in every detail and that no errors have been found. The notch lock 1006 is reset at the next "column 96" time which is signaled over line 464 to the lock circuit 1006. The purpose of the "Column 20" and "Column 96" signals, which are fed to AND circuit 1004 and notch lock 1006 , is to generate a pulse that is applied to notch magnet 246 for four milliseconds (from column 20 to Column 96) so that a pulse of sufficient duration acts on the test notch magnet 246 to cause the notch punch 242 to make a full cut through the card 100 and return to its original position.

In the event of error conditions in which the defective card interlock 998 is set, the signal from this interlock circuit is not carried on line 1002. Therefore, AND circuit 1004 and latch circuit 1006 cannot operate to energize magnet 246. The particular card under test 100 remains unnotched under these conditions, indicating that a validation of the card has not been successfully performed.

During the K to P transfer operation, the "AC to P transfer lock" signal is applied to the reset side of the second step lock " 1012 on line 468 . The latch circuit 1012 is thereby reset. The purpose of this is to interrupt the signal on line 1018 and de-energize magnet 274 so that the card continues to advance into slot 166 through the card transport device. When a notched card has been advanced to slot 166 in this manner, it will be determined that the card has been validated and passed the test without fail, while if the card is not notched, it is defective and must be replaced.

With the aid of the reading station described and designed according to the invention with testing device, it is in advantageously possible to check the data entered and punched on a card and the card with the help of the test notch so that they can be used by every operator who will later use this card indicates that the correct data is recorded on the card.

14BJaJt drawings 609686/178

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Claims (4)

Patent claims: 1. Reading device with test device for data of a punched card-shaped recording medium, at which the perforations are arranged in columns in different parallel decks, with a keypad for entering comparison data, a comparison device for the read and keyed characters as well as a test notch, which is generated by the comparison device in the event of a match of all read and keyed characters can be actuated, characterized in that the characters punched out in the mutually parallel decks (1 to 3) by the reading station (158) in columns for all decks essentially, time-division multiplexed at the same time, that one memory (366) is provided for receiving the read characters that an input register (372) is provided is, in which the keypad (128) by successive actuation of data keys (132, 134) entered data can be stored, and that the comparison device (952) the stored, compares associated characters. 2. Reading device with testing device according to claim 1, characterized in that the reading station (158) time-division multiplexed columns at substantially the same time that the Reading station (158) is connected to the memory (366) in such a way that the data from the various Decks read characters entered in different spaced areas of the memory (366) so that after completion of the reading process all characters of the first deck (102) are in front the characters of the subsequent decks (104, 106) are stored in the memory (366), and that the Comparison device (952) Characters generated by successive actuation of the data keys (132, 134) occur in the input register (372), with successively occurring ones in memory (366) compares circulating characters. 3. Reading device m't test device according to claim 2, characterized in that in the reading station (158) for each hole position (1, 2, 4, 8, A, B) of a deck (102,104,106) a phototransistor (234i to 234i «) it is provided that these are arranged in a line, corresponding to the hole positions lying in a line of several columns of different decks (102, 104, 106) and that a lamp (198) is provided on the other side of the card (100). 4. Reading device with testing device according to one of the preceding claims, characterized in that the comparison between a keyed in character and one of the data card (100) read and ^; The characters contained in the memory (366) can be repeated several times by re-entering the comparison character if they do not match.