DE2063525C2 - Decoder for a multiplex signal mixture that contains a pilot tone - Google Patents

Description

Transformers) used these and other inductive elements matched in the above mentioned Filter circuits are required are relatively bulky and expensive. They make manufacture difficult the receiver, as they usually have to be set and adjusted, which requires expensive electronic test equipment. Using of several inductive elements, these must be spatially arranged in such a way that no undesired alternation or coupling between them can take place.

Furthermore, the matched band filter circuits, which are normally used for separating the pilot signal and the restoration de? 38 kHz subcarrier are used, relatively high O values, so that they are quite phase sensitive. That is, one A relatively small shift in the resonance frequency of the tuned circuit has a relatively large change in the phase response of the filter for Signals of the sub-tuning frequency (19 kHz or 38 kHz}. In the case of an FM stereo decoder becomes one through such a change in phase angle Filters degrades the separation of the sterephone left and right signals (i.e., a Crosstalk between the two signal channels). Shifts of the type mentioned occur frequently due to changes in inductive or capacitive values; as a result of fluctuations in operating temperature or signs of aging.

Relatively low level signals of the type mentioned above, such as occur in FM stereo decoding circuits, can be used with advantage of monolithic integrated circuit dies (i.e. solid-state circuits in which a plurality of of active semiconductor components such as transistors and diodes as well as passive circuit elements such as Capacitors and resistors and their interconnections are attached to a common substrate made of semiconductor material). Such integrated circuits are the conventional circuit ίο processing arrangements with discrete components in terms of size, weight and reliability and in some cases also economical Considerations.

In the construction of integrated circuits, compared to circuits with multiple components, a number of economic aspects must be taken into account. For example, while in the case of non-integrated circuits the aim is to get by with as few active components as possible, since these are relatively expensive as discrete components, in the case of integrated circuits it is not so important to save on active components, since their production in integrated form is less expensive is. In the case of integrated circuits, on the other hand, efforts are made to provide as many circuit functions as possible on the circuit board and to get by with as few circuit elements as possible outside the circuit board. Integrated circuits are not so attractive when coils and / or transformers have to be provided in connection with the circuit board, since such inductive circuit elements not only have a detrimental effect on cost, size, weight and reliability, but they also make them a burden interconnection further comprises a plurality of relatively few available otier ^a, nschlußkontakte of the circuit chip (z. B. sixteen in a typical Execution), Furthermore, because of the relatively small dimensions of the circuit board (z, B, in of the order of 2.5 x 2.5 mm or smaller) and the resulting tight spacing between the supply lines for external circuit elements is desirable, the number of external supply lines for alternating current signals as low as possible to avoid unwanted coupling between the different Avoid sharing the circuit board as much as possible. Especially in the case of an integrated FM stereo decoder circuit, it is desirable that the 19 kHz and 38 kHz signals are processed exclusively within the circuit die, so that a Coupling of out-of-phase signals to the 38 kHz recovery stages is prevented, as above mentioned, phase errors in the 38 kHz subcarrier cause crosstalk between the left and right channels Have consequence.

It is therefore desirable to use arrangements with active components i without inductive components for the frequency selection (band filtering) in an integrated circuit. Such a frequency selection can be made in such a way that a certain signal component is superimposed with a corresponding locally generated carrier signal, so that a differential frequency signal related to zero frequency is produced, which can then be filtered with the aid of simple RC filter circuits. A frequency selection in this way can advantageously be accomplished with integrated circuits with the aid of amplifiers which are designed as symmetrical or push-pull synchronous detectors.

The invention is therefore based on the object of providing a decoder for a multiplex signal mixture create that contains a pilot tone that has as few inductive circuit components and itself characterized by a simple structure.

This object is achieved by the invention characterized in claim 1

The decoder according to the invention contains very few inductive circuit components and is simple in structure, so that it can be manufactured inexpensively and hardly requires any adjustment work. The decoder according to the invention is also very well suited for implementation in the form of an integrated circuit. Of the Decoder according to the invention is particularly well suited for stereo broadcast receivers.

Developments and advantageous refinements of the decoder according to the invention are the subject matter of subclaims.

The only oscillator of the decoder for an FM stereo receiver is on a harmonic of the 19 kHz pilot signal tuned. The frequency divider circuit coupled to the oscillator is part of one automatic frequency and phase control circuit (AFPR circuit) for the oscillator and generates a Reference oscillation related in time to the oscillator output oscillation with a subharmonic (nominally 19 kHz) of the frequency of the oscillator output oscillation. The frequency divider is free from inductive Attitude elements. The AFPR circuit also contains the phase detector, which comes from the Bezups oscillation and the composite signal which is demodulated in the receiver and which contains the received pilot signal DC voltage corresponding to the phase difference between the reference oscillation and the pilot signal generated. A control arrangement coupled to the phase detector changes according to the

DC voltage indicating the phase and / or frequency of the oscillator in such a phase error Meaning that the oscillator output oscillation has the predetermined frequency and the predetermined temporal Relationship to the received pilot signal maintains.

An arrangement is also coupled to the oscillator which generates a 38 kHz subcarrier in a predetermined time relationship to the 19 kHz pilot signal for the demodulation of the stereophonic difference signal components (LR) . The first synchronous detector, to which the 38 kHz subcarrier and the composite signal including the received differential signal sidebands are fed, generates two output signals which represent audio difference signal components (L - R) and - ( L - R) in antiphase. The opposite-phase tone difference signal components and the demodulated signal mixture including the tone sum signal component (L + R) are fed to a matrix circuit, the separate left "" - P ^ Mr-

Sound signals (L) or (R) generated for sound reproduction. For example, these signals can be further amplified and then fed to loudspeakers.

In FM stereo receivers it is also desirable that the listener be informed when stereophonic broadcasts are being broadcast be received. Usually a lamp is used for this, which lights up when in the received signal a pilot signal of adequate amplitude and duration is present. For this one can use the oscillator coupled arrangement may be provided, which is a further, opposite to that supplied to the AFPR detector Reference oscillation generated 19 kHz oscillation phase-shifted by 90 °. Preferably this is Arrangement free of inductive sound elements. A second synchronous detector is with the 90 ° phase-shifted 19 kHz oscillation and with the signal mixture containing the received pilot signal fed and generates an output signal in the permanent presence of the pilot signal that a display device is fed, which then visually indicates the reception of stereo broadcasts.

As is well known, in order to produce an acceptable stereo sound signal, the signal-to-noise ratio (the Signal-to-noise ratio) of the received FM radio signal must be greater than it is for monophonic transmissions necessary is. From the listener's point of view, it can therefore be more advantageous under certain reception conditions when the received stereo signals are reproduced in monophonic or monaural.

In a further development of the invention, an arrangement is therefore provided which the signal-to-noise ratio of the Measured sigwale mixture received and automatically switches to monophonic reception when the signal for an acceptable stereophonic reproduction is too noisy. Preferably the oscillator is the The decoder is set up so that it works with a frequency that is an even multiple of the received pilot signal (19 kHz) is where the even multiple is chosen so that the Oscillator frequency is above the frequency band of any signal component of the composite signal (e.g. at the sixth or twelfth harmonic of the pilot signal). A third synchronous detector is with one reference oscillation derived from the oscillator output and lying above the signal frequency band as well as fed with the demodulated composite signal including any interference components A relatively low-frequency output signal of the detector, which represents the interference components with compared to a predetermined acceptable interference threshold. In the presence of interfering components above the interference threshold is a stereo indicator and / or an automatic stereo switching arrangement a stereo lock signal is fed in so that the receiver can switch to mono mode if the The processed composite signal is too noisy for an acceptable stereo reproduction.

In the invention, a single oscillator is provided which operates at a frequency which is an even harmonic of the pilot signal and of the stereo differential subcarrier and is above the highest signal frequency component of the composite signal. A number of inductance-free frequency divider arrangements are coupled to the oscillator and supply the phase detector and three synchronous detectors with four harmonically related reference signals. The detectors are also ~ ·; '•••• »i Wom ^ rliiliortpn dcrnalapmi« rh iresneist and set up SO that the oscillator is regulated to a predetermined time relationship (phase relationship) to the pilot signal component of the signal mixture, that the presence of the pilot signal component is indicated, that the stereophonic difference signal component of the signal mixture is demodulated and that the presence of interference components lying above the signal frequency band in the composite signal is indicated wi J.

The invention is explained in detail below with reference to the drawings

I shows the block diagram of an FM radio receiver with FM stereo deco according to an embodiment of the invention;

F i g. 2 is a block diagram which illustrates how several bistable counter units are connected together can be to the in the arrangement according to F i g. 1 required switching oscillations for the synchronous demodulation to create:

3 shows a series of signal curves in the arrangement according to FIG. 2 generated switching rockers;

F i g. 4 the circuit diagram of an integrated amplifier for the stereo signal mixture in the arrangement of Figure 1;

F i g. 5 shows the circuit diagram of a voltage-controlled oscillator arrangement that can be built up in an integrated form with AFPR push-pull detector for the arrangement according to FIG. 1;

F i g. 6 the circuit diagram of an integrated push-pull synchronous detector for the stereophonic Difference signal with automatic stereo switch arrangement and matrix amplifiers for extraction the left and right tone signals for the arrangement according to FIG. 1;

F i g. 7 the circuit diagram of an integrated push-pull synchronous detector for over-band Interfering components with the associated voltage supply device for the arrangement according to FIG. 1; and

Fig. 8 the circuit diagram of an integrated form Buildable push-pull synchronous detector for the presence of the pilot signal with associated stereo reception indicator and switching device for the arrangement according to FIG. 1.

F i g. 1 shows the simplified block diagram of an FM radio receiver for the reception of monophonic or stereophonic broadcasts. Numerous signal paths are shown as a single line which starts from a block and in front of the entrance

is divided into two lines in another block. This indicates that the signals running over the lines in question are push-pull signals (ie two signals which are phase shifted by 180 ° and which are otherwise largely identical). The radio receiver has the usual FM receiving section 20 for the selective reception, amplification and demo ^ ilation of FM radio signals. The FM receiving section 20 supplies an input T \ of an FM stereo decoder circuit 22 with either an audio-frequency composite signal (L + R) when receiving mono broadcasts or, when receiving stereo broadcasts, with a stereo signal mixture consisting of a composite signal (L + R ), a control or pilot signal (19 kHz) and a differential signal (L - R) modulated onto a suppressed subcarrier. In addition, FM background music signals (SCA) can be used at the Ti input in both cases.

For the sake of simplicity, the signal supplied to the input Ti is always referred to below as a “composite signal”. In the stereo decoder 22, all of the circuit elements and units within the dashed block are preferably built in integrated form on a single semiconductor substrate. Terminal contacts Tt to 7 "i6 are provided on the integrated circuit board for connection to external circuit elements, signal sources or other circuits.

The demodulated composite signal supplied to the connection contact Ti of the decoder 22 is fed to a stereo amplifier 24 which linearly amplifies signals in the range from approximately 10 Hz to 150 kHz, so that it generates two essentially identical but 180 ° phase-shifted (i.e. push-pull ) provides amplified mixed signals which are fed directly to various circuit elements in the stereo decoder 22. The stereo decoder 22 also includes a voltage controlled oscillator 26 which oscillates at a frequency of 228 kHz, an even harmonic of both the 19 kHz pilot signal and the 38 kHz stereo subcarrier. The operating frequency of the oscillator 26 is mainly determined by a parallel resonance circuit with a coil 82 and a capacitor 80, which are arranged outside the circuit board of the decoder 22 and connected to this via the connection contacts T ₂ and T ₃ . The 228 kHz output oscillation of the oscillator 26 is, as shown in FIG. 5 will be explained later, formed into a substantially symmetrical rectangular shape. The output oscillation of the oscillator 26 is kept in a predetermined temporal relationship to the received 19 kHz pilot signal with the aid of an automatic frequency and phase control circuit (AFPR circuit). The AFPR circuit contains a frequency divider arrangement coupled to the output of the oscillator 26, which generates an oscillation with a frequency (nominally 19 kHz) which is an integer sub-multiple (Vu) of the oscillator oscillation frequency and which is in a predetermined time relationship to the oscillator output oscillation The desired frequency division and Time relationship are established with the help of a first frequency divider 28, which divides the output oscillation of the oscillator 26 by 2 (to nominally 114 kHz), a second frequency divider 30, which divides the output oscillation of the frequency divider 28 by 3 (to nominally 38 kHz) and one to the Frequency divider 30 coupled phase selector 32, which feeds a third frequency divider 34 with a predetermined of two opposite phases of the oscillation of nominally 38 kHz. The frequency divider 34 divides the output oscillation of the phase selector 32 by two and feeds an AFPR push-pull phase detector 36 in push-pull with an oscillation of nominally 19 kHz. The phase detector 36 is also supplied with the push-pull composite signal including the 19 kHz pilot signal from the stereo amplifier 24.

A differential DC voltage is generated on a filter capacitor 38 arranged outside the circuit board 22 and coupled to the phase detector 36 via connection contacts U and ti , which is the phase difference between the received pilot signal and the nominal 19 kHz oscillation from the output of the oscillator 26 reproduces. This differential DC voltage is coupled symmetrically or in push-pull by the capacitor 38 to the Ος / ίΙΙβίηΓ 26 in order to correct its oscillation frequency and phase accordingly. The AFPR circuit holds the 19 kHz output oscillation of the frequency divider 34 essentially in a special 90 ° phase relationship to the received 19 kHz pilot signal.

The frequency divider 30 generates the required 38 kHz subcarrier for demodulating the difference tone signal (LR ) from the received sidebands of the suppressed 38 kHz subcarrier. These sidebands, together with the rest of the signal mixture at the output of the stereo amplifier 24, are fed in push-pull to a subcarrier push-pull synchronous detector 40 "first synchronous detector". The locally generated 38 kHz subcarrier originating from the frequency divider, which is kept in the correct phase and at the correct frequency by the AFPR circuit, is fed to the subcarrier detector 40 in push-pull from the output of the frequency divider 30. The detector 40, as will be explained, is designed as a "double symmetrical" synchronous detector (synchronous ring demodulator) and therefore generates push-pull output signals including ( LR) and - (LR), the desired difference tone signals. The positive and negative difference tone signals are fed to matrix amplifiers 42 and 44, respectively, which also receive the summed tone signal (L + R) and the remaining part of the composite signal from amplifier 24.

The matrix amplifiers 44 and 42 generate uncompensated left and right tone signals (L) and (R) _{at their outputs T] 0 and Tu, respectively.} These uncompensated

so left and right tone signals are fed to conventional equalization circuits 46 and 48 and the resulting Compensated signals are amplified in sound amplifiers 50 and 52 loudspeakers 54 and 56, respectively The equalization networks 46, 48 also feed in those from the push-pull demodulation process residual ultrasonic signal and the pilot signal and modulation components of the 38 kHz subcarrier, which are present in the composite signal at the output of the stereo amplifier 24, removed

It is also ensured that the stereo decoder 22 indicates when the FM receiving part 20 supplied signals stereo transmissions are available and for this purpose the presence of the pilot signal, which is only transmitted with stereophonic, but not with monophonic broadcasts, perceived. The detector for stereophonic transmissions includes a fourth frequency divider 58, the a second output of the phase selector 32 coupled

is pelt at which a 38 kHz oscillation occurs which is 180-phase-shifted with respect to the oscillation fed to the frequency divider 34. This second output oscillation of the phase selector 32 is divided by 2 in the frequency divider 58, so that a 19 kHz oscillation is obtained which is a predetermined phase position of approximately 90 ° to the output oscillation of the frequency divider 34 ha 'and essentially in phase with the received pilot signal. The pilot signal, together with the remaining part of the signal mixture from the stereo amplifier 24, is coupled in push-pull to a pilot signal push-pull synchronous detector 60 "second synchronous detector". Furthermore, the output signal of the frequency divider 58 is fed to the detector 60 in push-pull mode, so that differential DC voltages are generated at capacitors 62a, 626 which are coupled between connection contacts 7} or T »and ground.

The differential DC voltage between the terminal contacts Τη and Te is amplified in the detector 60, so that a DC voltage related to ground potential is provided at the output terminal Tg , which DC voltage indicates the presence of the pilot signal in the received signal. A stereo indicator 64 connected to terminal contact 79, which typically consists of an incandescent lamp and a switch transistor, provides a visual indication of stereo reception.

Furthermore, an arrangement is connected to the subcarrier detector 40, which the subcarrier demodulation stages locks or switches off when due to the prolonged absence of a pilot signal of certain Minimum amplitude indicates that a non-stereophonic (monophonic) broadcast is being received, or when the signal to noise ratio (the signal to noise ratio) of the received signal is too bad to be satisfactory Stereo playback is. The locking arrangement contains an OR gate 66, which has an input on the connection contact ig for the pilot signal detector 60 and with a second input to an interference push-pull synchronous detector 68, ("third synchronous detector"), the task of which will be explained later, is connected.

Upon receipt of a corresponding signal from the output of the pilot signal detector 60, the OR gate 66 provides an output signal to a stereo blocking circuit 70, which in turn is coupled to the subcarrier detector 40, so that the detector 40 is blocked if either no acceptable pilot signal is present or the demodulated composite signal has an insufficient signal-to-noise ratio for acceptable stereo reproduction. When the subcarrier detector 40 is disabled, only monophonic information (L + R) is fed to the matrix amplifiers 42 and 44. As in connection with F i g. 7, the stereo indicator 64 is connected to the output of the OR gate 66 instead of directly to the detector 60 when the stereo reproduction (instead of the stereo reception, as explained above) is to be displayed. The stereo blocking circuit 70 includes a delay element with a capacitor 72 coupled between the terminal contact Tb and ground and a resistor (not shown) which z. B. can be provided on the integrated circuit chip 22. The resistor and the capacitor 72 form such a large time constant that the constant presence of a pilot signal display at the output of the detector 60 for a longer period of time (e.g. one second) is necessary before the subcarrier detector 40 can be activated.

The interference detector 68 is connected to the push-pull composite signal from the output of the stereo amplifier 24 as well as with the push-pull square wave with the fundamental frequency of 114 kHz from the frequency divider 28 fed. A connection contact connected between the connection contact connected to the output of the disturbance detector 68 71 «and ground-coupled capacitor 76 is generated

to a voltage that shows interfering components in the composite signal whose frequencies are higher than the highest Useful signal component. It has been found to be useful for those above the signal frequency band to detect lying interferences with a frequency in the vicinity of 100 kHz. The special frequency of IHkHz is here for simplicity in view chosen so that it is derived from the voltage controlled oscillator 26, whose Arbeitsfrequettz is limited to one harmonic of both the 19 kHz pilot signal and the 38 kHz subcarrier. the perceived disturbances are in a suitable arrangement (shown in Fig. 7) in the disturbance detector 68 compared to an allowable signal-to-noise ratio reference level, and if the perceived signal-to-noise ratio is below the permissible threshold value or reference level, the OR gate 66 is a blocking signal as already mentioned, the stereo indicator 64 can be connected to the output of the OR gate 66 connected so that the stereo indicator lamp goes out whenever the stereo lockout circuit 70 blocks the subcarrier detector 40

Like F i g. 1 shows, further external connection contacts are provided on the decoder circuit board 22. For example, a connection contact Tt is connected to ground and a connection contact Tn is connected to an external operating voltage supply B + . The connection contacts Tu and Tf are connected via numerous line connections (not shown) within the circuit board 22 to various circuit elements within the individual blocks. The corresponding connections are shown in the other figures.

Outer capacitors 78a and 78fc are coupled between ground and the connection contacts T \% and 7 "i6 for the stereo amplifier 24. As will be explained with reference to FIG. 4, the capacitors 78a and 786 are used for the signal derivation in the bias circuits of the stereo amplifier 24.

F i g. 2 shows several counters in block form

so connecting logic circuits. Each counter can be designed as it is in DE-PS 20 65 294 The following is based on the assumption that positive logic is used for the sake of simplicity in Fig. 2 shown as logic elements positive logic AND elements. The AND connection leaves can be achieved particularly easily with a counter of the type mentioned by adding a circuit arrangement of the counter with the complement of a certain signal

In Fig. 2 (see also FIG. 3), the voltage-controlled 228 kHz oscillator 26 supplies an essentially sinusoidal continuous oscillation to a limiter circuit 310, which generates a square-wave continuous oscillation at its output with a fundamental frequency of 228 kHz (signal profile A FIG. 3) This 228 kHz square wave A is fed to the trigger input (T) of a first frequency-dividing bistable toggle or flip-flop circuit 312 which has its outputs ("0",

U 12

»1«) complementary 114 kHz square waves in signal D together. Through this synchronous buzz

(Signal curves B, B, Fig. 3) with positive and negative hung, which is constantly maintained because the flip-flops 318 and

Directed level transitions, which are triggered in parallel with the positive 322 by the signal A, is

directional level transitions in signal A collapse - an exact synchronous demodulation of the stereophonic

len. is generated. The 228 kHz square wave output 5 see difference signal information ensured so that

of the limiter 310 is also an inverter stage 314, crosstalk is largely prevented if on

supplied, which at its output_a 228 kHz right hand of FIG. 6 will be explained later. A fifth

corner oscillation (signal curve A, Fig. 3), which the flip-flop 328 generates complementary rectangular shapes

Complement of the output oscillation of the output oscillation (signal curves F, F) with a

represents oscillation of the limiter 310 provides. The io basic frequency of 19 kHz and a phase shift

That is, the individual negative level transitions exercise of essentially 90 ° with respect to the signals

in signal A essentially coincide with the E, E. The triggering of the flip-flop 328 occurs as a result,

positively directed level transitions in signal A that one of the 38 kHz output oscillations of the

together, and vice versa. Flip-flops 318 (signal D), one of the 19 kHz output

A second flip-flop 316, the synchronous state 15 oscillations of the flip-flop 322 (signal E) and one of the

with only certain of the positively directed level above 19 kHz output oscillations of the flip-flop 328 (Si

ganges in the signal Ä changes, delivers gnal F) to an AND gate 330 at its output. Further

("1") an asymmetrical pulse signal (signal curve C, are the other output oscillation of flip-flop 318

F i g. 3). The positive and negative going level over- (signal D), the other output oscillation of the

courses in signal C essentially fall with 20 Fiipfiops 322 (Signai Ejunu the other Auigäfigssehwin-

certain positive transitions in the signal Ä generation of the flip-flop 328 (signal F) to another

together. The manner in which the signal C generates AND gate 332 is supplied. The output vibrations

will be explained later. the AND gates 330, 332 are in an OR

A third flip-flop 318, the complementary rectangular element 334 combined, which with its output at the

output oscillations with a base frequency of 25 trigger input (T) of flip-flop 328 is switched on.

38 kHz is generated at its input (T) at during each of the flip-flops 312,316,318 and 322 through

simultaneous occurrence of a positively directed one of the 228 kHz signals A, Ä is triggered,

Transition in signal A and a "high" level ("1"), the flip-flop 328 only receives trigger information from

triggered in signal C. Triggering flip-flop 318 other of the associated flip-flops. The signals F Fs are

takes place in that the 228 kK ^ output oscillation 30 is therefore somewhat compared to the basic clock signals A, Ä

of the limiter 310 (signal A) and the asymmetrical delayed. This delay causes the pilot

Output oscillation of flip-flop 316 (signal C) to signal detector 60, which processes signals F, F , in

an AND gate 320 are coupled. The output does not affect its basic mode of operation,

signal of AND gate 320 is triggered except that it has a slightly reduced output voltage

output (T) of flip-flop 318 is coupled so that it supplies to 35. On the other hand, the delay becomes more advantageous

its outputs ("0", "1" ^ complementary rectangular shape for the work of a pulse stretching circuit

oscillations (signals D, D) with a basic frequency ^ exploited, as shown in FIG. 7 will be explained

generated by 38 kHz. The output oscillations D, D will.

of the flip-flop 318 can be the first synchronous detector. It will now be explained how the asymmetrical

40 in Fig. 1 are fed. The combination of the 40 output oscillation (signal C) of flip-flop 316

Flip-flops 312, 316 and 318 are generated by frequency dividers 28. The triggering of the flip-flop 316 occurs

and 30 in FIG. 1 and is used to obtain the 228 kHz output oscillation of the

228 kHz output oscillation of the limiter 310 Inverter stage 314 (signal Ä) the 114 kHz output

(Signal A) to be divided by 6. The individual level overshoots of flip-flop 312 (signal B) i'.d die

outputs in signals D and D occur synchronously 45 38 kHz output oscillation of flip-flop 318 (signal

are fed to an AND gate 336 with a positive level transition in D). Further

228 kHz signal A. the 228 kHz output oscillations of the inverters

A fourth flip-flop 322 generates complementary stage 314 (signal A), the other 114 kHz output

Square wave output oscillations (waveforms E, E oscillation of the flip-flop 312 (signal B) and the other

with a base frequency of 19 kHz. Triggering the 50 38 kHz output oscillation of flip-flop 318 (signal

Flip-flops 322 takes place in that the 228 kHz output D) is fed to an AND-Güed 338

The output oscillation of the limiter 310 (signal A) is the 228 kHz output oscillation of the inverter stage 314

asymmetrical output oscillation of flip-flop 316 (signal Ä), the first-mentioned 38 kHz output oscillation

(Signal C) and a ά <* τ 38 kHz output oscillation of flip-flop 318 (signal D) and the output

of the flip-flop 318 (signal D) an AND gate 324 55 oscillation of the flip-flop 316 (signal C) a

are fed. The output signal of the AND gate 340 is fed to the output variables of the

of the 324 reaches the trigger input (T) of the flip-flop AND gates 336, 338, 340 are in an OR

322, which combines the for the operation of the phase detector 36 in member 342 with its output to the

Fig. 1 required 19 kHz oscillations generates trigger input (T) of flip-flop 316 is switched on

The individual level transitions in the signals E, E ω of all AND gates 336, 338, 340 of the 228 kHz

contact jweils fed in timed relation to a positive trigger signal Ä and since the flip-flop 316

directional level transition in signal A , as it is with (as well as the other flip-flops shown) its state,

the 38 kHz oscillations D, D is the case, if at all, only when a positive is fed in

It is clear that the level transitions in the output oscillation of the FI-directed trigger pulse changes

pflops 322 therefore essentially fall in time with 65 flip-flops 216 its state when certain ones occur

Level transitions in the exit signa! the Fiipfiops 318 changes the positive-going transitions in the signal Ä

together. In contrast, the positive level transitions change the other flip-flops 312,318,322,328

Signal F, with negative level transitions, have their state essentially positive when they occur

directed transitions in signal A, which are shifted by half a period of the 228 kHz oscillation compared to the positive transitions in signal Λ. Another feature of the output oscillation of flip-flop 316 is that the "high"("1") s and the "low"("0") parts of the signal have unequal durations (ie, signal C is asymmetrical). Such an asymmetrical waveform is particularly advantageous for generating the 38 kHz oscillations D, D , for which the 228 kHz oscillation A must be divided by 6 (ie a number that is not an integer power of 2).

In the frequency divider arrangement described above, the oscillator 26 operates at a frequency which an integral harmonic of the 38 kHz subcarrier frequency and an integral harmonic of the 19 kHz pilot frequency is This choice of the operating frequency of the oscillator 26 facilitates the generation (or Time setting) of the individual leading and trailing edges of the 38 kHz switching signal from a single Polarity of the Oszuiaior-Takiirn pulse output oscillation. The central axis passages of the 38 kHz switching oscillation are precisely controlled in this way, see above that there is a good separation of the demodulated stereophonically linked sound signals, as before will become apparent.

Other timing relationships are possible; however, the system described above has the advantage of that the logic and frequency divider circuits are particularly simple.

One can also generate the required sets of complementary square waves using other linking functions than in the arrangement according to FIG. 2 generate. For example, to generate the output signal of flip-flop 316, input signals A, C and B can be fed to AND element 340 instead of as in FIG. 2 feed the input signals Ä, C and D. In any case, the same s'ingale shapes are obtained as in Fig. 3. Other modifications are also possible.

Each of the flip-flops can have one or the other of the two logic states ("1" or "0") when the system is initially switched on. In order to obtain the desired relative time relationships between the output variables of the various flip-flops, the logic circuits connected upstream of these must be able to take these two possibilities into account. For example, the flip-flop 316 can initially have one of the two states (“1” or “0”) when a trigger pulse is supplied via the OR gate 342. The AND gate 340 ensures that the positive and negative-going transitions in the signal Q as in FIG. 3, are not transported or rearranged, but occur in the relationship shown with the other signal curves. The logic circuits for the remaining flip-flops are also set up in such a way that the signal curves shown in FIG. 3 result.

The manner in which the rectangular oscillations B, B. D, D, E, E and F, F are used in the decoder arrangement 22 is illustrated in FIG. 5, 6, 7 and 8 will be explained.

FIG. 4 shows the circuit diagram of a stereo amplifier, corresponding to the amplifier 24 in FIG. 1, for the Generation of balanced push-pull stereo signals. The stereo amplifier according to Fig. 4 is suitable particularly good for the construction in integrated form on the circuit board 22 according to FIG. 1.

In Fig. 4, the composite signal supplied by the FM receiver is coupled to a symmetrical or push-pull differential amplifier circuit via a capacitor 501 arranged outside of the circuit board 22 and the connection contact 71 of the circuit board 22.The two halves of the push-pull amplifier circuit each form an emitter follower stage with a shunt regulator in the emitter load impedance. The eir.e half of the differential amplifier circuit contains an emitter-follower transistor 503 with signal-variable emitter load impedance, which contains the collector-emitter path of a shunt regulating transistor 505, the emitter of which is connected to ground via a resistor 507. The collector of transistor 505 is directly connected to the emitter of the emitter follower transistor 503 and connected to one end of an output load resistor 509. The collector of the transistor 503 is connected to an operating voltage source (B + , ζ. B. + 8.5 volts) via a resistor 511.

The input signal is mixed from the connection contact Ti is coupled to the base of the emitter follower transistor 503 via an emitter follower transistor 513 designed in a Darlington configuration When there are changes in the input signal mixture, transistor 503 is fed back from the collector of the Emittenolger transistor 503 to the base of the variable impedance transistor 505 is kept substantially constant. The feedback circuit includes an emitter follower transistor 515 and a DC voltage transmission network with a current source transistor 517, which is connected to its emitter via a Resistor 519 is connected to ground and with its collector via a resistor 521 to the emitter of the transistor 515 is connected. The collector of the current source transistor 517 is connected to the base of the Transistor 505 via a cascade of emitter follower transistors 523, 525 and 527, each with one to ground lying emitter load resistor 529, 531 or 533 coupled A resistor 535 is between the emitter of transistor 523 and the base of transistor 525 are coupled

The base of current source transistor 517 is biased via emitter follower transistors 537 and 539 with emitter load resistors 541 and 543, respectively of the circuit board 22 arranged capacitor 78a is derived, which is connected between the connection contact T _iS and ground (FIG. 1).

The circuit design described above ensures that the current source transistor 517 and the shunt regulating transistor 505 receive equal base bias voltages (DC voltages). In fact both transistors 505 and 517 get their base bias from the same source (the emitter de; Transistor 523) have essentially identical circuit elements. The bases of the transistors 50! and 517 can be viewed as directly connected to one another in terms of DC voltage. Dei Emitter working resistance 507 of the transistor .'505 is' twice as large as the emitter working resistance 51f of the transistor 517. However, the resistor 519 is aucr to a corresponding current source transistor 54i of the other half of the differential amplifier

15 16

closed and therefore receives twice the current conduction of the transistor 559 is increased, so that the

DC as resistor 507. The DC collector current of transistor 549 is essentially

voltage drops across the resistors 507 and 519 are remains constant, the current from the transistor 503 is

therefore the same, and the base-emitter DC voltages are fed to the transistor 559 via the resistor 509

of transistors 505 and 517 are essentially s The lowered collector current of transistor 505 and

same. Set the collector quiescent direct currents (when the increased collector current of transistor 559 is absent

the signal) of the transistors 505 and 517 are therefore the amplified input signal mixture

essentially the same if the output signal mixes are identical

Transistor training is, as it is obtained with one, that for example the base-emitter paths

integrated circuit is the case io one or more transistors, e.g. B. the transistors

The second half of the differential amplifier is equal to 561 and 563, in parallel with the base-emitter paths of the

designed like the first half, with the exception of transistors 505 and 559 are connected, so that

The fact that the base of the emitter follower transistor 549 is a current amplifier for coupling the output signals

with constant collector current does not send signals to e.g. detectors 36, 40, 60 and 68 in

fed, but on a substantially fixed 15 Fig. 1 result.

The stereo amplifier 24 supplies a linear signal-voltage divider with a resistor 551 and an amplification in the frequency range from 10 Hz to ίΛί) kHz Zener diode 553, which is connected between a voltage source and couples the amplified signals via the transistor ( B +) and ground as well as with their connection 561 and 563 to a number of impedance change points via a load or consumer element borrowed in a Darlington circuit,
put emitter follower transistor 555 to the base of the amplifier 24 when transistor 549 is coupled to enable rapid switching on. The basis for switching on the receiver is ensured by measuring transistor 513 in the above-described difference. Which is connected to the zener diode 553. 25 charging arrangement for capacitor 78a includes one

In the same way as for transistors 505, transistor 565, which has its collector connected to the

and 517 are also described here the collector rest operating voltage supply (B +), with its emission

the transistors 547 and 559 flow equal to one another via the connection contact 7 »to the capacitor

and are due to the differential circuit via the 78a and with its base to a switching signal source

Resistor 519 is connected every four collector quiescent currents (517,505, 30 The switching signal source switches the

547,559) are essentially the same. Furthermore, all transistors 565 are in when the receiver is switched on

Base biases at corresponding points - a conductive or low-resistance state and after

th in both amplifier halves essentially a predetermined time interval in a non-conducting

the same (e.g. the voltages at the bases of the or high-resistance state. The switching signal source

Transistors 517 and 547 as well as the voltages at 35 contains a transistor 567, which with its collector

Bases of transistors 503 and 549 the same). The series connection of two resistors 569 and

Therefore, amplifier 571 yields a good Gleichtaktunterdrük- to the operating voltage supply (+ B), with

pretensioning. Furthermore, due to its emitter, a resistor 573 is connected to ground

Difference circuit across the resistor 519 and with its base to, for example, the base of the

Base biases of multiple output transistors, 40 connected to transistor 517 is the collector of the

For example, transistors 561 and 563 all of transistor 567 is directly connected to the base of the transistor

same. In the idle state (signal-free state) flows connected to 565.

between the emitters of the transistors 503 and 549, the loading arrangement for the capacitor 786 includes resistor 509 coupled substantially no two additional transistors and an emitter Wider stream. That is, these emitters have substantially 45 stand (not shown) in the same manner as the same DC voltage at 2 V _B e below the transistors 565, 567 and the resistance 573 553 with the voltage at the Zener diode operating voltage supply B + are connected. the

In operation, the connection contact 7Ί over the base of the additional capacitor 501 supplied to the transistor 567 endeavors, Chen transistor is connected to the base of the transistor 547, the collector current of the transistors 503 and 549 50, while the emitter of the transistor 565 is differentially to modulate or change. However, due to the feedback from the _{closing contact 7J 6} , the collectors of the transistors 503 and 549 to the bases, the operation of the charging circuit for the termination of the transistors 505 and 559, the impedances of the sator 78a is described; the similar charging circuit transistors 505 and 559 in such a sense 55 for the capacitor 786 operates in the same way, changing the collector currents of the transistors when the main power supply (B +) of the 503 and 549 are kept essentially constant. When the receiver is switched on, the transistor 565 conducts, for example, the input signal mixture in essentially immediately, since its base is directly applied with the positive direction in one of the current line of the voltage B + . The transistor 567 increases the sense of the transistor 503, so it is at this point in time in the high impedance via the associated feedback the base of the state. Capacitor 78a very quickly becomes a less positive signal via transistor 505, so that it charges transistor 565 and the bases of the resistance of transistor 505 increases. At the same time transistors 537, 539, 517 and 567 receive their current conduction of the transistor 549 by the operating voltage. When transistor 567 conducts input signal (which begins at the emitter of transistor 549 65, the voltage at the base of the transistor drops across transistors 513, 503 and resistor 509 565 so that transistor 565 is fed against the blocked) lowers while being driven due to the state. If the capacitor 78a_ feedback in the second amplifier half has a predetermined quiescent target voltage, the |

Transistor 565 is blocked and remains in this state until the receiver is switched off and on again.

Pig.5 shows the circuit diagram of a controlled Oscillator that is particularly suitable for manufacture in an integrated form and for a working frequency of 228 kHz, as shown in FIG. 1 specified. The same circuit elements in FIG. 5 and 1 are denoted by the same reference numbers

The controlled oscillator 26, which can be constructed in accordance with DE-OS 20 48 369, essentially delivers square waves (signals A, A, F i g. 4) with a base frequency of 228 kHz and a predetermined phase relation to the 19 kHz pilot signal am Output of the stereo amplifier 24 for the clocking to the frequency divider circuits in FIG. 2.

The oscillator 26 contains an amplifier arrangement with a matched LC network in a feedback branch between the output and input of the amplifier. The amplifier, designed as a differential amplifier, contains emitter-coupled transistors 611 and 619 with a common emitter resistor 613, which is connected to ground. This common point is the base of a transistor 609 connected in Darlington circuit to transistor 611. The transistor 619 is also connected to a transistor 617 in a similar Darlington circuit. The collectors of transistors 609 and 611 are directly connected to the operating voltage supply (B + ) connected, ferries .; the collectors of the transistors 617 and 619 are connected to B + via a load resistor 615. The mutually connected collectors of the transistors 617 and 619 are connected to the input starting point 607 via a DC voltage transformer arrangement with a pnp transistor 603, the emitter of which is connected to B + via a resistor 621, its base to the resistor 61S and to its collector is connected to the connection point between the anode of a diode 623 and the base of a transistor 601. The cathode of the diode 623 is connected to ground. A resistor 605 is connected between the emitter of transistor 601 and ground, while the collector of transistor 601 is connected directly to the base of transistor 609 (ie, input exit point 609)

As in connection with F i g. 1, the coil 82 and the capacitor 80 are located outside the integrated circuit board 22 and are connected to this via the connection contacts 7} and T) . The base of the transistor 617 is connected to the connection contact T ₃ , a point at which the DC voltage is essentially equal to the connection contact T ₂ connected to the base of the transistor 609. The resistor 615 develop output signals are coupled via an emitter follower transistor 677 and a suitable Spannungsübertragungs- and reversing assembly 671 at output terminals A and A.

The resonant circuit with the coil 82 and the capacitor 80 is a current sensing arrangement with a designed in emitter follower circuit constant current transistor 625, the with a bypass control or variable load transistor 627 is coupled, assigned. The base of transistor 625 is through a Reference voltage source, consisting of the Power supply B + connected series connection of a resistor 629 and a Zener diode 631, biased to an essentially fixed voltage. a zener diode 637 and a resistor connected to ground

639. The emitter of the transistor 625 is connected directly to the connection contact T ₃ for the coil 82. The collector of the transistor 627 is connected to the connection contact T ₃ via the emitter-collector path of a line-controllable transistor 641. The transistor Ö41 forms, together with a similarly operating transistor 643 and the transistor 627, a current splitter arrangement for the provision of a controllable reactive current parallel to the coil 82, as in detail in DE-OS 20 47 922 is explained

Difference DC control voltages for changing the reactive current flowing parallel to coil 82 are used the transistors 641 and 643 via emitter follower transistors 645 and 647 from the AFPR push-pull phase detector 36. The detector 36 contains a first Differential amplifier detector having a first composite signal current source transistor 649 which is connected to one of the Push-pull outputs of the stereo amplifier 24 according to FIG. 4 is connected For example, corresponds to Transistor 649 corresponds to transistor 561 in FIG. 4. The first Differential amplifier detector according to Figure 5 further contains two switch transistors 651 and 653, the common with their emitters to the collector of the current source transistor 649, with their collectors to a corresponding one of the outputs 71 and T ₅ and with their Bases to a corresponding one of the complementary 19 kHz square wave outputs (E, E) of flip-flop 322 in FIG. 2 are connected.

The phase detector 36 also includes a second differential amplifier detector having a second signal mixed current source transistor 655 (corresponding to the Transistor 563 in Fig.4), which has its collector on the emitter of two switch transistors 657, 659 is connected. The base of transistor 655 is connected to the other of the two push-pull outputs of the Stereo amplifier 24 connected in Fig.4. The bases of the transistors 657 and 659 are connected to the complementary square wave outputs E and E of the flip-flop 322 in FIG. 2 connected. The collectors of transistors 657 and -659 are connected to the output contacts 7s or T ₄ connected. That is, the collectors of the transistors 651, 653, 657 and 659 are cross-connected. The cross-connected collectors of the transistors 653 and 657 are connected via a collector working resistor 661 and the collectors of the transistor Ren 651 and 659 are connected to an operating voltage source (B +) via a collector load resistor 663. Instead, to minimize the effects of any mismatch between resistors 661 and 663, one can, too smaller sized resistors (z. B. 6 ohms) using and interconnecting the connecting contacts of the T ₄ and T ₅ far ends of these resistors, and (eg. 6 K also not shown) via an additional resistor to the common Connect the operating voltage. A filter capacitor 38 for the output signal is _{coupled between the terminal contacts T 4} and Ti outside the integrated circuit board. Further filter capacitors 673,675

are outside of the circuit board between the Connection contacts 7} or · Ts and ground switched Capacitors 673 and 675 are used to adjust the dynamic range of the demodulated signals zoom out. The emitters of the current source transistors 649 and 655 are connected to resistors 665 and 667, respectively Ground and are cross coupled through a resistor 669 to increase the gain in the detector raise.

In operation, the oscillator circuit generates a substantially sinusoidal at the connection contact 7} Oscillation with a nominal frequency of 228 kHz, which is mainly caused by the coil 82 and the capacitor 80 is determined.

The sine wave generated at the resonance circuit 82, 80 is symmetrically limited by the differential amplifier 609, 611, 617, 619 with associated circuit elements so that a symmetrical square wave with a fundamental frequency component of 228 kHz is generated at the resistor 615. This square wave is coupled via transistor 677 with the associated GieichspannungQbertragungsanordnung to the terminal Ä and stelri there as one of the two complementary 228kHz-Pechteckausgangsschwingungen ready The second 228 kHz square wave output waveform at terminal A is generated by the additional Spannungsübertragungs- and reversing assembly 671 typically produce the Voltage transfer arrangements Square waves with upper and lower voltage values of nearly 2 volts and zero, respectively.

The square wave output oscillations A, Ä are in connection with Fig. 1, 2 and 3 in frequency divider and logic circuits to inter alia complementary 19 kHz switching signals E, ZT with a predetermined phase position to the 228 kHz square waves A, Ä, corresponding to the relevant signal curves in Figure 3, all processes positively and negatively directed transitions in the signal e are coincident with positive going transitions in the signal A, the positive-going transitions in signal e in each case with every twelfth positive-going transition in signal A coincide.

The phase of the 19 kHz switching oscillations E, E is compared in the phase detector 36 with the phase of the 19 kHz pilot signal from the stereo amplifier 24. Opposite DC voltages are always generated at the connection contacts 7} and T ₅ when the pilot signal component at the output of the stereo amplifier 24 is not phase shifted by 90 ° with respect to the 19 kHz switching oscillations E, E. The polarity of the direct voltage at the connection contacts Γ «and Ts shows whether the pilot signal leads or lags the switching oscillation to restore the required 90 ° phase relationship between the 19 kHz oscillations. The numerous output signals of the flip-flops shown in FIG. 2 are therefore kept in a predetermined phase relationship to the 19 kHz output pilot signal of the stereo amplifier 24, so that the pilot signal, stereo difference signal and interference information above the signal frequency band can be recovered with the aid of synchronous detectors, like in In connection with Figs. 6, 7 and 8 will be explained. The non-synchronous components (i.e. all components with the exception of the 19 kHz pilot signal) of the stereo signal mixture fed in, as well as the 19 kHz switching oscillations E _{1 £ fed to the bases of the transistors 651, 653 L} 657, 659, do not generate any DC components due to the symmetrical structure of the phase detector 36 at the output contacts 74, Ts. Other high-frequency components, which are generated by the phase detector 36, are removed at its output by the low-pass filtering of the capacitor 38 and the associated resistors at the connection contacts Ta and 7s in the absence of a received stereo signal, the receiver measures tunes to a stereo signal and then changes the inductance of the coil 82 (for example with the aid of a tuning core) so that the previously measured voltages are restored. The oscillator 26 then works with its nominal frequency of 228 kHz in the desired phase relationship to the received 19 kHz pilot signal. This adjustment is normally done in the factory, but can easily be done by a service technician at home as it is very simple and does not require any complicated test equipment. 1 and the other figures must be made.

F i g. 6 shows a differential signal detector and matrix amplifier circuit for demodulation that is particularly well suited for implementation in integrated form and connection to the stereo amplifier 24 (FIGS. 1 and 4) and the flip-flop 318 (FIG. 2) within the integrated circuit board 22 the difference signal component (L - R) of the stereo signal mixture and the combination of this component with the audio sum signal component (L + R) to generate stereophonically linked left and right channel audio signals.

The differential signal detector contains a doubly symmetrical synchronous detector (ring demodulator) with two current source transistors 701 and 703, which correspond to the transistors 561 and 563 in FIG. The bases of the transistors 701 and 703 are each connected directly to one of the push-pull outputs of the stereo amplifier 24 in FIG. 4 connected. The emitters of the transistors 701 and 703 are each connected to ground via a resistor 705 or 707. The collector of transistor 701 is connected directly to the interconnected emitters of a first pair of switch transistors 709, 711, while the collector of transistor 703 di ~: ki is connected to the interconnected emitters of a second pair of switch transistors 713, 715. Dv bases of transistors 709 and 713 are connected to one of the complementary 38 kHz square wave outputs (D) of flip-flop 318 (Fig. 2), while the bases of transistors 711 and 715 are connected to the other of these complementary 38 kHz square wave outputs (DJ An operating voltage source (B +) k \ is connected to the collectors of the two transistors 709 and 715 via an output resistor 717 and to the collectors of the two transistors 711 and 713 via an output resistor 719 that is essentially the same as the resistor 717.

Push-pull output signals, which the demodulat-

The differential signal components [(L - R) and - (L - RJ]) are generated at the resistors 717 and 719 and coupled to emitter follower transistors 721 and 723. The transistors 721 and 723 serve as voltage sources and generate the desired differential signal components at resistors 725 and 727. The sum signal information (L + R) is generated together with the rest of the signal mixture also at the resistors 725 and 727 by means of transistors 729 and 731, which have their collectors to the resistors 725 and 727 and their bases to one of the Push-pull outputs (to which L + R are available) of the stereo amplifier 24. The emitters of the transistors 729 and 731 are each connected to ground via a resistor 733 and 735. The transistors 723 and 731 form the matrix amplifier 42 (FIG. 1), its Output signal (z. B. / fy via the connection contact Tw, the equalization network 46 and a sound output amplifier to a sound reproduction device, beispie llike a loudspeaker is coupled. The transistors 721 and 729 form the matrix amplifier 44 (Fig. 1), the output signal (z. B. L) via the connection contact Γιο, the equalization network 48 and a second sound amplifier on z. B. a second speaker is coupled.

To the modulation of the base-emitter voltages of the transistors 721 and 723 by collector current fluctuations of the transistors 729 and 731, the stereo amplifier 24 with respect to the Transistors 729 and 731 fed signals complementary signal mixtures fed to the bases of condensation transistors 737 and 739. The collectors of the Transistors 737 and 739 are connected directly to the emitters of transistors 721 and 723, respectively. The emitters the transistors 737 and 739 are each connected to ground via a resistor 741 and 743, respectively.

The current line of the transistors 731 and 739 changes accordingly by the same amounts in opposite directions the changes in the output signals of the stereo amplifier 24 (push-pull input signals). The sum of the collector currents of transistors 731 and 739 (which load transistor 723) therefore remains in essentially constant. Likewise, changes in the output signal of the stereo amplifier 24 do not cause any changes the load on transistor 721, since the sum of the collector currents of transistors 729 and 737 remains essentially constant when the output signal of the stereo amplifier 24 changes. An exact Matrixing of the sum and difference signal components is therefore guaranteed

In the operation of the differential signal detector according to FIG. 6, the complementary 38 kHz square wave output of flip-flop 318 (D, D) is maintained in the correct, predetermined phase relationship to the received pilot signal component, as in connection with FIG. 2 and 5 explained so that a synchronous demodulation of the difference signal is achieved. The push-pull synchronous detector m: t to the transistors 701, 709, 711 and the transistors 703, 713, 7-5 supplies complementary signal components including voltage components which reflect (L - R) and - (L - R) at the resistors 717 and 719, respectively passed via the foiger transistors 721 and 723 and combined before the equalization at the resistors 725 and 727 with currents which represent the sum signal component (L + R) supplied by the amplifier 24. The sum signal current components are fed to the corresponding load resistors 725 and 727 via the current source transistors 729 and 731. By superimposing the differential signal voltages and the sum signal currents, the desired matrixing results, which is essentially independent of the load on the output contacts Tto and T \ 1. The equalization networks 48 and 46 coupled to the contacts Tio and T \ \ modify the matrixed signals in such a way that the desired left-tone and right-tone signal components (L) and (R) result. Because of the doubly symmetrical nature of the synchronous detector and the low-pass characteristics of the equalization networks 46, 48, no components other than the desired left-tone and right-tone signals occur at the output filter capacitors of the networks 46, 48.

The correct matrixing of the sum and difference signals depends on; zmvp. Part of “J? R adjustment of the currents supplied by the current source transistors 701, 703, 729 and 731. Such an adaptation can be achieved relatively easily in an integrated circuit by fitting essentially identical transistors 701, 703, 729, 731 and essentially identical emitter resistors 705, 707, 733 and 735 close together on the circuit board 22.

The fc.ft wall-free matrixing also depends on the ratios of resistors 717 and 719 to resistors 725 and 727. In the present dcppeltsymmetrisdien synchronous detector arrangement, the switch transistors 709, 711, 713, 715 are fed with symmetrical 38 kHz square waves of the correct phase position, so that a full-wave or two-way demodulation of the 38 kHz differential signal subcarrier takes place. The resulting peak-to-peak value of the audio frequency components of the demodulated difference signal is linked to the peak-rectified carrier at the detector output by a factor of 2π . The peak differential carrier for the composite signal is set in accordance with the standards for stereo broadcasting so that it is equal to the peak sum component for a left-only signal or a right-only signal. In order to obtain a perfect matrixing of the sum and difference signals, the resistors 717 and 719; r / 2 times as large as the resistors 725 and 727, at which the sum signal components are generated. 6 furthermore contains an arrangement which automatically blocks or switches off the differential signal demodulation circuits when either the prolonged absence of a pilot signal exceeding a predetermined amplitude indicates that a non-stereophonic (monophonic) program is being received, or the signal-to-noise ratio of the received signal is considered insufficient for satisfactory stereo playback. The way in which a stereo signal is obtained becomes a hand of fig. 7 and 8 explained For the time being, it suffices to state that such a blocking signal is generated in both of the above-mentioned cases.

In the arrangement according to FIG. 6, the stereo blocking signals are fed to an amplifier with a first transistor 741 which has its collector connected to the operating voltage source (B +), its base connected to a source of the stereo blocked signals and its emitter connected via a resistor 743 to the base

Switch transistor 745 is connected. The emitter of the transistor 745 is connected to ground, and an output switching signal is picked up at the collector of this transistor via a resistor 747 connected to the operating voltage source. The output of the switch transistor 745 is coupled to a multiple VgrVorspanno ^ elle, as described in DE-OS 18 06 4b7. The term "Ve / =" here denotes the forward voltage drop at the base-emitter junction of a normally conducting transistor (e.g. approximately 0.65 to 0.7 volts for silicon transistors such as those found in integrated circuits). Reference voltage sources (usually within the integrated circuit) which provide one or more integer multiples of Vbe above zero potential at \ s low impedance be as "multiple V _BE - referred to voltage sources." In the present case, the multiple Vgp voltage source contains a transistor 749 in a collector circuit and a transistor 751 in an emitter circuit, which are connected together with negative feedback. The collector of the transistor 749 is connected to the operating voltage source, while several resistors 753, 755, 757 are connected in series between the emitter of the transistor 749 and ground. The junction of resistors 755 and 757 is connected to the base of transistor 751. The emitter of transistor 751 is connected to ground, while the collector of transistor 751 is connected directly to the base of transistor 749. As explained in DE-OS 18 06 467, with conductive transistors 749 and 751 at the resistor 757 there is a voltage equal to Vbe- The ohmic value of the resistor 757 is smaller than the base-emitter resistance of the transistor 751, and the additional resistors 753, 755 are smaller than the input resistances of the corresponding stages to which they are coupled. In this case, the series-connected resistors 753 and 755 produces a voltage on each of which is equal to the product of V _B e and the relationship between the respective resistor (753 or 755) and the resistor 757. Namely, especially in the Circuit according to FIG. 6 generates a voltage of 7 Vbe at the emitter of transistor 749 and a voltage of 4 Vec at the junction of resistors 753 and 755.

The junction of resistors 753 and 755 is connected to the bases of two stereo transisotropes 759 and 761. The emitters of transistors 759 and 761 are connected to the interconnected emitters of switch transistors 709, 711 and the interconnected emitters of switch transistors 713, 715, respectively. The collectors of transistors 759 and 761 are interconnected and connected to the emitters of current splitter transistors 763 and 765 via an emitter resistor 767 and 769, respectively. The bases of transistors 763 and 765 are tied directly to the emitter of transistor 749 (7 V _BE when the multiple V β £ voltage source is operating). The collectors of transistors 763 and 765 are connected to resistors 717 and 719, respectively.

Between the input and the output of the switchable multiple VW voltage source is a Feedback device switched to the speed with which the arrangement switches from stereo to mono operation processing circuit contains a transistor 771, which has its collector through a resistor 773 to the Base of transistor 745, with its base connected through a resistor 775 to the emitter of transistor 749 and is connected to ground with its emitter.

In operation, if the in connection with F i g. Arrangement to be explained 7 and 8 indicates that stereo information suitable for reproduction is no longer present or no longer present, the voltage at the base of transistor 741 falls below a predetermined value (e.g. 1 volt), and transistors 741 and 745 begin to switch to the non-conductive state. The voltage at the base of the transistor 749 rises in the positive direction, so that the transistor 749 and then the transistor 751 conducts, whereby the multiple voltage source is switched on. This switching process is supported by transistor 771, which, together with transistors 749 and 751, begins to conduct. The transistor 771 switches off the transistor 745 very quickly as soon as the switching process begins. A positive voltage (4 \ 'üt) provided at the connection point of the resistors 753 and 755 causes the stereo blocking transistors 759 and 761 to conduct. Likewise, a positive voltage (7 Vbe) available at the emitter of transistor 749 causes current splitter transistors 763 and 765 to conduct.

In conducting transistors 759 and 761 of the switch transistors 709 and 711 and to the common-connected emitter of the switch transistors 713 and 715, a positive voltage (3 V _B s) is coupled to the interconnected emitter sufficient to these switch transistors and thereby to lock the difference signal detector or switch off. The push-pull signal mixes supplied via the current source transistors 701 and 703 are then derived by the blocking transistors 759 and 761 and cancel each other out at the connected collectors of the transistors 759, 761. There, the direct current components of the output signals of the current source transistors 701 and 703 are combined. These combined DC components are then split into equal components by resistors 767, 769 and transistors 763, 765, which are coupled to load resistors 717 and 719. The DC biasing voltage across the matrix transistors 721 and 723 is therefore kept essentially the same for both stereo and mono playback. If this were not the case, ie if the bias voltage were to change when the arrangement was switched from one operating mode to the other, a thud would be heard in the loudspeakers. Such undesirable noise is prevented by the arrangement described above.

The differential signal detector remains inoperative until the presence of an appropriate one Input signal corresponding to the pilot signal at transistor 741, transistors 741 and 745 are switched on and thereby the multiple Vsp voltage source as well as the blocking and splitting stages are switched off.

As mentioned above, an input signal greater than about 1 volt (low current Vbe of transistor 741 plus moderate current Va ^ of transistor 745) is sufficient to keep transistors 741 and 745 conductive (and hence stereo operation to maintain). On the other hand, if the transistors 741 and 745 are turned off and the transistor 771 is turned on (ie in mono operation), a positive voltage of more than! Volts at the base of transistor 741 are required to restart stereo operation, since in this case resistors 743 and 773 are parallel via transistor 771 as a voltage divider

to the input (base-emitter path) of the transistor 745. Namely, an input voltage of about 3 V _B e (approximately 2 volts) required at the base of the transistor 741 to switch to stereo operation. The difference between the voltage levels required at the base of the transistor 741 for switching on the stereo mode or for maintaining it results in a desirable hysteresis characteristic, as a result of which the stereo reproduction, once it has been initiated, is retained even if there are brief fluctuations in either the received pilot signal level or occur in the signal-to-noise ratio of the demodulated signal.

When stereo information suitable for reproduction is received and processed in the receiving section (indicated by the arrangement to be explained in connection with FIGS. 7 and 8), the base of transistor 741 receives a positive input voltage which is sufficient to make this transistor conductive do. Transistor 745 also conducts so that the input to transistor 749 is not positive enough to render transistor 749 conductive. The multiple VW voltage source with transistors 749 and 751 and all transistors 759, 761, 763 and 765 are therefore switched off. The differential signal detector stages operate under these conditions, so that signals (L - R) and - (L - ,) are generated in the manner described above. The transistor 771 is also switched off under these conditions.

F i g. 7 shows an arrangement for perceiving the signal-to-noise ratio of the received composite signal and for providing a stereo blocking signal when this signal-to-noise ratio is below a predetermined one for the This signal-to-noise ratio detector with the associated Steps is particularly suitable for building in an integrated form and for interconnection with the stereo amplifier 24 (Fig. 1 and 4) and the flip-flops 312, 318, 322, 328) (Fig. 2) within the integrated circuit die 22.

The signal-to-noise ratio detector contains the push-pull synchronous detector 68 with white current source transistors 801 and 803, the bases of which are directly connected to one of the push-pull outputs of the stereo amplifier 24 in FIG. 4 are switched on. The emitters of the transistors 801 and 803 are connected to ground via a common emitter resistor 805. The collector of transistor 801 is directly connected to the interconnected emitters of a first pair of switch transistors 807, 809, while the collector of transistor 803 is directly connected to the interconnected emitters of a second pair of switch transistors 811, 813. The bases of transistors 807 and 811 are connected to one of the complementary 114 kHz square wave outputs S, θ of the flip-flop 312 (Fig.2), while the bases of the transistors 809 ^ and 813 are connected to the other of these two outputs B, B. An operating voltage source (B +) is connected directly to the collectors of the transistors 807 and 813 and connected via the series connection of a forward-biased voltage drop diode 815 and a resistor 817 to the interconnected collectors of the transistors 809 and SIl. The interconnected collectors of the transistors 809 and 811 are further connected ω to the connection contact 7Ή of the integrated circuit board and via a Zener diode 819 to the operating voltage source (Ή +). A capacitor 76, which determines the bandwidth of the signal-to-noise ratio detector 68, is coupled outside the circuit plate between the connection contact Tu and ground. An interference threshold regulator, consisting of a variable resistor 821 coupled via the operating voltage source and a series resistor 823 coupled between the connection contact Tu and the wiper of the resistor 821, can be provided outside the circuit board 22 in order to enable the signal-to-noise level to be set at which stereo blocking signals are generated . Instead, it is also possible to set an acceptable signal-to-noise ratio solely with circuit elements within the circuit chip 22, so that the circuit elements 821 and 823 can be omitted.

A transistor 825 and two Darlington pair transistors 827 and 829 form one Differential amplifier for the perception of interference. Di? The base of the transistor 829 is connected to the connection contact ΤΉ connected. The base of transistor 825 is connected to a Reference voltage source 831 connected. The reference voltage source 831 is from a DC voltage balancing arrangement with transistors 567 and 835 designed in a differential circuit, which lead to the stereo amplifier 24 belong, fed. The bases of transistors 567 and 835 are directly connected to the bases of transistors 517 and 547 in FIG. 4 connected. The collectors of transistors 567 and 835 are across the series connection of the resistors 569 and 571 connected to the operating voltage source ß-t-. One taken from the junction of resistors 569 and 571 DC reference voltage is coupled directly to the base of transistor 825. This DC reference voltage supply arrangement Corresponds in terms of direct current to the interference detector elements 810-817 and supplies a direct voltage which changes in the same sense like the quiescent DC voltage that the interference detector provides at the base of transistor 829.

The output signal of the differential amplifier with the transistors 825, 827, 829 is generated at a resistor 843 which is connected between the operating voltage source S + and the interconnected Kolk. <Gates of the transistors 827 and 829. Connected to resistor 843 is an average value detector having an arrangement for increasing the duration of fault-indicating pulses. The mean value detector contains a detector transistor 845, the emitter of which is connected to ground via a resistor 847, its collector to the operating voltage source B + via an operating resistor 849 and its base to a pulse stretching circuit 851. The collector of the transistor 845 is connected to the connection contact 7a of the integrated circuit chip (FIG. 1) and to the OR gate 66 in the stereo blocking circuit 70 (FIG. 1). The capacitor 626 (FIG. 1), which is also connected to the connection contact Tg, filters the output signal of the transistor 845.

The pulse stretching circuit 851 contains a bistable multivibrator with two transistors 853 and 855, the a! s flip-flops are of the set-reset type. Fault indication pulses generated at resistor 843 are to the set input of the flip-flop (i.e. the base of transistor 853) via a voltage transfer and Amplifier circuit with a transistor 857, a Zener diode 859, a resistor 861, a resistor 863 and a transistor 865 are coupled. The circuit elements 857, 859, 861 and 863 are shown in FIG specified order via the operating voltage

27 28

source 0+ switched. The resistor 843 is to be compared to the menen interfering components to the Base of transistor 857 (which is to be measured by the opposite signal-to-noise ratio. Variable resistor 821, if The type of line, like the vast majority of transistors, is available by hand (by the manufacturer the integrated circuit board) connected in such a way that the resulting pretensioning, while the base of transistor 865 nvt the 5 voltage transistors 827 and 829 for all Connection point of the resistors 861 and 863 detector output signals connected to the connection contact Tm is. The collector of the transistor 865 is to be kept blocked, which are smaller than the one through the base of transistor 853 and the collector of the acceptable out-of-band transistor given this setting 855 connected. The base of the transistor noise level.

855 (the reset input of the flip-flop) is connected to an io. The push-pull output signals of the stereo over source of periodically recurring pulse amplifiers 24 are connected to the current source transistors 801 and 803, which are supplied by combining the output signals. The switch transistors 809 and 811 Ie of the flip-flops 318, 322 and 328 can be obtained. And the 19 kHz square-wave output and 114 kHz square-wave input signals B and B alternating (E) cies_FJipflops 322, which are 19 kHz between the saturated and the blocked output oscillation (F ) of the flip-flop 328 and the one state is switched. Interference components in the output signal 38 kHz output oscillation (D) of the flip-flop 318 gnal of the amplifier 24, the frequency of which is combined at or in dtr by ORing and is close to the 114 kHz switching frequency, are generated twice by amplifiers with transistors 867 and 869 the superposition effect of the detector 68 into one of the reverse. The collector of transistor 869 is transmitted to the 20 zero upward-reaching frequency band, base of Tt insistors 855 and 871 (and to the collector of transistor 853 while other components in the composite signal) are connected. The output pulses generated by the flip-flop 853, 855, the capacitor 76 and the associated resistors at the collector of the transistor 853 (e.g. the resistors 821 and 823) are transmitted outside the low-pass range of the filter via a voltage transfer stage with 25. The capacitor 76 is dimensioned in connection with the transistor 871, resistors 873 and 875 a named resistor so that the transistor 877 and a resistor 879 result in the basis of the desired interference detector frequency response. Disturbance detector transistor 845. components within the predetermined bandwidth

During operation of the arrangement according to FIG. 7, the 114 kHz generated by the pulse at the connection contact Tu . Reference DC voltage supplied to circuit 831. Transistors 827 and 829 respond to positive quiescent DC voltage, the pulses directed to the base of transistor 829, the amplitude of which is supplied together with interference detector 68. That is, the current source transistors 801 and 803 generated via resistor 821 on capacitor 76 are sufficient in the bias voltage generated to overcome the bias voltage supplied via transistor 825 in the same way as transistors 567 and 835, and there only half that of the 35 den. Each such positively directed pulse, which the transistors 801 and 803 supplied direct current reaches the presence of excessively strong out-of-band working resistance 817, which indicates the corresponding interference, is through the circuit with the working resistance 569 in the reference voltage source transistors 827, 829, 857, 865 with The associated S31 is only half as large as the load resistance circuit elements transmitted and the polarity was 817. The resistance "> 71 simulates the effect 40 in reverse. The corresponding negatively directed switch transistors 809, 811 in the detector 68. The pulses reach the base of the Transistor 853, so that diode 815 supplies the same as the base-emitter line, the flip-flop 853, 855 is set (i.e. transistor 853 threshold transistor 829 part of the desired non-conductive, transistor 855 conductive and output signal threshold shift between the inputs for transistor 871 in high-voltage or ; '■ «-Zu Transistors 825 and 827. Since the reference voltage source was 45). The flip-flop 853, 855 remains in the "!" State until Ie 831 and the detector 68 are fed from a common source from the transistor 869 to the next negative operating voltage source B + and in the level transition to the reset input at the base of the same area on the circuit board 22 transistor 855 arrives. The generation of the resets are arranged, fluctuations or changes occur in_F i g. 3 illustrated by the three signals "E + F", with one DC voltage also in the other 50 "E + F + D" and E + F + D. In the case of the DC voltage on and it is avoided that the generation of these reset pulses is affected by the related changes on the operation of the disturbance telephony with F i g. 2 exploited fact that tors 68 have an impact. the output of flip-flop 328 by a small one

As is well known in FM receiver art, interval (e.g., on the order of 5 microseconds the peak amplitude of sound signals (and higher frequencies) compared to the level transitions of the main quentas Signals) at the output of the FM demodulator trigger signals from the oscillator 26 is delayed. Of the 20 regardless of the respective reception conditions. Reset pulse is applied during this small delay (i.e., RF signal level and receiver noise) is generated at the interval

essentially constant, that is, the peak dunodu- If the flip-flop 853, 855 is in the "1" state

The signal amplitude is determined by the transmitter-side 60 (presence of excessive interference), frequency deviation and the transmission characteristics - the transistors 871, 877 and 845 are all conductive stik of the demodulator, but not by the received and discharges the capacitor 626. Whom; the signal amplitude is set. The stereo amplifier 24 has excessive interference for a long enough period of time, giving a stable gain characteristic. The capacitor 62b is discharged to such an extent that an essentially constant DC voltage OR element 66 and thus also the stereo blocking circuit as a measure of the signal level at the output of the circuit 70 is activated, as in connection with FIG. 8 Use amplifier 24. This is described in more detail by the circuit 831,
The DC voltage supplied can then be perceived

29 30

Set input of the flip-flop 853,855 hold the base faults indicating the short-term presence of

of the transistor 855 supplied pulses the flip-flop interference of large amplitude, which is the permissible

853, 855 in the reset state, so that the interference threshold is exceeded, calls on the capacitor 62b

Transistors 871, 877 and 845 all turned off a comparatively low voltage, so

are. The voltage across capacitor 62b then only shows that the mode switching arrangement is not activated

the presence <j the absence of the pilot signal is indicated.

(see Fig. 8), and the stereo lock circuit 70 operates in Fig. 8. 7 a power supply is provided,

corresponding. the voltage levels of e.g. B. +6.2 volts and +3 Vbe

The circuit with the flip-flop 853, 855 and the volt supplies, which in other parts of the circuit board Flip-flop 322 stretches the demodulated interference-indicating io chens 22 (e.g. used for the flip-flops in Fig. 7) Pulses so that there will be an effective increase in the. There are numerous circuit layouts for this. Demodulation amplification of these glitches results in useful conditions and the arrangement shown here

without the amplitude (the dynamic range) of is only one possible embodiment.

Signals must be increased, the z. B. from the case of FIG. 7 power supply Detector transistor 845 and the upstream transistor circuit is an external β + voltage source (from

storage stages are processed. e.g. +8.5 volts) via the connection contact Tn to the

And TTvar will be the arbitrarily occurring collector of a first emitter-follower transistor 802 Glitch pulses, which are characteristically connected to a short one. The emitter of transistor 802 is over Have duration and variable amplitude at which the series connection of a resistor 804 and Processing in flip-flop 853,855 in pulses variable 20 of several transistors 806,808,810 and 812 with ground

rather duration ( ^{depending on the} relative phase position of the connected. The transistors 806 and 810 are each as

Reset pulses and the demodulated glitches) diode switched by their collector and their base

and fixed amplitude (determined by the »U-Aus are directly connected to each other. The emitters of the

output voltage of 853, 855) implemented Depending on the transistors 806 and 810 are connected to the bases of

relative phase of the reset pulses and the demodulation 25 transistors 808 and 812, respectively. The collective

flip-flop 853, 855 of transistors 806 and 808 are combined.

on the output side the "!" state over a period in the sound and with that of the emitter of transistor 802

Range from zero to the 19 kHz period. The far end of resistor 804 is connected. the

mean duration of the collectors of the transistors 810 and 812 supplied by the flip-flop 853, 855

treated pulses is therefore half of the 30 interconnected and connected to the emitter of the transi-

Period of the applied reset oscillation (i.e. stors 808 connected. The emitter of transistor 812

about 25 microseconds). depends on mass. The base of transistor 802 becomes

The disturbance-indicating direct voltage at the output by means of a between the connection contact Tn and

(Collector) of the detector transistor 845 is therefore biased to the ground coupled voltage divider

by the pulse stretching in the flip-flop 853, 855 with 35 from the series connection of a resistor 814, one

associated circuits increases or enlarges Zener diode 816 (with a nominal Zener voltage of

In contrast to a simple interference integrator 5.5 volts) and the transistors 810 and 812, there is an or a high-gain interference amplifier under the connection point of the resistor 804 and the present collector of the transistors de interference detector, which works with pulse stretching, separates the permanent presence 40 806 and 808 is an amplifier with low, relatively weak level interference, the greater output resistance is connected. The amplifier is greater than the preset interference threshold (one contains a collector load resistor 818, the state in which switching to mono reception between the connection contact Ti ₂ and the collector is desired), and the momentary presence of a transistor 820 is switched, another high level, Brief oscillations of instead of transistor 822, which with its collector directly to the disturbances (a state which is temporary, so emitter of transistor 820 is connected, that switching to mono reception is not desired). between the emitter of transistor 822 and ground While the interference threshold circuit 825, 827, 829 supplies the connected emitter resistor 824 and a return output signal that contains the amplitude characteristics coupling branch with a demodulated interference between the collector of the characteristic, so transistor 820 and the base of transistor 822 normalize that bistable flip-flop 853, 855 the amplitudes of the switched Zener diode 826 and one between the supra-threshold interference pulses. The flip-flop 853, 855 base of transistor 822 and connected to ground effectively amplifies the short-term pulses with respect to resistor 828.

the long-term pulses by adding each of these pulsar- In operation, the transistor 802 through the ien is on average to the same width that is generated by the ss biasing network with the circuit elements 814, reset frequency of the flip-flops 853, 855 (19 kHz in the 816, 810 and 812 in the conductive state pre-stressed present case) is determined, is stretched. The transistors 810 and 812 are conductive and supply the amplitude of the interference pulses that trigger the flip-flop 853, 855 of the base of the transistor 810 a nominal DC voltage, are not +2 V _B f at the output of the flip-flop 853, 855. (Vbe is defined as a range of distinguishable from one another. The normalized output 60 voltage values, which are present at the base-emitter junction of an output signal of the flip-flop 853, 855 then reach a transistor when this junction conducts). In the signal integrating arrangement (capacitor 62b), which of the present arrangement, the transistor 812 conducts the extended duration of the demodulated pulses more strongly than the transistor 810, so that the base-emitter voltage amplitudes convert. The downstream voltage of transistor 812 is actually somewhat larger stereo-mono switching arrangement (FIGS. 6 and 8) 65 than that of transistor 810. However, this is insignificant to a relatively high voltage at the difference in the present case and capacitor 626, which the permanent presence is therefore ignored if the preset interference threshold is exceeded

Base-emitter junction creates a voltage drop of Vbe The voltage at the emitter of transistor 802 is therefore equal to the sum of the voltage at Zener diode 816 and t Vk (e.g. approximately + 6.2 volts),

The transistors 820 and 822 are also biased into the conductive state, the base of the transistor 820 carrying a voltage of +4 Vbe due to the operation of the transistors 806,808,810 and 812.The emitter of the transistor 820 is therefore set to +3 Vbe (2nd B. approximately 2 volts) and forms a low-resistance voltage source for the numerous flip-flops on the circuit board 22.

F i g. Fig. 8 shows an arrangement that facilitates the reception of stereo broadcasts suitable for reproduction indicates

The arrangement including a detector for the presence of the pilot signal and a circuit for generating it of automatic stereo switching signals is particularly suitable for the construction in integrated form and is connected to the stereo amplifier 24 (FIGS. 1 and 4), the flip-flop 328 (FIG. 2), the stereo blocking circuit (FIG. 6) and the interference suppression circuit (F i g, 7) in the integrated circuit board 22 can be connected.

The pilot signal detector contains a doubly symmetrical synchronous detector with two current source transistors 901 and 903. The bases of the transistors 901 and 903 are each connected to one of the push-pull outputs of the stereo amplifier 24 in FIG. The emitters of the transistors 901 and 903 are connected via a resistor 905 and are each connected to ground via a resistor 907 and 909, respectively. The collector of transistor 901 is directly connected to the interconnected emitters of a first pair of switch transistors 911, 913, while the collector of transistor 903 is connected directly to the interconnected emitters of a second pair of switch transistors 915,917 and the bases of transistors 911 and 915 are connected to one of the complementary outputs F, F of the flop 328 in FIG. 2 connected, while the bases of the transistors 913 and_917 are closed to the other of the complementary outputs F, Fan. The collectors of the transistors 911 and 917 are connected to an output terminal T ₈ , while the collectors of the transistors 913 and 915 are connected to an output terminal Ti . The arranged outside of the circuit board 22 filter capacitors 62a and 62ύ are connected between the connection contacts Ti and T% on the one hand and ground on the other hand. The base-emitter junction of a clamping transistor 921 is connected between the connection contacts Ti and T ₈ . An operating voltage source (B +) is directly connected to the collector of the transistor 921, via the resistor 849 (see FIG. 8) to the collectors of the transistors 911 and 917 and via the series connection of resistors 923 and 925 to the collectors of the transistors 913 and 913 915 connected. A differential amplifier with transistors 927 and 929 is connected to the connection contacts Ti and T ₈ . The emitters of transistors 927 and 929 are connected to ground via a common resistor 931. The base of the transistor 927 is supplied with the output signal generated at the collectors of the transistors 911 and 917, since this base electrode is connected to the connection contact Ti . The output signal of the transistor 845 (FIG. 7) indicating the presence of disturbances is also fed to _{the connection contact T 8.} The base of the transistor 929 is connected to the connection point of the divider resistors 923 and 925 and thus receives the output signal generated at the collectors of transistors 913 and 915. The resistors 923 and 925 are dimensioned so that the transistor 929 in the absence of a differential span voltage (ie in the absence of an indication of the presence of a pilot signal) between the connection contacts Ti and Ta is kept in the conductive state. The collector of the transistor 929 is connected directly to the operating voltage source (B +) , while

ίο the collector of transistor 927 is connected to the operating voltage source (B +) via a load resistor 933. Signals generated at resistor 933 which indicate that both a 19 kHz pilot component and no excessive interference at the output of the Amplifier 24 are present, a level transfer stage with an emitter follower transistor 935, an emitter working resistor 941 and one between resistor 941 and the emitter of transistor 935 switched Zener diode 939 fed to the collector of transistor 935 is connected to the operating voltage source connected. The connection point of the resistor 941 and the diode 939 is above similar resistors 945 or 943 with the bases of a first transistor 937 in an emitter circuit and a further transistor 947 connected in parallel in an emitter circuit. The collector of transistor 947 is connected via a load resistor 971 connected to an operating voltage (+ 6.2VoIt). The signals generated at the resistor 971 are transmitted via an emitter follower transistor 973 and a time constant tennetzwerk 975 to the stereo lock input of the Transistor 741 (Fig. 6) coupled. The time constant network 975 includes one between the emitters of the The transistor 973 and the ground emitter resistor 977 are connected between the emitter of the transistor 973 and the base of the transistor 741 connected relatively large series coupling resistor 979 and the filter capacitor 72 connected between the base of transistor 741 and ground. Sator 72 is connected to the circuit board 22 via the connection contact Ti _3.

The second load coupled via resistor 941 contains the collector of transistor 937, which is connected via the Series connection of a resistor 949 and a diode 951 is connected to the operating voltage source (B +)

The collector of transistor 937 is also connected to an emitter follower transistor 955. the Transistors 937 and 955 with their associated

“Circuit elements work as regenerative switches or hold circuits with two stable states, designated as a whole by 919. Between the emitter of transistor 955 and ground is the series connection of a Zener diode 963 and an emitter resistor 957 switched. An emitter resistor 959 is connected between the emitter of transistor 937 and ground. One Diode 961 is connected between the ends of resistors 957 and 959 remote from ground. An output signal is obtained from transistor 955 by means of an intermediate

«O the connection point of the resistor 957 and the Zener diode 963 and the output terminal T _{9 of} the circuit board 22 connected resistor 965 obtained. The output signal generated at the connection contact Tg is based on a lamp supply

U transmission transistor 967 coupled in the emitter circuit (outside of the circuit board 22). A pilot signal indicator lamp 969 is connected between the collector of transistor 967 and an external DC voltage supply.

supply that is sufficient to keep lamp 969 glowing to bring switched

In the operation of the pilot signal detector, the push-pull signal mixtures fed to the current source transistors 901 and 903 by the stereo amplifier 24 are demodulated by the stereo amplifier 24 with the aid of the complementary 19 kHz square waves F, F fed to the switch transistors 911, 917, 915, 913 -Pilot component, which indicates the reception of stereo transmissions, are generated by the detector arrangement on the capacitors 62a and 62Z> opposing DC voltage components The arrangement (especially the phase position of the flip-flop 328) is set up so that when the oscillator 26 is working properly, the resulting DC voltage component on the capacitor 626 is more positive than the DC voltage component generated across capacitor 62a. The transistor 927 is therefore made conductive when the pilot signal is present. When the transistor 927 conducts, the current conduction of the transistors 935 and 937 decreases. As the current conduction of the transistor 937 decreases, the current conduction of the transistor 955 increases. The voltage at the emitter of the transistor 955 becomes more positive, and if it exceeds the sum of the Zener breakdown voltage of diode 963 plus the forward voltage of diode 961, a positive voltage is coupled to emitter dt * transistor 937 which blocks transistor 927 and keeps it blocked. At the same time, if the emitter voltage of transistor 955 is sufficiently positive, the transistor 967 switched on The indicator lamp S * »9 or other display device (e.g. an electromagnetic, articulated iron wing indicator) is therefore energized, so that the listener is informed that a stereo broadcast is being received.

Under these conditions (with stereo reception indicated by the current line of transistor 927), transistor 947 also becomes non-conductive and the transistor 973 conducts. The capacitor 72 begins via the transistor 973 and the resistor 979 charge to a positive voltage at a predetermined rate. After a predetermined duration of stereo reception (e.g. I second) has the capacitor 72 is charged to such an extent that the transistor 741 (FIG. 6) becomes conductive and the im Connection with F i g. 6 described duty cycle for activating the stereo difference signal detector is initiated.

The delay caused by resistor 979 and capacitor 72 is such that one ongoing stereo playback, once initiated, is reasonably assured.

If an essentially continuous or permanent 19 kHz pilot signal component is not present at the output of the stereo amplifier 24, the differential DC voltage component between the connection contacts Tg and Τη is not positive enough to keep the transistor 927 conductive, and because of the differential switching of the transistors 927 and 927 929, transistor 929 tends to conduct. The areas 923 and 925 are dimensioned in such a way that the transistor 929 is biased into the conductive state under this condition (ie in the absence of a 19 kHz pilot signal). When transistor 927 ceases conducting, transistor 935 conducts and supplies transistor 937 with an input signal that renders that transistor conductive. However, the transistor 937 remains non-conductive until the transistor 935 conducts sufficiently, to overcome the reverse voltage coupled from transistor 955 to the emitter of transistor 937. When this reverse voltage is overcome and the Transistor 937 conducts, transistors 955 and 967 are turned off. This turns on the stereo indicator light 969 deleted At the same time, the transistor 947 conducts, since the transistor 935 conducts. The transistor 947 works in Emitter circuit, so that it has the supplied signal in the Polarity reverses and thus transistor 973

to be made non-conductive. The capacitor 72 discharges at the relatively slow speed given by the resistors 977 and 979 so that after a predetermined time interval, during which no pilot signal is perceived,

Is the capacitor 72 has discharged so far that the Transistor 741 (Fig. 6) is also blocked. Thereupon the in connection with Fig. 6 explained stereo blocking circuit, the arrangement switched to mono playback

It can be seen that the voltage delay and the time constant delay caused by the discharging of the capacitor 72 the indicator lamp 969 still switched on for a while or the stereo switching transi stör 741 remain switched off for a while, after the pilot signal level is below that initially required for switching to stereo playback The level has fallen

Stereo playback is not interrupted.

If a pilot signal sufficient for dL · stereo reproduction is present, but the signal-to-noise ratio is insufficient for an acceptable stereo reproduction, the following happens: As in connection with FIG. 7th an unacceptable signal-to-noise ratio is indicated by the fact that transistor 845 conducts. When transistor 845 conducts, the voltage at terminal contact Tt (at the base of transistor 927) drops to a relatively low value. The Anklamme tion transistor 921 ensures that the voltage at connection contact 7j only drops to a value that is approximately 1 V _BE less than the voltage at connection contact Ti , so that the correct bias of the pilot signal synchronous detector under these conditions tongues is not disturbed. The transistor 929 becomes kept conductive due to its fixed base bias via resistors 923 and 925, and the Transistor 927 is blocked by the presence of the pilot signal at the output of stereo amplifier 24 under these conditions the voltage at the capacitor 62a does not change. The stereo indicator lamp 969 is therefore switched off and the transistor A blocking signal is fed to 741 so that the arrangement switches to mono reproduction

55, We shall now consider certain relationships that prevail between different parts of the stereo decoder arrangement.

The stereo decoder with the circuit board 22 and the associated external circuit elements

6 * is set up in various ways so that it can work well in the presence of interfering components results in the treated signal mixture and a decision is made against such interference components in favor of the useful signal components. The way in which the Stereo operation is turned off when excessive interference is present has been related with FIGS. 6, 7 and 8 described in detail. the Signal-to-noise ratio detector arrangement according to FIG. 7 and the

if 35 36

s | additional devices according to Fig. 6 and 8 for (determined essentially by the capacitor 76,

Switch between mono and stereo playback using resistor 817 and resistors 821 and 823, P are also set up so that between actual and 'if any) on the order of 20krfc ! ' unacceptable interference conditions and certain work, what an acceptable interference sensitivity for iCi acceptable signal ratios, which results in the interference detector as excessive $. Because of the self-adjustment ρ disturbances could be misinterpreted, the threshold setting elements can also differentiate or regulate them will. elements 821, 823 are omitted, without thereby affecting the tolerances of the other elements of the interference detector yf the composite signal supplied, particularly high-level signals, may be excessively restricted.

W Ie (e.g. repeated timpani or cymbal beats in ic certain other features of the arrangement

H? an orchestral performance), these can contribute to a quiet, interference-free stereo reproduction.

U signals also accompanied by ultrasonic interfering components. The 38 kHz differential channel subcarrier will be like this

| 1 which is the result of overmodulation and which is restored as a result of it being essentially free from

Ip; resulting generation of harmonic distortion spurious modulation components is the same as in conventional

If there are components in the transmitter. It is true- 15 circuits to restore the subcarrier

s | it seems that such harmonic noise components occur in by the signals with a bandwidth of

Vi fall the frequency band on which the interference detector can pass at least 1–2 kHz.

II (Fig. 7) responds This interference detector is therefore typically included arrangements for doubling νϋΐ set up that it automatically the acceptable pin of the pilot signal a matched 19 kHz band-K level of ultrasonic components (ζ. B. in the vicinity of 20 pass-circle , two or more frequency doubler equiv of 114 kHz) changes and thereby the current straightener and a tuned 381 Hz bandpass circuit. ! '■} ■ Stereo reproduction of such high-level signals including those restored in such an arrangement '. . ' in the presence of a relatively high ultra-38 kHz subcarrier, the sound level is maintained by AM interfering components ij A noise detector whose i contaminates the, if it is in the audio frequency range or j; Response thresholds under such signal ratios 25 are in the vicinity of which, after the demodulation, an audible 'remains fixed, could undesirably cause switching noises in the loudspeakers. Furthermore is

effect on mono operation. the restored subcarrier in such a case

', - · The automatic disturbance threshold setting takes place arrangement with FM and PM disturbance components

in the circuit according to FIG. 7 by the special one which cleans the stereo separation of the demodulated Switching of transistors 801, 803, 807, 809, 811 and 30 affect sound signals.

^: 813. And work if normal level or While part of the undesired Störkomponen-

'; relatively low composite signals from th in the subcarrier recovery channel by Veren stereo amplifiers 24 to the current source transistors according to the bandwidth of the matched bandpasses 801 and 803 are supplied, the switch transistors can be eliminated, exists because of the phase temp-807, 809, 811 and 813 as synchronous detectors under 35 sensitivity of a narrowband filter in practice one Generation of an output signal at resistor 817, lower limit of this bandwidth. That is, if the which is reduced relatively linearly to the 114 kHz component bandwidth of the channel, the th of the composite signal is related to In resistor 817 the rate of change of the phase error in dependent flows a relatively constant quiescent direct current. of the deviation from the center frequency In the case of high-amplitude signal mixtures, on the other hand, the bandpass becomes 40. A relatively minor offense of transistors 801 and 803 in the blocked mode of a narrowband channel therefore produces one State controlled during the other of these transi- relatively large errors in the phase of the disturb in the highly conductive state is controlled. restored subcarrier, reducing the stereo dies arises due to the common connection disconnection is impaired. Furthermore have narrow bands Emitter of transistors 801 and 803 to the 45 digits subcarrier recovery circuit in general-resistor 805. Under these prerequisites an asymmetrical bandpass characteristic is in my opinion, the Resistor 817 a DC component also produces subcarrier phase changes and a verdict is greater than the normal quiescent DC compo- sition of stereo separation in the presence of interference nent. In the event of sustained high-level signal mixtures. Oscillators that can be activated by entering the therefore increases the DC voltage at the resistor so separated pilot signal is dragged or synchronized. and the resulting reference voltage are condensed, also tend to interfere with their sator 76 humbles itself. The level of the demodulated output oscillation, as it is sufficiently rigid Interference components that are required to phase synchronize the input of a signal Talking threshold of the transistors 829, 827 to excessive amount required is the oscillator gen, increases as a result. So with a high level 55 there cannot be enough of Störmodulationskomporen-signal mixes the acceptable level can be decoupled from the composting of the pilot signal in order to components automatically increased by 114 kHz prevent these components from affecting the output signal.

One can also say that the interference detector modulates phase and amplitude in nal.
Desirably with weak signal modules - With the present arrangement, a 38 kHz

tion is more sensitive to disturbances than with a strong switching oscillation or a regenerated subcarrier Signal modulation. by frequency division of the output oscillation of the

Due to this self-regulation of the disturbance detector for the oscillator 26 generated by the phase transmitter 36 high and low level signals and the interference amplitude (Fig. 5) in a fixed temporal relationship to the received compression rfor which is held in connection with a pilot signal. A characteristic of this P i g. 7 described interference pulse stretcher can be an arrangement of the oscillator 26 and the phase detector larger demodulation bandwidth for the interference detector 36 is that the oscillator 26 essentially as it would be practical without thei2 features. insensitive to amplitude, phase or Fre-Typically one can with a bandwidth frequency modulation of the pilot signal by Störkomponen-

ten is in or near the audible spectrum. The 38 kHz auxiliary switching carrier, which is derived from the output signal of the oscillator 26 is obtained, is therefore also free of such undesired interference components.

This is because of the synchronous 90 ° phase relationship between the received pilot signal and the 19 kHz reference switching oscillation supplied to the phase detector 36, the control output voltage of the detector 36 is essentially free of interference-related Fluctuations in the amplitude of the pilot signal. The phases (as well as the amplitudes) of the output oscillation of the Oscillator 26 and the generated 38 kHz switching oscillations are therefore both free from the effects such interfering components.

With regard to interference-induced frequency and phase modulation components of the pilot signal, the bandwidth of the phase detector 36, which is determined by AC filter elements rather than by tuned circles is correct. can be made extremely small (on the order of 10-20Hz) while the feedback loop gain of the AFPR circuit is so is dimensioned that it is sufficient to bring about the phase and frequency synchronization of the oscillator 26 and maintain. In this case the interference-induced phase and frequency modulation components of the pilot signal through the switch transistors of the phase detector 36, but are almost completely removed from the AFPR signal by the narrow-band /? C filter at the output of the phase detector 36 removed. Through this filtering, the oscillator 26 (and consequently the generated 38 kHz switching oscillation) of the audio-frequency phase and frequency modulation components that make up the pilot signal in presence accompanied by interference in the received signal, decoupled.

The scheme of synchronizing an oscillator with the help of a narrow-band AFPR detector and thereby obtaining a narrow-band subcarrier recovery system can also be used in other Realize form. A narrow-band subcarrier recovery system eliminates the interference in recovered stereo signals when receiving weak signals. An oscillator with a Center frequency of 19 kHz can match that of 19 kHz

ι «synchronous output signal of the phase detector are automatically phase and frequency controlled, and The 38 kHz subcarrier for the synchronous detector of the stereo auxiliary channel can be obtained by doubling the frequency of its output oscillation. In In this case, the frequency doubler is a frequency converter arrangement, which is the subcarrier input of the Synchronous detector for the stereo auxiliary channel couples with the 19 kHz oscillator, and the input auxiliary carrier of the AFPR synchronous detector is from the 19kHz oscil lator supplied by yourself. The expression »frequency conversion zer «here denotes either a frequency multiplier or a frequency divider, and the frequency converter can have an output which supplies a signal that compared to the input signal is not in the

Frequency is changed.

While above the invention in its application to a complete stereo decoder arrangement has been explained, various of the described subunits of the arrangement can also be used with advantage use separately or individually. Furthermore, z. B. all coils or inductances are omitted, by using a different type of oscillator.

A composite signal amplifier, disturbance detector and a mastrix amplifier are in DE-OS 20 63 637, 20 63 524 and 20 63 729.

In addition 8 sheets of drawings

Claims (4)

Claims: third synchronous detector (68) is fed, which is also coupled to the signal source (24) and 1. Decoder for generating decoded signals from the multiplex signal mixture accompanying, with a multiplex signal mixture, the at least the fourth reference oscillation frequency-synchronous a pilot tone and a modulated suppressed 5 demodulation components that derive a Contains carrier of twice the pilot tone frequency, high-frequency interference in the signal mixture ent with a synchronizable oscillator as well as a speak. Phase locked loop for this having a 6th decoder according to claim 4 or 5, characterized Contains phase detector, which is characterized from the multiplex that the second synchronous detector Signal mixture and one from the oscillator speed to (60) control signals for switching off the first Generation derived signal a control signal for the synchronous detector (40) via a blocking circuit Phase lock generated, and with a first (70) supplies Synchronous detector to which the multiplex Signalge mix from one signal source and also one from the first reference 15 derived from the oscillator oscillation oscillation to generate a demodulation product is supplied, thereby marked- The invention is based on a decoder as it is in the draws that the oscillator signal of a Fre- preamble of claim 1 is assumed to be known Sequence divider circuit (28,30,34) for generating and in the IRE Transactions on Broadcast and first and second reference oscillation trains - 20 Television Receivers, Volume BTR-7, July 1961, No. 2, p. 67 leads, the second of which is half as high a frequency up to 72 is described like the first one and the phase detector (36) decoder for Muitipiex signal mixes that have a is supplied, which contains from this and the pilot tone him, are also from DE-AS 12 55 140 supplied multiplex signal mixture, which contains the and the US-PS 31 33 993 known pilot tone, the control signal generated which 25 According to the currently In the USA common deviations from a predetermined phase norm for stereophonic FM broadcasting and frequency relationship between the second reproduces a main carrier with the sum of two stereophonic reference oscillation and the pilot tone and linked audio frequency signals, namely the left side input of the oscillator (26) for adjustment gnals (L) and the right signal (R), frequency-modulated such deviations is supplied. 30 being the main carrier for compatible reception 2. Decoder according to claim 1, characterized with either monophonic or stereophonic FM-characterized in that the phase detector (36) is set up with a receiver or Ts) zar delivery of anti-phase suppressed, with the difference (L - R) of the two signals of the same amplitude, » λ low-pass filter with 35 stereophonically linked audio signals amplitude, two inputs and synchronous switch (651,653,657, modulated subcarrier as well as a pilot signal to 659) which for Generation of the control- Use in the demodulation of the suppressed signal the low-pass filter inputs are modulated with each half-cycle subcarrier in the receiver, for which purpose in some cases the first reference oscillation is alternately connected to another, with a commercial background, to the two amplifier outputs (Fig. 1 40 basic music (SCA) frequency modulated subcarrier and 6). comes 3. Decoder according to claim 1 or 2, characterized. In a conventional FM stereo receiver it is characterized that the frequency divider circuit at the output of an FM detector or frequency discrete first and a second frequency divider (30 minators the signal mixture from the summed audio signal or 34) for deriving the first and second 45 components (L + R ), which can be used either in mono or in reference oscillation contains stereo receivers and one 4. Decoder according to claim 3, characterized in the frequency range of z. B. 0 includes and 15 000 Hz, a characterized in that the frequency divider circuit includes a 19 kHz pilot signal and sidebands of a suppressive third frequency divider (58) for providing a th 38 kHz subcarrier, in soft, the difference signal third reference oscillation whose Grundwel- contains _as component (L - R) and which encompass a frequency range of 90 ° to the fundamental wave of the second range from 23 to 53 kHz, generated The reference oscillation is shifted and a two-signal mixture can also be supplied with a background synchronous detector (60), the music ( SCA) frequency-modulated 67 kHz subcarrier is also coupled to the signal source (24) and contains its sidebands, for example, from 59 to from the multiplex signal mixture with the third 55-75 kHz. This commercial component reference oscillation of frequency-synchronous demodulators is generally derived in home receivers with functional components, and that the second aid removes it from matched filter circuits. Synchronous detector (60) provides control signals for a switch (973, 955) to reproduce the stereophonic sound programs, which with a reception in the home receiver is the 19 kHz pilot signal type indicator (64, 969) and an energy source to μ homely from the rest of the signal mixture with the help of a Circuit is interconnected (Fig. 1 further matched filter circuits removed and es and 9). becomes one in phase on the 19 kHz pilot signal ϊ'ί 5. Decoder according to claim 4, characterized by a 38 kHz carrier for demodulation ί; 'ί; draws that the frequency divider circuit at one in the sidebands of the suppressed subcarrier || Output (from 28) generates a fourth reference oscillation 65 plugging difference signal information. For the ψ supplies whose fundamental wave is above that of the strong generation of the 38 kHz carrier and its union jjf components of the composite multiplex signal with the difference signal information become common fe! taken frequency band is and a different inductive elements (coils and / or