DE2061576A1 - Storage arrangement - Google Patents

Description

IBM Germany Internationale Büro-Maschinen Gesellschaft mbH

Applicant:

Official file number: applicant's file number!

Boeblingen, December 8, 1970 lw-rz

International Business Machines Corporation, Armonk, NY 10504 New application
Docket SA 967 112

Storage arrangement

The invention relates to a memory arrangement with a Large capacity main storage, small capacity high-speed storage and facilities for transferring Data between the memories, as well as another memory to store marks for each stored in the quick memory addressable data unit.

With such a memory arrangement, the processing speed of a data processing system is considerably increased in that memory access only ever has to be carried out to the high-speed memory, which has a short access time. This advantage of the shorter access time of the high-speed memory is offset by the disadvantage that data transfer from the main memory to the high-speed memory may be necessary in order to provide the necessary data in the high-speed memory, but overall the above-mentioned advantage predominates. The storage requirements for high-speed memory can come len Ausgangskanä- it from different institutions of the data processing system, such as the central processing unit, or input /. Devices must therefore be provided which allow requirements from different entrances to be taken into account.

A device of the type described above is in the German

109827/1394

see laid-open specification 1,815,234. The requirements facilities are forwarded to it, which are common to all entry routes. This can often cause delays arise from the fact that several requirements have arrived at the same time, but only one of them can be dealt with.

A memory arrangement with a main memory and a peripheral one Memory is described in U.S. Patent 3,449,724. There is a common priority circuit in this facility provided, which of several requests received at the same time is the one with a specified highest priority selects. The request information is stored in the device described in a register stack, for each Request a register is provided. Provided that there is access to the memory for a specific requirement is, the relevant request information is transferred to a further register stack. Through the aforementioned priority circuit In this facility too, waiting times arise from the fact that several requests arrive at the same time only a single one is admitted to the system. On the other hand, the main memory is in the memory arrangement described divided into several basic memory modules. Requirements that relate to different modules could well be carried out at the same time if the necessary control devices were provided.

The invention is therefore based on the object of a memory arrangement to create, which has a request branch for each memory request source.

This object is achieved according to the invention by a plurality of memory request gates, with devices for storing the requests being provided for each request gate, by priority devices for assigning the priority, which receive the request information and with memory solvers, which priority conflicts of several requests

Docket SA 967 I _{12 1og827 / l394}

_ ο _β

to solve the same data unit of a memory connected are.

Since separate storage devices are provided for storing the request information for each request branch, a preliminary check of the requests for certain Constraints take place largely simultaneously. The memory solver devices ensure that always only one request, namely the one with the highest priority, receives access to the relevant storage device. There in the case of an access to the high-speed memory, in addition to the high-speed memory, the mark memory must always be addressed These memory solvers for the quick storage and for the brand storage also work largely at the same time.

Furthermore, a request branch for input / output channels are provided. This means that the usual channel buffers can be used. Through the memory solver, which for both quick storage and brand storage are provided, a flexible priority arrangement is achieved.

According to an advantageous further development of the invention, register stacks are used as devices for storing the requirements provided, which in addition to the actual requirement information |

mations also store a control word which can be used at any time The progress of the handling of the request.

The control word mentioned in connection with the Acceptance register stacks described above in U.S. Patent 3,449,724 are omitted. The control word also offers a advantageous way of storing a variety of other necessary control information, such as information relating to the order in which multiple requests must be made to the same data unit.

Further advantageous developments of the invention are the D. ** «1 * 67 112 _{1098? 7 /}

- 4 remaining subclaims can be found.

The invention will now be based on what is shown in the figures Ausführungsbelspieles are described in more detail. Show it:

Fig. 1 is a block diagram of the embodiment,

Figs. Ia-Ic the work cycle in the form of a flow chart the device according to Fig. 1,

Figs. 2a-2h is a split block diagram of the facility ™ according to Fig. 1,

3a is a timing diagram of a retrieval operation; 3b is a timing diagram of a memory operation;

3c shows a timing diagram of a retrieval operation with data exchange between the memories;

FIG. 3d shows a timing diagram of a memory operation with data exchange between the memories, FIG.

fc Fig. 4 shows the subdivision of the main memory and the

High-speed storage in basic storage modules,

5 shows a representation of a data transmission between the memories.

Before starting the description of the exemplary embodiment, some of the examples used in the description should be used at this point Expressions are explained:

Virtual address:

A logical address that uniquely identifies certain data.

Physical address:

An address in the fast memory, which is the virtual address is equivalent to. There is a first and a second physical address for each virtual address.

A memory area that contains 256 words. Each page is divided into 16 lines.

row:

A storage area that contains 16 hoards.

Word;

The addressable storage unit in high-speed storage.

Brand store;

Contains indices (marks) of the rows at this point in time are stored in the quick memory.

Allocation memory:

Contains the indexes of the cells that are currently stored in main memory.

! Address allocation ;

[The conversion of a virtual address in order to the physical. see memory addresses to arrive.

Cell Identifier:

/ The field within a memory location of the mark memory, which j clearly the line indicating what is assigned at the time of these memory portions in the token store * sliding chermafien shows such a field in the allocation memory is clearly a row address in the main memory to which at this time of the relevant memory location in the Allocation memory allocated lit.

Docket SA 967112 10 9 8 277 1 394

Main memory pointer:

The field within a memory location of the allocation memory, which indicates the address of the main storage location where the referenced data is stored.

Fig. 1 shows in a clear form the structure of the embodiment of the present invention.

It can be seen from Fig. 1 that the present embodiment relates generally to two request ports, i.e. input channels for requests. These entrance gates for the Storage requirements are labeled P and Q in FIG. However, the invention is not applicable to two entrance gates of this type limited, but multiple request gates can also be provided.

The source P of memory requests is via bus 1 to the P register stack 3, sequence control generator 5 and P priority device 7 connected. The P register stack 3 can consist of a group of registers and contains the individual requests that have arrived. In addition, in the registers containing the requirements, displays about the The progress of the handling of the memory request is saved. The sequence control generator 5 determines the order in the multiple memory requests must be made to the same memory address. For example, if a fetch and a store request arrive in this order and both requests refer to the same address, then obviously the fetch request must be carried out before the injection request in order to obtain the intended data.

The Q request source is via the manifold 2 with the Q register stack 4, the sequence control generator 5 and the Q priority device 8 connected.

The P priority device 7 is via the collecting line 9 with Docket SA 967 112 10 9 8 2 7/1394

the brand memory solver 11 and via the manifold 13 with the Quick storage solver 15 connected. The Q priority facility 8 is connected to the token memory releaser 11 via the collecting line 10 and connected to the rapid storage release 15 via the collecting line 14. The memory solvers 11 and 15 are mainly composed from blocking AND gates. Since it is assumed that both P and Q have requests to the fast store or the token memory can arrive at the same time, it is the task of the memory solvers 11 and 15 mentioned to resolve the conflicts to solve, which arise from the two requirements for the same data unit. The token memory solver 11 is Via the collecting line 17 with the brand memory 19 and the quick storage release 15 via the collecting line 18 with the Rapid storage 20 connected. There is a 1:! Match between the mark memory 19 and the high-speed memory 20 the physical line addresses.

At the same time as the priority determination within a given request branch (P or Q), the virtual address becomes a Request split into two physical addresses, both for the token memory and for the high-speed memory. If the request is given priority, these two physical addresses become the first and second addresses called, used for this purpose, two storage locations in the token memory and the two corresponding storage locations in the high-speed memory | to address. The tokens from the first and second memory locations in the token memory and the data from the first and second physical addresses in the high-speed memory are sent via bus lines 21, 23 and 22, 24 to the P decision unit 25 or to the Q decision unit 26, whichever The requirements stem from the requirements branch. If there is no conflict, this can be done for both branches at the same time. In the decision-making unit of a particular one A comparison is carried out by logic circuits at input gates between the virtual address of the request and the brand identifier for the fast storage locations. At the same time the data from these two memory dockets SA 967 112

10 9 8 2 7/1394

are read from the quick memory. If one of these comparisons gives a positive result, the relevant Data of the request source made available, provided certain control bits, which are described below will allow such a transfer. If found is that the desired virtual address is not in the high-speed memory and if the relevant control bits are a certain Position, the original request and the content of the token memory parts via the bus 27 and 28 to the R transmission unit 30. This unit 30 controls the data transfer between the main memory and the high-speed memory. In the above case it is necessary to transfer the desired data from the main memory 32 to the high-speed memory 20 in order to be able to make this data available to the request source afterwards. The requirement in question in the request register stack is via the manifold 31 or 33 communicated that the data transfer is taking place and there is currently no further action in relation to it in response to this requirement. The request will only be considered again when the desired data is in the quick storage are located. In the meantime, other memory requirements can be met in the P or Q register stack.

The R transmission unit 30 is via the collecting line 35 with the R priority and splitter 36 connected. This device works in the same way as the one described P and Q devices 7 and 8. It is also similarly via manifold 39 and 41 to the token memory solver 11 and the quick storage solver 15 connected. It can thus be seen that the aforementioned memory solvers 11 and 15 are in conflict solve, which by requests for the same data unit in the mark memory or high-speed memory from the register stacks P or Q or the R transmission unit 30 originate. In the exemplary embodiment described, the source R has the highest priority, this is followed by P and Q has the lowest priority.

Docket SA 967 U2, 09877/1394

The R-transmission unit 30 is via the collecting line 43 with connected to the allocator 45. Between the main memory and the Fast memory is transferred one line of data as a unit. Between a specific one stored in main memory There is no direct relationship between the data page and an index in the allocator. It is therefore necessary to save the main memory line in the Explicitly name allocation memory 45. The allocation store 45 provides an association between the requested virtual address and the physical address in main memory, which the line of data contains what is required by the virtual address. Once the R transmission unit 30 has the virtual address and other related information about the collection point * Receipts 27 and 28, the associative map memory 45 is searched to find the page of data which is in main memory contains the virtual address. The transmission unit 30 then controls the transmission of this data between the main memory and the high-speed memory via the bus 47. As soon as the transmission is finished, the request that triggered this transmission is given the highest priority to keep the data.

The FIGS. Ib and Ic show the Handling of a P request. At the same time as the treatment of a P request, a Q request can also be handled in the same way and the R transmission unit can also carry out a data exchange between the two memories at the same time. If more of these requirements apply to the refer to the same data unit in the fast memory, R has the highest priority, followed by P and Q. The priority becomes in the Brand Storage Solver and the Quick Storage Solver determined and the 'priority sequence transmitted to the specific priority facilities. These give your requirements according to this either priority to access to the brand store or Fast memories gain or hold back the demands.

Xn Flg. Ib it is shown how "in" incoming P-request

SA 9 * 7 IU! 0M2T / 1894

is treated. The request stack 3 is initially after block 3A queried in Fig. Ib. If the P request stack is not empty still has to be checked whether it is full. When it is full, the P-request source is notified of it and offers the request again in a next cycle. When the request stack is neither full nor empty, as by the way 6B, then there are two possible ways to follow up on the handling of the request. The treatment a request is largely determined by control bits, which together with the request in a register of the relevant Requests register stacks are stored. The control bits give, among other things, the age of the request, which is in a specific register. A control bit also indicates whether a request is ready to be determined Parts of the system can be transferred. A control bit indicates, for example, whether a request is suitable for priority establishment to be forwarded, or whether it is in a waiting state and for the completion of a data transmission waits between stores. It can of course also happen that a request stack is neither empty nor full is, however, that no request in the batch is eligible to be transferred to the priority facility. If that is the case is, the incoming P-request can be in a free stack memory location stored and immediately transferred to the priority facility. That way it becomes Waiting on request register stack bridged. This last incoming request goes to the priority device earlier than the other requests already stored in the stack. The request that arrived last goes to the request stacks via the control lines 6 and 12 as shown by line 6A in Fig. Ib. The incoming P request becomes the P register at the same time to the sequential control generator and to the P-priority device.

If, however, there is a request in the register stack, DOOtat SA «7 112

■ "■■." Tl '!!! "'! 1 u" "" '

- 11 -

which are transmitted to the priority facility at this time it is not necessary that the incoming request be transmitted directly to the priority facility will. The incoming request then only becomes a register stack and transmitted to the sequence control generator as shown by block 5C.

The next step can be seen from the block 5D and consists in that a blocking information for the incoming request is produced. Address locking information is necessary because the memory requests are not always in order in which they are accepted by the system. "A problem arises when on-demand store requests refer to the same memory word and the requirements are also located in the register stacks. If e.g. a store request for a specific word arrives before a retrieval request, the store must be stored before the readout of the data, otherwise the wrong data would be read out. The same applies to a retrieval request for a certain word that is waiting in the register stack and a storage request for this word, which arrives later in the stack. In this case the readout must done before saving the new data. If there are two storage requests for the same word, | these two requests are executed in the order in which they arrived in order to be in the specific location to have the right data available at all times. The blocking information, which relates to the order of the necessary Execution of the requirements is referred to together with the associated requirement in the relevant register of a stack. This lock information consists of a lock word which is used for each register in the stack Bit contains. Depending on the value of this bit, it can be determined for a specific request whether this request is linked to another requirement. A request can only be carried out when all bits in the lock word

Docket SA 967 112 10 9 8 2 7/1394

have been postponed. In this way it is ensured that only all other requirements which are related to the relevant Requirement are linked and must be executed first and are actually executed before the request in question can be executed.

While the lock word is being generated by the sequence control generator, an available request can already be made from the P register stack be directed to the priority facility. This is illustrated by block 7A in Fig. Ib. At the same time as the allocation the priority of this request, the virtual address of the request is divided into two physical addresses.

If there is no request in the P register stack ready for the Priority facility to be directed like through the line 6A is shown in Fig. Ib, then the incoming request quasi bypassed the register stack and fed directly to the P priority device and the sequential control generator. In addition, however, the request must also be stored in a register of the stack. This is illustrated by block 5A in FIG Fig. Ib shown. At the same time, the blocking information for this request is generated (5B, Fig. Ib). It is important, note the difference between blocks 5B and 5D in Fig. Ib. If the incoming request does not pass the register stack to the priority facility, then the Blocking information is generated before the incoming request is finally routed to the priority facility. This is shown in Figure 5d. The blocking information then possibly prevents the incoming request from going directly to priority facility is managed. If, however, on the other hand, the incoming request virtually bypasses the register stack directly is directed to the priority device (5A, Fig. Ib), then the request applies for priority regardless of whether a link, i.e. a lock, would have to exist with other requirements. The relevant revocation information for this request is only activated at the same time as the transfer to the Priori-Docket SA 967 112 1 0 9 8 2 7/1 3 9 A

ity facility generated. If locking information needs to be entered for this request, the relevant bits are set in the register in which the request was stored in the stack. At this point the However, the request can already be made in the priority facility that is not to be stopped or transferred back, but is already transferred to the decision units 25 and 26. At this point, however, the request is checked and it it is determined whether blocking information was later entered in the register stack for this request, which bypassed the stack. If so, then the request will declared invalid and has to be done at a later date transmitted once to the priority facility.

As shown in block 7C (Fig. 1c), it is necessary to resolve data and brand conflicts. If, for example, there is an R request and a P request for the same data word at the same time, the R request is given priority. The solution _: this priority conflict can take place for the data from the high-speed memory and the tokens from the token memory at different times, ie in different cycles. For example, it may only be necessary that the R transmission unit informa; tion must be stored in the token memory at the end of a data transfer. In this case, the R transmission unit 30 is given priority for the token memory access and not for the string memory access. In a certain machine cycle, a request can be given priority for \ the mark store but for the fast store ». In the next cycle, the P request therefore tries to get more priority for the facility that was first denied.

Nominal di · P-A * requirement priority for both the data and for brands is dl · in two physical addresses divided virtual · address xu * mark memory and rapid storage via ftassMlleltuagen 9 and 13 carry · ». ' The do -

Boetat .X NT 113 _108827/139 4

Read marks and data are transmitted to the P decision unit 25 via the bus lines 21 and 22. This is in Block 25A shown in Figure Ic. The decision-making unit determines then (25B, Fig. Ic) whether the desired virtual address is either the first or second physical address in the fast store is equivalent to. For this purpose, the brands that correspond to the first and the second * physical address in the Fast memories correspond to, read out and the virtual address which is located in these marks is matched with the virtual Address of the request compared. If the data corresponding to the desired virtual address is in one of these two physical addresses of the high-speed memory are located, then the lock word is examined for the relevant request. If a lock is stored for this request, then this is in connection with the case described above happen where the request was routed directly past the register stack to the priority facility, via the bus 31 is the relevant control information in the request, which is at this point in time in the decision unit 25 is entered and in this way prevents the request from being processed further. So this requirement must be routed to the priority facility again at a later point in time. This is in block 3IA in Flg. ic shown.

However, if the requirement is not linked to other requirements, the requirement can be executed. If the request relates to storage, then the data which are to be stored are stored together with the request in the register and can be stored at the desired virtual address in high-speed memories. If, however, the request relates to the reading out of data, then the desired word read out from the high-speed memory is stored within the request information.

In some cases, the device can also send data from the main socket SA 967 112 1098 27/1394

SAD ORIGINAL

memories that are believed to be needed in the near future are transferred to the high-speed memory. The data transfer between the memories described so far only relates to the case that data from the high-speed memory was required which is still in the main memory and therefore has to be transferred * to the high-speed memory first. However, when there is a high possibility that certain data will be needed in the near future, a so-called advance transmission is carried out. This probability is given when a request relates to the first word of the 16 words of a data line. A check is then whether the data line is similar to the next higher address is already in fast memory. If this is not the case / an advance data transfer is carried out from the main memory to the high-speed memory. This advance transmission is represented by block 29 in Fig. Ic. To carry out this advance transfer, a request for a slip for the data line with the next higher address is stored in the P register stack. This bill request will then trigger a data transfer from the main memory to the high-speed memory.

If the data with the desired virtual address is not in the fast storage, i.e. in neither of the two physical addresses which of the virtual address of the request then a data transfer between the memories is also triggered (30B, FIG. 1c). As already described, the desired data is found in the main memory via the allocator memory 45. With the help becomes the virtual address of the received memory request the main memory address is determined in which the desired data is stored, and this data is then used for the Transfer quick storage. In the decision units 25 and 26 facilities are provided by means of which established it can be determined which storage locations in the high-speed storage are best suited to receive the new data to be received. These facilities also make a choice between the first and second physical address, which the data

1098 27/1394

- 16 lines of the virtual address should be included.

During the exchange of data between the memories, the trademark registration is checked £ ÜR the selected address. A bit of the brand word, which is stored in a memory location in the brand memory, indicates whether the content of this data line has been changed. If this was not the case, this means that the same entry as in the high-speed memory is also in the main memory. In this case, it is permitted that the data belonging to the desired virtual address overwrite the data stored in the selected physical address. However, if the relevant bit indicates that the data in the selected physical address has been changed, then the data must first be brought into the main memory, since it is necessary that a valid storage of each data word is available somewhere in the memory system at all times. After this transfer back to the main memory, the desired data transfer of the data belonging to the virtual request address from the main memory to the selected physical address of the high-speed memory can take place. After this data transfer has ended, the request that triggered this data transfer can be transferred to the priority facilities. This is shown in Fig. 1c by the line 30D. This requirement then applies again for priority (30E, FIG. 1c). In the subsequent test (25B, FIG. Ic), the device thus indicates that the data belonging to this virtual address are now in the high-speed memory and path 25C (FIG. Ic) is taken.

Exact description

A detailed block diagram of the memory arrangement according to the invention is shown in FIGS. 2a to 2h. In FIGS. 2a and 2b the P and Q request entry ports are 4 290 and 4292 shown, over these goals can e.g. requirements of two different Data processing systems or are received by two devices of the same data processing system. With several

Docket SA 967 112 10 9 8 2 7/1394

Entrance gates are of course also all combinations possible The P-entrance gate is via the manifold 3000 with the

! P-register stack 4000 and the Q-entrance gate over the manifold 3001 connected to the Q register stack 4001. Both stacks are via the bus lines 3022 and 3023 with the sequential control generator

] , rator 4OO2 connected. The P input gate and the P register stack

• are also with the P-priority and splitter facility 4004 connected, while the Q gate and the Q register stack are connected to the

; Q priority and splitter 4005 are connected.

; The mentioned priority facilities as well as the R priority device 4018 for data transfer between the main memory

MS and the quick storage HS are with the quick storage solver

j 4006 and connected to the token memory solver 4008. the ; named memory solvers are with the P, Q and R Schnellspei cells 4010, 4011 and 4024 connected. The brand memory solver

:. 4008 is associated with the P, Q, and R mark memory cells 4012, 4013

\ and 4026 connected. Said rake memory cells contain control information for controlling gates for access to the mark memory. This access takes place via the buffer 4308. The lines mentioned contain facilities for time control,

; or delay, the addressing of the mark memory and the subsequent control of the P, Q and R fetch mark registers

^! 4314, 4316 and 4312 allow. Likewise, 1st in the P and

; - ■■. ■■■

j Q fast storage cells of a delay of a fast storage |

j built-in cycle, which is a «synchronization between the j Addressing the high-speed memory 4300 via the high-speed memory -

I buffer 4298 and reading the information into the

j P and Q fetch data registers 4304, 4306 allowed. The R-Schnell-

[Memory cell 4024 works in the same way with the R data [register 4302 together. In addition, the P and Q fast

) Memory cells with the P * and Q decision devices 4014 and 4015 are connected, while the "R quick storage device is connected to the" _ R transfer unit 4016 rsrbun.dsn is. The P and Q call-offs are elt dea P and Q deciding facilities tied together. GUicherMflen is the R-Abruf Msxkenrefister «dt dem Faffsrrsgieter 4034 of the allocation memory 4032, with the R-transfer

DOCket βλ 967 112

109827/1394

transmission unit 4016 and the R priority device 4020 connected. The data required in the allocation memory 4032 are initially read into this memory via a monitoring program. This allocation memory fulfills the function of an index to the data lines stored in the main memory 4294. With The allocation memory can therefore be used to determine which data line in main memory 4294 has which virtual address is equivalent to. Two output registers 4028 and 4030 are provided for allocation memory 4032. From register 4028 is address information available, which relates to new data, i.e. data which is transferred from the main memory to the high-speed memory should be, while from register 4030 address information is available, which refers to old data, i.e. data which is transferred from the high-speed memory back to the main memory be transmitted.

A buffer register 4038 is also provided for the main memory, which contains both access information and the data to be saved. The main memory data cell 4040 receives input information which relates to the configuration in which the desired information from the main memory should be read out. Similar to what was previously described for the other cells, the main memory also contains data cell 4040 Delay devices for synchronizing the reading of data from the fetch data registers 4296. The main memory fetch data registers 4296 are connected to the 4298 fast store buffer registers.

The FIGS. 3a to 3d show the timing of a memory access. It is assumed here that terstap ·! “A requirement is ready to be dealt with. The request director stacks are searched periodically to find the oldest request that is ready to be transmitted to the priority facility. It is expressly pointed out that the handling of requests in both input branches and data transmission between the memories can take place at the same time. This Docket SA 967 112 10 9 8 2 7/1394 _{BAD 0R! G! NAL}

In the present memory arrangement, the temporal overlap of different work processes is indicated by certain control bits and enables the facilities described. To illustrate the mode of operation of the present device, a P requirement referenced.

In Fig. 3a, the timing of a retrieval request is shown. Due to this requirement, data should be called up, i.e. read out, from the high-speed memory. The person in question For this purpose, the P request is transmitted from the request register stack to the P priority device, which is responsible for receiving it Request contains a register. In the priority device, this request competes for the access priority to quick storage and to brand storage. The virtual address is divided into a first and a second physical address and suitable logic circuits determine whether the desired word in the quick memory or the mark memory is also from a higher priority facility is desired. If this is not the case, the polling request is received in the P priority direction the priority to address the high-speed store and brand store. The solution of a possible priority conflict happens in the quick memory solver and the token memory solver (FIGS. 2a and 2b). To address the Memory becomes the relevant physical address from the priority device to the token storage buffer and the fast storage buffer and the information contained in the first and second physical address is read out. Into the P-Schneilspelcher cell and the P-mark memory cell control information is transmitted which indicates in which polling data registers and which polling mark registers the data should be read out. In this device, a comparator is provided, which the brands of the first and compares the second address with the offered virtual address of the request. If one of the two addresses is the same with the virtual address, the data from the retrieval data register made available to the request source.

Docket SA 967 112 1Q9827 / 1 39A

It may be possible that at this point there is one in the brands stored control information must be changed. This need becomes the relevant requirement in the register stack communicated and this request applies again for access priority to the token memory. When given this priority supplemented brand information is stored in the brand memory.

The time sequence when storing data (FIG. 3B) in the high-speed memory is similar to the sequence of a retrieval request. If the save request is given priority, as previously described, transfer the tags of the first and second addresses to the arbitration unit. The brands are in this facility is compared with the virtual address and if they are the same, the request is notified that the relevant Data can be stored in the quick memory. Here, too, there is an indication in the relevant request in the register stack saved when the mark needs to be added. The request then applies for priority a second time. If priority is given to addressing either the high-speed store or the token store, or both, the data to be saved are stored. If it is necessary to supplement the content of a branded memory item, the added trademark saved in trademark memory.

On the other hand, if the line identifier, i.e. line identifier neither the first nor the second address is equal to the virtual address of the current request, then the decision unit determines one of the two physical ones Addresses, and the desired data information is then transferred from the main memory to this address. Fig. 3c shows such a request that a data transfer from Main memory in the high-speed storage brings with it. A control signal is sent from the decision device to the R transmission unit transmitted, which announces that a data exchange is imminent. If the R transmission unit is free, this data transfer can be carried out. It can do this

Docket SA 967 112 _{1098? 7 / l394}

it may be necessary to transfer both data from the high-speed memory to the main memory, as well as * from the main memory to the high-speed memory transfer. The transmission is shown in dashed lines in FIG. 3c. The request in the register stack is then notified of the completion of the data transfer. For this purpose it contains the request for a waiting bit (W), which is reset at time E in FIG. 3c. The requirement applies thereupon priority and can access to fast storage and Got to the brand store. The decision device again compares the marks with the virtual address (F in Fig. 3c). Theoretically it is possible that in the meantime another request for a second data transmission to the addressed one Location in the quick storage has triggered, namely in the time between the completion of the first data transfer and the Comparison operation in the decision unit. For this special case, which occurs only very rarely, there is a special one Treatment of the requirement provided. Normally, after the second comparison (F in Fig. 3c) indicates that the desired data are now stored in the quick memory. This data then becomes the request source read out and the control information of the relevant request is added to the request register stack to enable the used brand information to be supplemented. At time G, the request then applies again for priority. If it is given priority, an access will be granted carried out to the trademark memory and the added trademark information is stored.

3D shows the timing of a memory request with data transfer between the memories. The requirement for storing data is described in the catfish bis treated to the decision device (H, Fig. 3d). If the comparison in the decision device indicates that the desired If the data word is not available in the high-speed memory, the R transmission unit is switched on. After the necessary data transfer is the waiting bit in the relevant

Docket SA 967 112 m0ft!> 7 / 110i

■ 1Q98Z // 1J9 *. BATH ORIGINAL

reset the register of the requirement stack and the requirement is retransmitted to the priority facility. Once the priority has been received, access to the brand memory are executed. The two selected brands are stored in the Decision device compared with the virtual address and it is normally found that the relevant line identifier is the same in one of the two brand information items the virtual address. Control information transferred to the request register stack (J, Fig. 3d) and the Request is retransmitted to the priority facility. If priority is given, the data to be saved can stored and the brand information added.

Theoretically, it is possible that during a request to store data, the desired line of data from the high-speed store is read out by another request after the decision means has indicated that the desired virtual address is in the quick storage {at D in 3b). In this case, however, the memory exchange unit will transmit a signal to the request register stack and determine Reset control bits which, without this reset, would cause the described second transmission of the request to the priority device would have enabled (Dl in Fig. 3b). This ensures that a store request never data at a virtual address that has since been read from the fast memory Decision device that last compared the line designation of the markers can save. The same conditions apply to the stored! 1 of a retrieval request (according to B in Fig. 3a). In either case, the request must begin again and be forwarded to the priority facility after which the decision device will determine that the desired virtual address is not in the quick store is located. Of course, data transfer between the memories is then necessary. The requirement can be based on this can be fulfilled with the normal process.

Dook.t SA 967 112 ₁₀₉₈ 27/1394

BATH ORIGINAL

The mode of operation of the individual in FIGS. 1 and 2 shown Units will now be described in more detail.

As already mentioned, the register stacks for receiving the requirements consist of individual registers. Control bits are also stored in these registers together with the actual request information. The register stacks 4000 and 4001 also contain control devices, primarily for controlling the input and output gates of the register stacks. The task of the register stack is to provide a recording location for each request, as long as it has not yet been carried out, in which information about the progress of the processing of the request can be stored. The status of a request can therefore be read at any time in the relevant register of the batch. A new incoming request is stored in any empty one of the registers of a stack. In the case of a storage process, the request information is usually available first and the data to be stored only follow a short time afterwards. The time difference can be one or more cycles. If there are several storage requests, the order of the requests and the associated data must be adhered to. When data arrives, the control of the input gates of the register stack looks for the oldest storage request, which is still without data, f in the register stack and the incoming data is stored for this request in the relevant register of the stack. The control of the output gates of the register stack looks for the oldest request and sends it to the priority facilities. The order in which the requests arrive is recorded in the control of the request register stack. However, the control of the output gates of the request register stack has the possibility of directing each request to the priority facilities at any time. The request information contains the virtual address, a display about storing or reading out, the destination address of the read out data, the data to be stored and check bits.

Docket SA 967 112 ■ T 0 9 8 7 7 M 3 9 *

th. The register stack is in the control devices display devices are also provided, which can indicate whether the register stack is empty or full. The connection of the individual units of the memory arrangement according to the invention to one another is from FIGS. 2a to 2h can be seen without further ado.

The one from the P register stack 4000 to the P arbitrator 4014 transmitted information consists of the virtual address, an indication of whether it is a storage or readout operation acts, the destination address, the data to be read, an indication of whether the request is linked to others and a Display of whether the request triggered a data transfer between the memories. From the P register stack 4000 to the P priority devices 4004 becomes the virtual address, an indication of whether it is a store * or readout operation is a validity indicator that transmits the data to be stored, various control bits and gate switching signals.

The P-mark cell 4012 controls the reading of the relevant Register of the P request register stack to the decision device.

The P priority facility 4004 is connected to the P register stack 4000. When a request in the priority facility 4004 has received priority, a priority acceptance bit (PX) is set by the priority device in the relevant register of the request register stack, and furthermore also the control bits which indicate that a request is waiting for a data exchange. Also via this connection between Priority establishment and request register stacks become the Lock bits reset in the lock word. This is the case when requirements are linked to which the requirement in question has been executed.

The P decider 4014 is with the P request register stack connected via the 2010 manifold. Lock bits in the lock word of this register of the Docket SA 967 112 109827/139 A

Register stack can be controlled. Furthermore, control bits can be set in each register which indicate / that data or Marks are to be stored and further control bits in each register of the register stack, which indicate whether the named Data or marks are to be stored in the first or second address of the mark or fast memory. In addition, control bits can be used in each Register of the request register stack are set, which indicate the status of the request. Finally, the Address of an advance data transmission and the control information to save this advance address in the relevant Register of the request stack are transferred.

The sequence control generator 4002 is connected to the stacks of requirements registers in order to be able to set the blocking bits of the blocking words in the registers.

The facilities of the Q requirement branch are similar Kind of interconnected like the establishment of the P-request branch.

The control bits stored in the registers of the request register stack will now be discussed in more detail below. Each of the registers of the stack contains a field to hold the virtual address. As already described, a pre-address can also be stored in a register of the stack. Two further bits, F and S, indicate whether the request relates to reading out or storing. In the case of reading out, the relevant F bit is set directly by the request . The F-bit can be reset by the decision device if it is an advance data transmission. The S-BIt is set directly by the request. A Bee timmungsfeld contains the destination address of the data to be read. This field is set directly by the request. Further, a data field for receiving the data einzuspeichernden 1st provided. Since, as I said, these dates only later than the

, 09827/1394

Addresses of the request arrive must be used to store them Data a separate gate circuit can be provided. In each register of the request register stack are the following Control bits stored:

STK V - This bit indicates that there is a request in this register of the stack. This register will called valid and the STK V bit is a valid bit.

SD V - This bit indicates that the data to be saved has arrived are.

W - This is the wait bit and indicates that this request is for data exchange between the memories waiting.

ISI - When data transfer takes place between memories, this bit indicates that the data transfer has been initiated by the request in this register became. The request in this register is given priority over access after the data transfer has ended to get the transmitted data before other requirements for the data word in this address are met can be. If the request that triggered the data transfer has been met, all wait bits are deferred in other requests.

PX - This is the priority acceptance bit and indicates that this request has been given priority.

SI - This is the sequence control bit and indicates that the fulfillment of the request in this register of a particular Order is subject. The requirement is linked to other requirements. If all other requirements which precede the relevant

Docket sä 967 112 109827/1394

Requirement must be carried out are met, the bit in question is reset in this request. For each register in the different Requirement stacking is a specific one in a lock word Bit provided (see IV bit).

D - Memory data bit, is set if priority is given to Storing data was obtained.

T - This is the memory mark bit. When this bit is set, it means that the brand information, which belongs to this requirement, must be changed. When D and T are zero, data transfer is complete.

P - This bit is an indication of the first physical address in the high-speed memory.

A - This is the bit that indicates the second physical address.

CH - This is the change bits. When this bit is set, it means that the desired line of data is in the Quick memory was previously changed. In the meantime, new data has been saved in this line. The | The content of this line is therefore different from the corresponding one Data line in main memory. If the CH bit is at 1, this means that if a data transfer from the main memory to this line of the high-speed memory is necessary, this line to the Main memory must be transferred back at all times to keep the contents of this line of data for future use available. The CH bit is finally transferred to the mark memory.

IT - If this bit is set, it means that access can be obtained for the desired word in the data line of the high-speed memory, since there is currently no

Docket SA 967 112 109827/1394

Data exchange between main memory and this line of the quick storage takes place. This bit can therefore be called a not-in-transmission bit. This too The bit is finally transferred to the token memory.

H - This bit is called the hot bit. This bit is also finally stored in the mark memory. It shows indicates that the desired line of data is being accessed at the present time or shortly before was carried out. This line is therefore "hot". This bit is used when selecting a data line, which should be cleared for the transfer of a data line from the main memory to the high-speed memory, Only "cold" blocks should be overwritten by new data in the fast memory and not blocks in where there are hot words. The hot bit is generated at regular intervals by a cold generator (4022) deferred / the brand address random sequences, e.g. in Generated at intervals of eight cycles.

IV - The sum of these bits results in the lock word in each register of a request register stack. When a Bit in this word is set, this means that the request in which the lock word is stored is linked is with a different requirement, which is defined by the relevant bit in the lock word. It must so there are as many lock bits as there are registers in the request stacks. Only when all lock bits are set to O, the relevant request can be carried out (see SI bit).

Regarding the P * and A bits, it should also be said that these bits are dependent on set by certain bits in the virtual address.

The mode of operation of the sequence control generator 4002 will now be described in more detail. With the help of this generator you should

Docket SA 967 112 10 9 8 2 7/1394

Conflicts are resolved, which arise from the fact that several requests for the same data word in the high-speed memory relate. In order to avoid unnecessary waiting times, requirements are carried out in the device described, so far the data to which the request relates are available. So it can happen that older requests are waiting must and later requirements are carried out first. Four typical cases are discussed in the form of a short table will. A first request arrives at time T and then a second request at time T1.

1 2 3 a 4th a T Save a Read out a Save on computer a Reading out a Tl Read out a Save a Save on computer Reading out

In the first case, the wrong data will be read out if that Reading is done before saving. The same applies to case 2 if the storage takes place before reading out. in the Case 3 an error happens when the two store operations are not executed in the chronological order in which the requests were received. In case 4, however no mistake can happen. In all of the above cases that is, for the requests that have arrived at time T1 Lock bits generated. So the sequential control generator must have the ability have the virtual addresses of all requests that have arrived so far and that have not yet been completed with the virtual address to compare a newly arrived request. For this suitable devices are provided in the sequence control generator. For example, the virtual addresses of all can be used Tent stored requests in turn to the sequence control generator transmitted and compared with the virtual address of the newly arrived request. Every These old addresses, if they are not linked with the new address, become their register with a validity bit retransmitted.

Docket SA 967 112 10 9 8 2 7/1394

The function of the priority devices 4004 and 4005 has already essentially been described. In these priority facilities a series of tests is carried out and, depending on the control signals offered, logical decision signals generated. When asked whether a particular requirement should be given priority, it is also considered whether the quick storage is free. The quick storage is in the present Embodiment in eight Basls storage modules (BSM) divided. Several access operations to the fast storage can be carried out at the same time, as long as they relate to different basic memory modules. This division into several memory modules is taken into account in memory solvers 4006 and 4008. The brand store has yes a structure similar to the quick storage. Priority conflicts can be dealt with in the three priority institutions 4004, 4005 and 4018 take place at the same time. It is also possible that a P and Q request refer to the same But refer to a data line on a different word. In this case it is possible that the requirements are different Basic memory modules can be obtained and run at the same time. The relevant brand information is then transmitted to both the P and Q decision means.

It has already been said that one line of data contains 16 words. The two lines of data in the quick storage into which a virtual Address does not necessarily have to be be adjacent. Each of these two data lines is divided into two parts.

Fig. 4 shows the discussed division of the high-speed memory and the division of the main memory into four basic memory modules. A data line consisting of 16 words is stored in these four modules. When data is transferred from the main memory to the high-speed memory, either the first or second data line is selected in the high-speed memory and transferred to the Docket SA 967 112 10 9 8 2 7/1394

The 16 words are then transferred from the main memory to this line. From Fig. 4 it can also be seen that both the first and the second line in the high-speed memory are divided into two parts. Each part of it consists of eight words. The transfer of a line of data from main memory into the high-speed storage is done in four cycles, A, B _r C and D. For each basic storage module in the main memory is therefore a cycle needed per cycle and four words are transferred. When the data line is transferred to the first line of the high-speed memory, the first eight words are transferred to the address η and the second eight words to the address n + 1. The affected j

Basic memory modules BSM can be seen from FIG. 4.

If, however, the data line is in the second line of the fast memory is transferred, there is a cross-wise exchange when it is saved. The locations for the various 16 words in the second line with the address m and m + 1 result 4. With this type of data transmission between the memories, there is only one transmission cycle in each transmission cycle half of all basic storage modules in the quick storage are occupied. So although the data transmission has priority (R) still remains half of the fast storage is left for other operations. This overlapping of different operations is also made possible due to the special type of storage of the ver | separate data words in the first and second lines of the high-speed memory. Due to the cross-wise exchange, compared to the first line, it is ensured for both data cells in the high-speed memory that that only two basic storage modules have to be addressed by accessing a certain word.

For example, it can be assumed that the basic memory modules O to 3 in the high-speed memory are currently occupied by the data transfer during cycle A. A P request can refer to word 4 in these first and second data lines in the Obtain quick storage. This requirement occupies the basic memory modules 4 and 5, since word 4 is derived from the

Docket SA 967 112 109827 / 1394-

two data cells is read out, overlapping with the two A Q request on word 15 is also possible. By accessing word 15 in the first and second data line in the high-speed memory, modules 6 and 7 are occupied. Despite the implementation of a data transfer from the main memory to the high-speed memory, P and Q requirements are met possible for certain words.

Fig. 5 partly relates to the retransmission of a data line from the high-speed memory to the main memory. If the CH bit for this line is 1, this means that this line is in the main memory must be transferred back. The address in the main memory is determined with the aid of the allocation memory 4032. A new data line is then transferred from the main memory to the cleared data line. The address in main memory the line to be transmitted is also determined by the allocation memory.

Docket SA 967 U2 _{109827 / l39ft}

Claims (18)

PATENT CLAIMS fly memory arrangement with a main memory of large capacity, a high-speed memory of smaller capacity and devices for transferring data between the memories / as well as a further memory for storing marks for each addressable data unit stored in the high-speed memory, characterized by a large number of storage request gates (1, 2 , 4290, 4292), with devices for storing the requests (3, 4, 4000, 4001) being provided for each memory request port, through priority devices (7, 8, 4004, 4005) for assigning the priority, which receive the request information and with memory - Solving (15, 11, 4006, 4008), which solve priority conflicts of several requests to the same data unit of a memory, are connected. 2. Storage arrangement according to claim 1, characterized in that that the devices for storing the requests consist of stacks of registers and, in addition to the request information, also store a control word, which at any time maps the progress of the handling of the request. 3. Storage arrangement according to claim 1, characterized in that that the memory request contains a virtual address which has two lines of data in the high-speed memory (20, 4300) each defined by a so-called physical address. 4. Memory arrangement according to claim 3, characterized by a per se known mark memory (19, 4310), which for each data line in the high-speed memory (20) one the data the brand identifying this line, as well as control information. 5. Memory arrangement according to claim 1, characterized by Docket SA 967 112 109827 / 1.394 a sequence control generator (5, 4002) with comparison devices which recognizes requests for the same data address in the high-speed memory and in the control words of the relevant request stores control information such that the requests are in such an order be carried out that when writing and reading in connection with the same data address always the correct data are addressed. 6. Memory arrangement according to claim 5, characterized by a lock word (IV) which is provided for each total Register in the stacks (3, 4) contains a bit which is set by the sequence control generator (5) if the requirement should be linked to other requirements. 7. Memory arrangement according to claim 6, characterized by a sequence control bit (SI) in the control word, which is reset if the lock word does not contain a set bit. 8. Memory arrangement according to claim 2, characterized by a priority device (4018) for requests for Data transfer, in both directions, between the fast storage and the main storage and through a transmission unit (30, 4016) for controlling the transmission, which sets a wait bit in the control word of the request when the request is to terminate a data transmission waits and is then to be fed back to the priority device. 9. Memory arrangement according to claim 3, characterized by Decision means (25, 26, 4014, 4015) for each port (1, 2) for comparing the virtual address of a request with the label of the two corresponding physical addresses, with facilities for initiating a Docket SA 967 112 109827/1394 Data transmission between the memories in the event of a negative comparison, and with devices for determining Data cells in the high-speed memory (20) that are not used for a long time, into which the new line is then written. 10. Memory arrangement according to claim 8, characterized by Memory cells (4010, 4012, 4011, 4013, 4024, 4026) for each port (1, 2) and the transmission priority circuit (36), for the synchronization of the addressing and the readout operation of the fast or token memory and for controlling the decision devices (25, 26). 11. Memory arrangement according to claim 9, characterized by means for recognizing the address of the first word a data page in main memory and for storing a token request in the request register stack (3) such that a prefetch of the next line of the page is initiated. 12. Memory arrangement according to claim 9, characterized by a Hei B bit, which is stored in the marker memory with each tick and indicates that the relevant data line was recently addressed and by a KaIt generator (4022), which at regular, short intervals statistically selected mark memory addresses are addressed and the Hei S bits reset '... 13. Memory arrangement according to claim 2, characterized in that the priority devices (7, 8, 36) store information in the control word about a successful νβχsuchen access of a request to the fast or .larkenspeicher. 14 * memory arrangement according to claim 13 characterized by Facilities in the requirement register stacks (3, 4), which in each case send the oldest request with rejected priority *> that of the priority eia ^ ichttug "*. 8). 15. Memory arrangement according to claim 14, characterized by Facilities that allow simultaneous processing of requests from different request gates in the Allow decommissioning facilities (25, 26) and priority facilities (7, 8, 36). J.6. Storage arrangement according to Claim 8, characterized in that that the main memory (32) and the high-speed memory (20) consist in a known manner of several basic memory modules (BSM), a line of data from main memory in such a way into each of the two physical addresses of the high-speed memory it is transmitted that in each of the two physical addresses different basic memory modules (BSM) be occupied by a certain word. 17. Memory arrangement according to claim 16, characterized by a bit in the brand information which indicates whether the data content of a line in the high-speed memory 20 was changed, after which this line was only returned before being overwritten is transferred to the main memory (32). 18. Storage arrangement according to one of the preceding claims, characterized in that each of the said devices can be occupied by a request regardless of the occupied status of other facilities, whereby several requests can be processed at the same time and data can also be transmitted during this processing time can be performed between stores. Docket SA 967 112 10 9 8 2 7/1394 Blank page