DE2060454A1 - Adapted filter for the detection of a useful signal contained in an interference signal - Google Patents

Description

Adapted filter for the detection of a useful signal contained in an interference signal

The invention relates to a matched filter for recognizing a digital contained in an interference signal Useful signal that contains a number of memory locations that corresponds to the number of digits in the useful signal Shift register through which the signal to be processed can be shifted with the aid of a clock frequency, one of the adaptation the filter serving programming circuit and a Has summing circuit, at the output of which the degree of over-

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209825 / 09U

2Q6Q454

Tuning of the signal to be processed with that of the programmer circuit input into the filter, to be recognized useful signal indicating signal can be removed.

As from the book Skolnik, "Introduction to Radar Systems", McGraw Hill, 1962, pages 400 to 449, can be found in strong interfering signals or useful signals hidden in the noise either by the known correlation method or can be recognized with the help of so-called matched filters. The known correlation methods require a considerable amount Circuit complexity, since with these a multiplication and subsequent summation of the instantaneous values of the straight received signal with a reference signal representing a reproduction of the signal sought in the interference signal is required is. In the case of a matched filter, on the other hand, the filter is designed in terms of circuitry in such a way that if it is present of the useful signal to be recognized within the strongly disturbed receive signal at the output of the matched filter Signal output with the highest possible peak value compared to the signals that occur in the absence of the useful signal will.

However, are the useful signals to be recognized now subject to frequent changes or are these signals strongly coded signals, a correlator had to be used in spite of the greater complexity in terms of circuitry. The correlator can namely also immediately before the respectively desired signal recognition, the signal to be recognized at the moment Useful signal are supplied as a reference signal, while with an adapted filter for each new useful signal to be recognized the circuit of the filter had to be changed accordingly.

Now a digital, programmable one has already been used for signal detection Proposed matched filter in which the received signal and the one containing the useful signal is disturbed Signal with the help of a shift clock through a shift register

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hind ·, η close is pushed, with the outputs of each space this shift register e.g. in the form of a switch position selected from two possible switch positions programmed so that a certain digital signal is given as a reference signal, whether it is complete or incomplete If within the shift register a summing circuit emits an output signal, the level of which is a Ma3 is for the correspondence with the reference signal.

Although this angepa3te filter can without direct intervention in seiiie circuit to the corresponding switch positions are each adapted to be detected user signal by code, M, however mu3 before the respectively always resolved to be recognized useful signal in that must be performed within the programming circuit individual switch positions or reshaped.

The object of the invention is therefore to provide a new matched filter to create that can be adapted faster and easier than the known filters to a useful signal to be recognized in each case can. The filter should be constructed in such a way that it is switchable according to simple e.g. monolithic processes is to be built.

Starting from an adapted filter of the type mentioned at the beginning Kind is this task according to? the invention solved by φ

since! 3 the programming circuit has a second, corresponding to the first Shift register is in which the useful signal to be recognized is saved, and that in each case corresponding to one another Storage locations of both shift registers are linked to the summing circuit via comparators.

If the programming circuit is designed in the form of a second with the first identically structured shift register

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Relatively complicated digital signals can also be stored directly in this second shift register as a reference signal so that the filter is adapted to a new useful signal to be recognized in a very short time. The link of the two identically structured shift registers is possible via simple comparators, so that the entire filter can be implemented using modern, logical building block technology. According to a preferred circuit implementation the comparators are exclusive-OR elements.

According to a preferred circuit implementation of the matched filter, the summing circuit forms the math matic expression:

/ Anticoncidences x _u , x, '- N —- where

where x-y) is equal to the value of the signal to be processed and x ^ is the same as the value of the useful signal to be recognized and IJ is the same as the maximum number of positions of signals are.

Schalturigsteohnisch has this summing circuit N first Resistors, the inputs of which are each connected to an output of one of the Exclusive-OR gates and their outputs combined are connected to a further resistor, which is connected to a negative voltage that can be adjusted via a potentiometer and corresponds to the number N, and that the connection point between the interconnected first resistors and the further resistor, the output of the summing circuit forms.

The matched filter specified according to the invention and to be implemented in terms of circuitry can be in the form of individual Logic modules z, 3. in monoIythical technology in large Quantities and the smallest dimensions can be manufactured cheaply,

209 825 / 09U

BATH ORIGINAL

2060A5A

so there 3 by connecting the inputs in series and summarizing Filters or digital correlators with any number of digits adapted to the outputs on the summing circuit of these modules N are to be built up.

The invention is based on exemplary embodiments shown in the drawing explained in more detail.

Show in detail:

Figure 1 a programmable digital filter as it was already was suggested.

Figure 2 a according to? digital formed according to the invention programmable filter,

Figure 3 shows a circuit implementation of the in the filter according to the invention provided comparison and summing circuit and

FIG. 4 shows a basic functional diagram to explain the mode of operation of the filter according to the invention.

The filter proposed earlier and shown in FIG. 1 consists of a shift register 1 comprising several storage locations, to which a disturbed input signal x (t) containing the useful signal to be recognized is fed and shifted through the shift register with the aid of a clock frequency f_. Each of the storage locations 11, 12, 13 to In of the shift register 1, which are constructed, for example, as individual flio-flop circuits, has an inverting and a non-inverting output, each of which is led to a programming memory 2 in which the Jev / eilf- one of these provided at (UU ovo "noiciherplatz

209825 / 09U
BATH

206045A

Outputs via switch al, a2, ajü to an with the corresponding Output lines connected to a summing amplifier 3 are performed.

The changeover switches of the programming circuit 2 are now switched in such a way that they are activated when the just to be recognized appears Useful signal in the shift register 1 to all output lines led to the summing circuit 5 is a binary one Emit an L signal. That at the output of the summing circuit Detachable signal y (t) then reaches a maximum value, the α the agreement of all given to the summing circuit 2 Indicating input signals. That is, when this maximum output signal appears at the summing circuit j5 is just the useful signal to be recognized in the shift register available.

The adapted filter shown in Figure 2, designed according to the invention, also has a first shift register 1, the input of which is supplied with a highly disturbed input signal x (t) containing the useful signal to be recognized and is shifted through the shift register _{with the aid of a clock frequency ί φ} . In addition to this first shift register 1, a second shift register 2 is provided, which is constructed exactly like the shift register 1. The useful signal χ _ (t) to be recognized is fed to the shift register 2 as a reference signal and is inserted with the aid of a clock frequency. The contents of corresponding memory locations, e.g. 11 and 21, 12 and 22 etc., are sent to a comparison and summing circuit where the agreement or non-agreement, ie coincidence or anti-coincidence, between the signals contained in the respective memory locations of the two shift registers assigned to one another is determined and follow-up

209825/0914

BATH ORIGINAL

send the number of these coincidences or anti-coincidences is summed up. At the output of the comparison and summing circuit 3 therefore appears a signal y (t) y (t) = ^ coincidences. x, x '- £ ancient incidetices x, x' (2)

Dici-jes signal occurring at the output of the summing circuit 3 Pi t .does itself mathematically, since the sum of all ■ coincidences and the sum of all anticoincidences equal to the digits .- '. hl II the shift register 1 or 2 must be *. Therefore applies

U coincidences = N - Σ anticoinsidences, (3): v> lo "the equation (2) a i in the form

y = (π- ■ £ Antikoin ^ iJenzen) - Σ Antilcoirizideri ^ en (4) y =! • I-ciSi.iit

.icschrieber. will., can. If the imprint (4) is in the following shape

- y - 2 Σ anticoincidences - N

or (5) Σ N

- 2 =. Σ Anticoiticides - ^

imgeschrieben, then the "comparing and summing circuit of Figure 2 will be very simple circuitry formed J5, as this is shown in Figure J.

The individual output lines coming from the associated storage locations of the two shift registers 1 and 2, see FIG. 2, are linked for each storage location pair via an exclusive CDER element 31, 32, 33 to 3n. The outputs of the individual Exclusive-OR-Glieier are each via a first resistor R ₁ , R ₀ , R-, to R on a common Soli- ¹ It punk t to sum, which as an output Au from the Su ::: - ■. • lierschaltunj 3 is brought out. At this switching point

209825 / 09U

2D6045A

there is another resistor FU, its other connection An adjustable negative voltage is applied via a potentiometer P.

According to equation (5), the exclusive-OR elements Jl, ^ 2,33 to ^ n emit a signal when an anticoincidence occurs between two memory locations belonging to one another, with all these signals via the resistors R ₁ , R ₂ , R , until R are summed and a DC voltage corresponding to the number of digits N of the shift registers 1 or 2 is subtracted from this sum voltage via the resistor R ^. At the output Au of the summing circuit 3 there is a maximum negative signal -y (t) when all the memory contents of the memory locations assigned to one another are each anticoincident, i.e. the received signal just stored in shift register 1 does not match the reference signal stored in shift register 2 . If, on the other hand, the received signal stored in shift register 1 coincides with the reference signal stored in shift register 2, i.e. if the useful signal to be recognized is currently present, then the exclusive-OR gates no longer detect a single anticoincidence, i.e. the sum of all anticoincidences within of equation (5) has the value zero. In this case, a maximum positive signal appears at the output Au of the summing circuit 3 ^e in, which exactly corresponds to the amount of the direct voltage given to the summing point via the resistor R ^. If the received signal is severely disturbed, anticoincidences corresponding to the disturbance signal occur. The maximum output signal is therefore smaller than in the undisturbed state. Nevertheless, when the Hutz signal that corresponds to the reference signal is present, there is still a recognizable increase in the output signal.

This mode of operation of the filter adapted according to the invention is shown schematically in FIG. 4, with the shift register 2 a certain binary signal as a reference

20 9 8 25 / 09U

2Ό6045Α

reference signal is stored while through the shift register 1 a received signal containing the useful signal to be recognized as a result of the shift clocks of the clock frequency is pushed through from left to right. In addition to the schematic representation of the two shift registers 1 and 2, the signal that can be taken off at the output Au of the summing circuit J5 is shown on the right, depending on the number of Anticoincidences found between the two shift registers (AK) assumes a certain positive or negative value.

In practical studies of what is created according to the invention With an adapted filter, it was found that the signal detectability in the worst case is only 5 db lower is much more complex in terms of circuitry than one true-amplitude correlator. In the case of signal and noise ratios, those at the input of the matched filter are greater than 6 db, the signal detectability is even considerably better than with comparable correlators. That The adapted filter designed according to the invention is therefore particularly suitable for a filter that is also secured against targeted interference Command transmission and signal detection in location technology, with a further advantage of the invention Filters have the property of real-time evaluation of those contained in noise or in targeted interference signals Is to be called useful signals.

Other possible uses of the matched filter are also more analogue in secret or secure transmission or continuous signals, e.g. speech signals. In such an application, the matched filter is called Demodulator used, whereby only those who can demodulate a received signal that is passed through the digital filter useful signal to be stored as a reference signal.

209825/0914

Claims -lo-

Claims (2)

Claims Adapted filter for the detection of a digital useful signal contained in an interference signal, which has a shift register containing a number of storage locations corresponding to the number of digits in the useful signal, through which the signal to be processed can be shifted with the aid of a clock frequency, a programming circuit used to adapt the filter and a summing circuit has, at the output of a signal indicating the degree of correspondence between the signal to be processed and the useful signal to be recognized entered by the programming circuit in the filter, characterized in that the programming circuit (2) is a second shift register corresponding to the first , in which the useful signal to be recognized (x _rp * »(t)) can be stored, and that corresponding memory locations (e.g. 11,21; 12,22) of both shift registers (1,2) via comparators with the summing circuit (3) are linked. 2. Adapted filter according to claim 1, characterized in that g e k e η η shows that the comparators are exclusive-OR elements (31,32,33-. · 3η). 3 · Matched filter according to claims 1 or 2, characterized in that the summing circuit (3) uses the mathematical expression. » -11- 209825 / 09U -y (t) = 2 / anticoincidences X ₀ ,, χ '- N forms, where x _{v is the} same as the place values of the signal to be processed (x (t)) and X ^ 'is the same as the place values of the useful signal to be recognized (x ■ -, (t)). Matched filter according to Claim 3, characterized in that the summing circuit (3) has N first resistors (R ,, Rp, R ^ ... R), the inputs of which each have an output of one of the exclusive OR elements (51 * 32, 33 * first resistors (R,) .. R) and the further resistor (R ^,) forms the output (Au) of the summing circuit (3). aO9825 / O9U