DE2042596A1 - Circuit arrangement for converting a single coded input character into a plurality of coded output characters - Google Patents

Description

Patent attorneys 27 Aug 1970

Dipl.-Ing. A. OrQnecker _on , ~ _c ο β

Dr. -Ing. H. Kinkeldey L U k I 0 3 D

0r .-%. W. Stackmair
8 Munich 22, Maximilians * 43

The Bunker-Eamo Corporation

Oakbrook North, Oak Brook, Illinois, USA

Circuit arrangement for converting a single coded input character into a plurality of coded output characters

The invention relates to a circuit arrangement for generating a plurality of coded output characters in response to the Receipt of a single input character and in particular one Circuitry for generating a plurality of output characters as a result of the depression of a single key on a keypad.

In most applications where- uses a keypad is used to feed information into a data processing system, character combinations such as words or short Expressions, often on. For example, words like "buy", "sell" and "cancel" can often be used in sales-oriented applications appear. Output or instruction characters, such as "tab", "skip" and the like, may be included in the multiple character string in some applications. In such Use cases, significant working time can be saved, when these words are generated as a result of the depression of a single key, "However, the required change Combination of multiple characters in general in each application and even the required words or other character combinations can deal with in a single use case

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change over time. The number of characters in a sequence also changes within a single application and also from application to application.

Formerly, the creation of multiple characters was by fixed linkage (hard wiring) of the multiple character sequences in the monitoring logic of the system accomplished. A special logic design was therefore required for each application of the system and for each change in the system's multiple string it was also necessary to rewire the logical system to solve.

A problem similar to that discussed above also occurs with use cases where information must be transmitted over lines. If frequently used character combinations are saved as If a single character could be transmitted, there would be significant savings in transmission time and bandwidth obtain. However, a facility must be created which is able to transfer the transmitted characters into the to implement the desired multiple character sequence. Again there is versatility in construction and ease in implementation Changes welcome. - ..'- ..

The invention is now based on the object of a simple circuit arrangement for converting a single coded input character into a plurality of coded output characters, in which the plurality of output characters as a result the depression of a single key on a keypad is generated, which allows the sequence of the output characters easy to modify and the length of the available strings flexibility over a wide range having.

According to the invention, the circuit arrangement for converting a single coded input character into a plurality is coded Output characters identified by a character generator, which is adapted to a predetermined coded output

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sign in response to a selected combination created for him of input bits, a means to at least to apply part of an input character as input bits to the character generator, a counting device, a device, in order to apply the output signals of the counter as the remaining input bits to the character generator, a Device which is effective every time an output character from the character generator changes the output signal the counting means is generated and means responsive to a predetermined output signal of the character generator, to stop the generation of characters by the character generator.

If one proceeds in this way, one obtains a circuit arrangement to convert a single coded input character into a plurality of coded output characters. The circuit arrangement includes a character generator which is adapted to a predetermined, coded output character in response to generate a selected combination of input bits applied to its input. There is also a counter device provided, wherein at least a part of an input character to a part of the inputs of the character line generator and the output signal the counter device is applied to the other inputs of the character generator. Every time by the character generator an output signal is generated, becomes the output signal of the counter changed. When a predetermined output is obtained from the character generator, generation new character terminated by the character generator.

The already mentioned and other features, special features and advantages of the invention are to be found in the following, more detailed description Preferred embodiments of the invention, which are shown in the figures, can be found. The invention is but not limited to the illustrated embodiments.

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In detail shows

1 shows a schematic block diagram of an embodiment of the invention and

Pig. 2 shows a schematic block diagram after another Embodiment of the invention.

In FIG. 1 it can be seen that an input code on lines 10 is derived from a keypad 12. For the purpose of the following This discussion assumes that the circuit is either working fast enough to allow the generation of the multiple characters can be completed during the normally occurring minimum time that a key is depressed or that the keypad has a lock by which a key is not released until a release signal In this way, signals remain on lines 10 until all required characters are generated have been.

For the illustrated embodiment of the invention it was assumed that seven lines 10 are provided and that the output signal of the keypad 12 is encoded in the seven-bit ASCII code. While a keypad is shown in FIG. 1 for placing signals on lines 10, it will be apparent from the following discussion that ASCII codes may also be placed on those lines from another source such as a transmission line or a radio receiver can be. With such an input, a buffer register may be required to maintain the input code until the multiple character generation process is complete.

The multiple character (MC) flip-flop circuit H is normally in its ZERO state and produces an output signal on line 16 which is given to condition switch 18 to cause signals on lines 10 through lines 20, OR -Gate 22 and lines ? A au flow to in memory; .H-

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to be saved. In this way, input characters on lines 10 as long as the multiple character (MG) flip-flop 14 is in its ZERO state, immediately im Memory 26 saved. These characters can be saved in parallel or converted into serial characters before saving will. The memory 26 can, for example, a normal recording track acting as a delay line a drum or a plate. However, if detector 28 produces an output signal on line 30 indicating that the character code on the lines 10 is one of the special codes, which is in the column or position 6 in the ASOII code shows, then the MC flip-flop circuit 14 is set to its state EIHS. This removes the necessary from the gates 18 Condition whereby it is avoided that the characters on the line 10 are stored in the memory 26 '. the end as a practical matter, a short delay in the circuit before gate 18 may be required in order for the separation process in the circuit 28 and the setting of the flip-flop circuit 14 is completed before the character reaches this gate.

The four of the least _significant: leading S.ignale or row lines of the lines 10 are led to fourth to the entrance of the character generator 32nd The generator 32 may be any type of known circuit capable of receiving encoded input signals on a first selected number of lines and which through the use of matrix combinations of gates, diodes and / or the like are capable of generating a unique one Generate output on a second, selected number of lines. A dead memory (read only memory) can also be used for the generator 32. Since the particular generator used is not a critical part of the present invention, a generator suitable for this purpose will be described later. The other IT inputs of the character generator matrix are the IT output lines of the counter 36. The number of lines 34 and therefore the size of the counter 36 depends on the largest

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Number of characters required in a sequence of output multiple characters. If N equals three, then no more than eight characters are available in an output-side sequence. In general, the number of characters available is the same (2 ^H ).

In operation, the counter 36 is initially set to the counter reading reset to zero. The manner in which this is carried out will be described later. Thus the beginning code is the is placed on the die 32, the line code of the input P characters on the lines 10, including all zeros the lines 34 »This Singangs-Code is made by known coding methods converted into the seven-bit ASCII code for the first character of the desired output signal.

This character, which appears on lines 38, is applied to gates 40 as an information input. Since the MC flip-flop 14 is now in its ONE state, a signal appears on the ONE-side output line 42, thereby making the AND gate 44 partially operational. A signal on the control line will appear at the clock time of the character 46 (enable line), which completely AND gate 44 workplace is w horse power to produce an output signal on line 48 which is applied to the condition gate 40 to the character To cause code on lines 38 to flow through lines 50, OR gate 22 and lines 24 to be stored in memory 26. The signal on line 46 can be derived from memory 26 if it is in the "state in which it can receive a new character. In this way the first character of the desired multiple character sequence is obtained and stored.

The character on lines 38 is also sent to the end of sequence detector 52 created. The detector 52 can, for example, be an AND gate whose input signals are selected in this way are that it has an output signal on the end of sequence line 54

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generated only if the selected pole end code appears on line 38, as does all! Julien. Line 54 is connected to an input of an AND gate 60 through an inverter 56 and a line 58. The ONE-side output line 42 of the MC flip-flop circuit 14 represents a second input of this AND gate, the control line 46 (enable line) being its last input. Thus, UUD "gate 60 is fully capable of producing an output signal on line 62, which signal is applied to step counter 56 when the character code stored in memory is not the end-of-sequence code. This can increase the value of which appears on line 34 _o the matrix 32 is arranged such that the code that appears on the first four of the lines 10 including the grown value on lines 34, in the ASCII code for the second desired characters of the character sequence appearing on lines 38 results.

The sequence of operations described above is then generated with a new character of the desired sequence, each time is repeated when the counter 36 has an increment. It is emphasized that the same output codes as a Result of several different input signals can be generated can. Thus, for the word "rope", the code for the letter "1" is generated both when the counter has an output signal of 2 as well as an output of 3 is generated.

When the last of the characters it is desired to produce is stored in memory 26, the next increment has the Counter to the result that the matrix 32 on the lines generates the end-of-sequence code. According to a preferred embodiment of the invention, this is achieved in that no output from generator 32 is provided for the input code that occurs after the last character of a desired jcOlge has been generated iat. The resulting liull inputs to detector 52 cause a

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Signal on line 54 that is used to set counter 36 to zero and MG flip-flop 14 to its MLL state. If a lockable keypad is used, the signal on line 54 can also be used to unlock (release) the keypad 12. The circuitry is thus deferred in preparation for the next input code storing the sequence end code in the memory 26 are shown. If desired, this may be through the use of 58 h of the line as an additional input to the AND gate be accomplished 44th

The circuit arrangement thus described is able to to store either a single character or a plurality of characters representing an answer to a single code signal on Entrance are. The number of characters that appear in each sequence can be varied within a wide range that of the The size of the counter used depends and individual character strings are also possible. It can also be seen that the generated Multiple character strings can only be changed by changing the character generator matrix 32. Because this matrix ^ can be built on a single printed circuit board, changes in the string will be a relatively simple one Matter. If a ROM character generator is used, changes are made even easier by reprogramming alone of the ROM character generator.

For the illustrative embodiment of the invention, the numbers stored in the memory 26 are used to display on a display device provided with a cathode ray tube (CHT) to monitor. The contents of the memory are transmitted via line 64 to the video code character generator 66 led. This generator can have the same general shape as the generator 32, thereby simplifying the structure and the costs for the whole system are reduced » The video code output from generator 66 is based on the

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Line 68 is fed to the display device 70 for monitoring and repeating the display.

Since the character generator 32 is the most expensive element of the Pig. As shown in the circuit arrangement shown , the cost of a system having multiple inputs can be reduced if this element is shared by a number of keypads. Pig. FIG. 2 shows such a multiple system and also shows a selected configuration for the character generator matrix 32 and the counter 36 in more detail.

In Pig. 2, three key sets 12A-12C are shown, of which each is adapted to generate output signals in a selected code on corresponding output lines, such as ASCII. These output signals are normally via, satter 18, which is in Pig. 1 kind shown, directed to in a memory 26 to be saved. That particular keypad that has access to memory at any given time becomes determined by the input assignment logic 76. This logic receives signals from a master clock system (not shown) and generates output signals on one of three lines labeled 01, 02, 03 to indicate which of the three input keypads has access to memory at the given time.

When a column 6 character is detected in one of the keypads 12, it generates an output signal on the corresponding line 78, which is the corresponding MO flip-flop circuit of the MO plip-plop circuits 14 causes it to be set in its ONE state. This leads to a signal on the corresponding of the three Multiple character lines 42.

The four least significant bits or line bits of the code that appear on a set of lines 10 are on then corresponding gates at the input of a logical assignment

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circuit 80 applied. This circuit "consists of three sets of gates, one for each of the sets of lines 10, with corresponding outputs from each of the sets that are ORed. Each set of gates is represented by a corresponding one of the clock lines G1 to C3 in FIG When a signal appears on an appropriate clock line, the signals on lines 10 are passed through circuit 80 and lines 82 to form a set of inputs to character generator matrix 84.

The character generator matrix 84 is the same as that on the front End of the character generator 66 (Mg. 1), which is used for converting ASCII code into video code. This Circuit accepts the seven-bit ASCII input signals. And generates the corresponding 35-bit video output signals. These 35-bit signals on lines 86 are sent to a second Character encoder 88 is applied which puts these bits, seven bits at a time, in a display device, under control of a clock counter, fades in, in this way, seven bits arrive at the first clock during the time of the clock to the display device, followed by the seven bits of the second clock during the time of clock two and so on, until all five bars of the five seven-character signals have been generated. A code generator of this general Art is described in U.S. Patent No. 3,440,646, entitled "Code Conversion Means," by Ξ.M. Dean, shown. the the following discussion shows how this character generator can be used as the character generator matrix 32.

As indicated above, in addition to the 35 lines 86 as input, the matrix 88 also has five lines 90, from only one of them is leading a signal at any given time. These lines usually indicate the timing of the character that is being generated. In the present invention, they are

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but only used as additional code inputs «, Thus the circuit has three surrogate character clock counters (SSGC) 92, each of which is normally set to have an output on the first of its five output lines 94. The lines 94 are through an evaluation circuit, denoted by SSGC selector 96, connected to the five lines 90 «, Thus, at time C1, lines 94A become lines 90 connected, at time C2 lines 94B are connected and at time G3, lines 94C turn connected

The matrix 84 is adapted to receive seven input signals, only four of which are supplied by lines 82. The remaining three input signals are output lines 98 from the Program counter (SC) selector 100. Selector 100 is one Evaluation circuit that connects one of the three sets of output lines 102 from a program counter 104 to line 98 the control of the allocation logic clock lines connects. All program counters are initially set to zero.

As the matrix 88 produces outputs on its seven output lines 105 at the time of each character, they will Outputs not used as long as one of the multi-character flip-flops 14 is set to its ZERO state. This has its result in a signal on one of the lines 42, which is used as an input signal to a corresponding AND gate 106 is applied. The other inputs to each of the AND gates 106 are the enable line 46 and the corresponding allocation logic clock line. The output lines 108 from AND gates 106 are used to generate the signals on generator matrix output lines 105 in FIG fade in a memory (such as in the memory 76 shown in Pig. 1) and are also used as a jump signal for the Substitute character clock counter (SSCC) used. Thus, during the first character time in which a signal appears on a line 42, the character that is derived from the input code on the Line 82 results, including a rlull code

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all lines 98 including a signal on the first Line 90, through lines 105, a memory memory selection circuit 109 and a line 111 applied to in to be stored in a memory «The substitute character clock counter used SSCC is also given a value added / ax · During the next character time, the character appears that from the same combination of input signals on the lines 86, but resulting from a signal on the second line 90, on the output line of the circuit arrangement. The substitute character clock counter SSCC used again experiences an increase in value. This process continues until the The fifth character of the sequence is generated, at what time the replacement character clock counter SSCC is changed back to its original state and an overflow signal is sent to the corresponding Line 110 appears, which causes the corresponding program counter to experience a value add / axis. Additional Characters can now be generated with a new input signal appearing on lines 98 since the one used Substitute character clock counter SSCC has run through its five states again. This sequence of operations can be two repeated more times until a count of three appears on lines 98. Thus the circuit arrangement is able to use five-feature code as a result of the replacement character

'Clock counter SSCC for each of four possible outputs from the corresponding counter sequence for a sum of twenty possible characters.

After any character has been generated, the character sequence cannot be supplied with any coded output signal from the matrix 88 for the combination of the input signals applied to them on lines 86 and 90 are terminated. the Discovery of this ITull code leads to a signal on the Line 54, which announces the end of the sequence, which is applied to the multi-character plip-flop circuit used reset and to reset the replacement character clock counter SSCC and the program counter SC. The circuit is thus iot

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deferred in preparation for the next input signal and with the general configuration shown in Fig. 1 the invention of allowing characters to flow directly from the keypad to memory.

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Claims (10)

Claims / - \
1J circuit arrangement for converting a single coded input character into a plurality of coded output characters, characterized by a character generator (32, 84, 88) which is adapted to generate a predetermined, coded output character in response to a selected combination of input bits applied to it, means to include at least part of an input character as input bits | to apply to the character generator, a counting device (56), a device to apply the output signals of the counting device as the remaining input bits to the character generator, a device which is effective each time an output character is generated by the character generator for changing the output signal of the counting device and means (32) responsive to a predetermined output of the character generator for terminating the generation of characters by the character generator. 2. Circuit arrangement according to claim 1, characterized « that the counter reading of the counting device (36) increases each time. . takes when an output character is generated. 3. Circuit arrangement according to claim 1 or 2, characterized in that at least two of said counting devices (92A-92C, 104A-104C) are provided, the count of the first of these counting devices (92A-92C) increasing each time an output character is generated and the counter readings of the other counting devices (104A 104C) increase each time an overflow occurs in the previous counting devices (92A - 92C) 109816/1829 4 ·. Circuit arrangement according to at least one of Claims 1-3, characterized in that the coded input character can be derived by pressing a single key on a keypad (12). 5. Circuit arrangement according to at least one of claims 1-4, characterized in that a device is provided which indicates that an input character can represent a plurality of output characters, that a character storage device (26) is provided, that a device ( 18), is provided, the input characters normally forwards directly to the character memory device (26), and in that a device is also provided which is responsive to an output signal of the display device in order to transmit an input character to the converter circuit arrangement and the output signal of the converter circuit. To apply circuitry to the character memory device (26). 6. Circuit arrangement according to at least one of claims 1-5 » characterized in that the input characters are encoded in ASCII code, and that the display device can be excited when a character in a selected column of the ASCII code is applied to the circuit arrangement. 7. Circuit arrangement according to at least one of claims 1-6, characterized in that the character generator has no coded output signal which corresponds to the coded input signal which is applied to the character generator after the last character of a desired sequence has been generated, whereby the predetermined output signal is encoded in a zero code. 10981R / 1829 8. Circuit arrangement according to at least one of claims 1-7 » characterized by a plurality of different sources (12A, 12B, 12C) for the coded input characters, a separate counter arrangement for each of said sources, a device for displaying the input character source , the has at any given time access to the character generator (84, 88) and that to the output signals of the displayed source and the f corresponding to their counter means display means responsive to the display means for said character generator (84,88). 9. Circuit arrangement according to at least one of claims 1-8, characterized in that the character generator consists of two parts, that the counter devices consist of two parts, the first part of the character generator (84) the part of the input characters and the output signal of one of the counter devices (104A, 104B, 104C) and generates an intermediate code as an output signal, and wherein the second of the character generators (88) receives this intermediate code and the output signal of the other part of said counter devices (92A, 92B, 92C) in order to produce the desired coded output character produce. 10. Circuit arrangement according to at least one of claims 1-9 » characterized in that the second counter is a replacement character clock counter (92A, 92B, 92C) whose count increases after each generated character and that the first counter device (1O4A, 1O4B , 1O4C) increases in its count if the substitute character clock counter overflows. 1 0 9 8 1 h / 1: ■; ? 9 Blank page