DE2037730C - Method and circuit arrangement for achieving grid coverage for a color television camera with several image pickup tubes - Google Patents

Description

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730

The same 211, 311 receive the reference level Rl at the megahertz mullivibrator and are used at their second inputs and the level comparators to effect the horizontal grid coverage 212, 312 receive the level R 2 at their second. In practice, these clock pulses would be inputs. All level comparators work in such a way that during a part of a single horizontal Ab the level of the sampling applied to their first inputs is fed to terminal C, this part of the signal forming the "horizontal search line" with the signal applied to their second inputs. Compare according to the dar reference level. Various known positions in Fig. 3, the horizontal raster level comparators are suitable for this function. Coverage is initially carried out and takes place during A type of shahung, which in practice has proven to be satisfactory for this part of the single horizontal scanning, is the so-called differential which is designated with SH , and precisely during rential amplifiers with a high gain. It is this part of the horizontal scanning that within the general concept of the invention not required for horizontal grid coverage, only two reference levels to be used, whether pulses are supplied to terminal C. While the successive horizontal scans function in a satisfactory manner, the order was achieved in that only two reference levels 15 required for vertical raster registration were used, as shown in FIG. 1 and it is such that the reference levels R 1 and Λ 2 are essentially directed that the rising edge of each cycle occurs symmetrically to the "mid gray" level of the pulse when horizontally scanning the video signal [in line (a) of FIG. 2 vertical search line marked MG with 5th V. crosses. The designated] are arranged. The levels "black" 20 memory act in such a way that the digital signals from the and "white" are in line (α) eier F i g. 2 with BL. Level detectors when the rising and WH. designated. The closer the reference levels are scanned at the edge of a clock pulse, with each other, the more frequently the raster the flip-flops are performed at the frequency of the clock registration correction of the camera. Reference pulses are controlled and the output signals are level at 40 and 60% of the "white tip" voltage 95 from the flip-flops Twists give satisfactory results. One will remain until the next clock pulse is received. Sensitivity improvement can be achieved. Fig. 2 shows in line (d) a train of Ab by using additional reference levels which sample clock pulses and in lines (e) and (/) are arranged symmetrically to the level of half the amplitude of the changes in the output signals of the flip video waveform However, this measure flops which receive the waveforms of lines (b) and causes an additional overhead in the (c).

Camera. The level comparators 111, 112, 211, 212, In the preferred embodiment of the invention

311 and 312 provide one or the other of the two binary states which will now be described, namely memories 221 and 222 depending on whether the color video signal is higher or lower depending on the time of components 2 and 3 It is of course possible to have four separate memories as the reference level with which it is used in one and to avoid such parallel operation compared to any particular level comparator, but it has been shown that this will not. A typical color value signal curve which is required and since this would make the device compliant output signals from the two level comparators, 40, this procedure to which these are fed are not preferred in each case. The parallel operation is shown by means of lines (a) to (r) in FIG. 2 shown. Switch 240 executed, which is connected to the terminal

The digital signals from each level comparator men FD- guided pulse train between two to one or the other of four intervals is switched, namely with television memory 121, 122, 221 and 222 supplied. 45 frame rate and in the unit ~ 4 in the frequency These memory elements can be a variety of form divided by four. In a state that connects men, for example, flip-flops from switch 240, level comparators 211 and 212 made by Mullard, type FJJ 131 can be used. the storage elements 221 and 222. In the other to-to terminal C and below as stand, the level comparators 311 and 312 clock pulses designated with C clock pulses are connected to the storage elements 221 and 222. Since the memory elements are supplied to trigger the line and the parallel operation at a quarter of the frame rate image scanning. takes place, it is guaranteed that every signal of a picture

Clock pulses with two pick-up tubes are used one after the other during one odd and one different pulse repetition rates. A straight consecutive image is scanned. Pulse repetition frequency coincides with line frequency 55. Although it is feasible to match the digital signals and to be used by the level comparators during the entire period in which the vertical grid registration is to be scanned, this is normally not to be found out. The fact that in this case the required. Where only a centering of the image is required with the line frequency, the interrogation will coincide for a short time, means that the clock pulse is carried out in 60 periods of the scanning sequence, which is carried out by successive horizontal scans in the pair of search lines occurs near the center of the same position. It is arranged so that those of the image area PA (FIG. 3) are defined as they appear in the rising edge of each of these clock pulses in FIG. 3 at SH as a horizontal abiasi search essential in the center of the image area, and line and at SV as a vertical search line, the part of the sampling frequency which coincides with this, as already described above, rising clock pulse edges, further pairs of search lines (not shown) form the "vertical search line". The other pulse train- can be introduced at appropriate places (e.g. frequency can be given by a free-swinging five- near the four corners of the picture surfaces), if

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it is desirable to allow errors in height, width, linearity, distortion, and twist correct.

The scanned digits appearing at the outputs of the memory elements 121, 122, 221 and 222 are fed as input signals to the two edge detection circuits 130 and 230. The output signals of the storage elements 121 and 122 are supplied to the circuit 130 and those of 221 and 222 are supplied to the detection circuit 230. If four separate memory elements were used instead of the memory elements 221 and 222 operated in parallel, either the switch 240 could be placed between the memory elements and the circuit 230 so that the latter would operate in parallel, or two separate edge detection circuits could be used at the expense of greater complexity can be used in place of the edge detection circuit 230. The edge detection circuits 130 and 230 are designed to detect four types of edges, the term "edge" being used in the application to denote a transition of the video signal between the two reference levels. A more detailed description of the edge detection circuits is given below with reference to FIGS. 5, 6a and 6b. The edge types recognized by the circuits 130 and 230 are shown in FIG. 4, in which the four parts PF, PS, NF and NS each have a fast rising edge, a slow rising edge, a fast falling edge and a slow falling edge illustrate. Lines (a) to (/) of FIG. 4 represent the signal curves. 1 so-called places appear. It can be seen that the illustrated signal curve is the signal curve belonging to component 1. The signal curves belonging to components 2 and 3 would be obtained in exactly the same way in practice. The states of the signals from the memories 121 and 122 shown in lines (e) and (/) in FIG. 4 are denoted by A. E.g. Έ , and it is precisely in this form that the digits are fed to the edge detection circuits as it is in the Fi e. i is represented by suitable designations at the inputs to the edge detection circuit 130. The input signals to the circuit 230, which correspond to the video signal components 2 and 3, are denoted by C -I- E, C + E, D + F, ZJ + F and in Boolean algebra represent the states of the binary digits which are used by the Components 2 or 3 are derived, each corresponding to A, ~ Ä, B, Ή. The four types of edge recognized by the edge recognition circuits are thus shown in FIG. 4 following types:

for PF: a rising transition from B to B and from Ά to A at the same time;

for PS: a rising transition from B to B, ⁶ ^ which occurs one clock pulse earlier than a rising transition from Ά to A;

for NF: a falling transition at the same time from A

to Ά and from B to B; _6s

for NS: a falling transition from A to ~ Ä, which occurs one clock pulse earlier ak a falling transition from B to B.

By only detecting edges of the types mentioned above, it is ensured that the circuit does not respond to low-line information that would cause a delay of more than one sampling clock pulse between "A" and "B" transitions.

According to the illustration in FIG. 1, detected edges cause probe pulses which are passed by the circuits 130 and 230 to a comparator 50. The comparator 50 is designed, as will be described in detail below, to compare edges of the same direction derived from the various camera tube signals. If the occurrence of detected edges in circuits 130 and 230 does not occur simultaneously and if certain other conditions (described below) are met, it is likely that the cause of such non-existent coincidence is a misregistration, and if this is the case, the comparator 15 outputs a misregistration signal of a suitable type. The output signal from the comparator is fed to a further switch 60 which is synchronized with the switch 240 in frequency by a factor of four vertical blanking pulses. Thus, the output from comparator 50 may be directed to correct the misregistration with respect to component 1, component 2, or component 3, depending on which of components 2 and 3 is being compared to component 1 at any one time will. According to the illustration in FIG. 1 the comparator supplies one of eight correction channels VF2, VR1, HF1, HR1, VFX VR3. HF2>, HR3 until the error is corrected. The correction signals are as follows:

VFl = vertical correction forward for component 2.

VRl ■ - \ crtical correction backwards for component 2,

HFl ■■ - horizontal correction forward for component 2.

HRl - horizontal correction backwards for component 2

and similarly for component 3.

The correction signals for the misregistration can can be used to derive waveforms for the scan or alternatively can be used to control a motorized potentiometer assembly which controls the centering controls.

The operating conditions of the comparator 50 are as follows: First, the comparator is arranged so that that it does not try to trigger co-rectification signals to line up edges that are more than two clock pulses apart. This is how it is that fine image details are ignored by the grid coverage correction. Second is the Kompira tor designed in such a way that it only delivers a correction signal if it has a positive and a negative flank « receives in which the error occurs in both in the same direction. This is desirable because it fell has shown in practice that when eii Correction signpi after only one flank zugclassei a malfunction of the circuit is triggered

2 037

9 10

this can, if very close to each other, a not "1" = W ~ XYT "2" -WXYZ

Luminance accompanied by a color signal edge - »3« = WXYZ »4« = WX YT

signal edge and one not of a luminance- ^ ₈ _ ¹ R? XYT "6" = WXY7,

signal edge accompanies color signal edge. ι - w y ~ v 7 a - u / γ ν 7

The introduction of a limitation to a working 5 »/« - w λ r ζ «» « = ~ w χ. γ Δ

wise with two edges reduces the possibility of "9" = WXYT. "10" = WXYT,
such a mistake.

As mentioned above, the flanks- Da are six of the sixteen of those available. Binary-

detection circuits 130 and 230 designed so that codes with four bits each are not used,

that they are the four in FIG. 4 types of 10 shown may include some of the ten encoding types listed above.

Recognize flanks. genes can be uniquely identified without losing all four

Each edge detection circuit has ten bits of coding that are required. Under

different logical states "1" to "10"; the admission of these superfluous bits one obtains the following

Stages »1« to »5« are used to denote the increasing ten codes for the ten states:

lowing flanks PF and PS , and the 15

Stands »6« to »10« are used to denote »1« = W ~ X »6« = WX

to recognize falling edges NF and NS. The "2 .. < -WYZ " 7 " -WYZ

ten states are shown in FIG. 5 together with the ^ * -WYZ »8« = WYZ

corresponding input signals shown, which λ - w W a - w V7

are required to create an existing logical »o ^{>> 4 <<} ~ ^wr ^>·>)« .- WY Δ

State in the next logical state to an- * 5 "= WXYT " 10 "= WXYT
to the. Returns in the absence of a detected edge

the edge detection circuit in one of the. It can be seen that for all states "1" to

initial states »1« or »6«. If the on- »5« the TP condition of the flip-flop »^« and for

successive binary level of the signals from the * 5 all states »6« to »10« the IF requirement requires

Storage elements 121 and 122 (in the case of the alarm clock. If the exciter and control inputs

device 130) are received, cause the need for a bistable level of type D on a high

bare signals that the edge detection circuit are held positive potential, then a

their logical state when the clock input signal occurs, which is sent to the preselection input

impulses C changes which are fed to it. 3 ° is transferred to the output at Q until

If the edge detection circuit is in this way by applying an input signal to the

Initial state "6" takes the edge clear input is reversed and vice versa, therefore

detection circuit to the state »1«, if on, a signal is applied to the extinguishing terminal, if

B-level is received by the storage element, since then the states "1" to "5" are required and a

if an edge is to follow, this is a rising input signal applied to the preselection terminal, if

Flank must be. Subsequently, one or the states »6« to »10« are required

several B signal level inputs result in a transition to The input signal sent to the extinguishing terminal!

the state "2". From Fi g. 4 it can be seen that Ύ ~ Β, and the input lead to the preselection terminal

then, if during the presence of the Iogi output signal is ~ XA, since from the above

see to. ands "2" a /! - condition from the Auf- 4 ° table shows that X is used to

If a PF edge occurs, the logical addition is to identify the states "I" and "6" and that

"5" in FIG. 5 is generated. In alternative A denotes the possibility that a sloping

Way generates the] "Z" condition (i.e., the off-edge occurs and 7 "denotes the possibility that

output signal from memory element 121 is ~ Ä, and that a rising edge occurs.

Output signal from memory element 122 is at the same time 45 The condition for the circuit in a

tig B) a logical state "3", which passes over to the arbitrary state and remains there (other

Representation is to be achieved. This could result in states as “1” and “6 &, in which the circuit

neither a slowly rising edge PS nor a return according to its design, if no

represent useless edge, and a -4-SignalaI- known edge is present), is that the

level is required at the next clock pulse to 5o circuit in the previous one. State is and

to create a transition to state "4" in order to meet the condition for a suitable transition

to confirm the edge PS. The logical state between the states is present. So if everyone

then returns to the state »1« if the state from the table given above starts with the

next clock pulse received a Λ signal level (obtained from FIG. 5) required transition

will. A similar process is combined by the addition 55, so this provides the following conditions

stands »6« to »10« for falling edges. worked.

Line (g) of FIG. 4 shows the states that are created by the edge detection circuit (e.g. 130) during the condition to reach the state

of usable transitions are taken. "2" ^ = WYE + ΨΥΖΉ

The ten states "1" to "10" are intended for ⁶ <>"3" = WYZ ~ ÄB

moderately by using ten of the six- _ "

ten binary codes are shown, which at Ver - WY Δ Α

Turn of four flip flops are available. "5" = TF YZ A The selection of the "7" == W ~ XA + WY ZA used for the ten states Coding is arbitrary. In practice it has proven to be ⁶ 5 «- w ν 7 τ n

The ten following additions have been found to be useful

the four flip-flops * W *, »ΛΓ«, »F«, »Z« would be » ⁹ « = WYZB

use. "10" = WY ΖΈ

11 12

The formulas that provide the keying for the D inputs of the flip-flops "X," Y ", " Z "are obtained from the first table" I "to" 10 ". The selection of states in which X occurs yields:

Substituting the conditions that are required to achieve each of these states yields this:

D _x - = (TF XB -I- WYZB) I WYZ Ά B + WYZA

+ WYZA + (WX A + WY ZA) + WY ZA ~ B + WYZB
= (X + YZ) (WB -I- WA) + Z (WA + WB) VY ZA ~ B

This means that when they are present, which simply provide an inverse function. From-

Equation shown condition at input D _x eventual use of NAND gates results

An output signal X from the flip-flop "<¥" reaches animals in the reverse of the required Boolean

will. If this condition is not met, expressions take place at the inputs of the flip-flops. This is

Flip-flop »Λ '« sets state X on . ao merely a practical economy and affects

In a similar way one obtains: Impaires the validity of the theoretical expressions

not. The real expressions are in the circuit

Dy = "3" -f "4" + "8" + "9" given in the diagram.

WYZ Ά B + WYZA + WYZ Ά B The four flip-flops » W«, »X«, »K«, »Z« are one

+ WY ZB a _5- fold with H ', X, Y, Z and each flip-flop

= 7Z? U-f YZ [WA + WB) ^nat e ^'ne n Vorwähleingang PR, a clear input

CLR, "D" - or clock pulse inputs D and C, sound like outputs Q, ~ Q. Unused inputs are

throughout the circuit to a marked V

O ₇ = "2" + "3" -f- "7" + "8" 30 potential placed. The inputs A and B are from the

(WXB + WY ZB) \ WY ZA ^ B storage elements 121 and 122 taken (in the

+ (WX A + WY ZA) + WY ZTiB Fig. (Sa and fib not shown), and it is from the

= (X + Y Z) (WB + WA) + YZ'AB logic of the circuit can be seen that the required Boolean algebraic expressions to the

It can be seen that the input D _x - to the flip-input “D” of the flip-flops “AT”, “>'”, “Ze auf

Flop »- ¥«, which in this flip-flop requires the characters Γ> _Λ , D _v , D ₇ and at the inputs PR

i ι. to provide an output signal-Jf, the condition and CLR of the flip-flop "W" are available,

lumgen for any of the possible logical edge detection sounds 130 and 230

/ istands required, with the exception of the states "1" generate tactile pulses for the comparator 50. Each

or "6". If an unacceptable edge on - 4 ° detected edge generates two pulses, one of which

'.ritt, if the required input D _{x is} not reached, one is triggered immediately after the other,

because none of the specified conditions for the io- being these pulses special output terminals

uic states »2« to »5« or »7« to »10« can then be fed to switching units 130 and 230. This

occur, and an output sign X is made by the Fiip- inipuke are made by the comparator da / .u,

Mop "-Y" reached. From the table of logical 45 the flange assigned to each of the cannulas I. 2 and 3

States it can be seen that X is used for this. to compare information and to assess

iim to identify the states "1" and "6" and let that generate a suitable correction signal

consequently causing an unacceptable edge that will. The conditions under which the tactile

that the circuit returns to the "1" state and pulses are generated are indicated in FIG.

when the flip-flop "W" is in the state W 5 ° ben, which with the Fi g. 5 matches except that

and returns to state "6" if the flip- added additional states "11" to "18" \ vur-

FIop "W" is in the W state. the. These additional states are provided in such a way that

These equations (i.e. preselect "W", clearing that the outputs are compared to the levels and follow-

"W", D _x , Dy, D _z ) represent the Boolean conditions for the storage elements 121, 122, 221 and 222

gen, which remain unchanged at the inputs of the flip-flops 55 for two further clock pulses.

"W", y> X ", " K "," Z "are required. This means that in the event of a recognized

A device-technical implementation of this incoming flank on / f level for two further clock input pulses must be present in FIGS. Represent levels in a manner similar to an edge detection circuit (signal 6o be present. Thus, in FIG. 8 the evaluation 130; circuit 230 would in practice be the same gear for reaching the states "11" to "H"). The gate circuit is not specified in detail and the states "15" to "18" are written as A and B, since they are directly specified by the above-mentioned the-. The Boolean expressions for the theoretical expressions is derived. Every goal G would stand »! \ " To" 18 "represent the conditions for creating a NAND gate. It can be seen that 65 reaching these states, e.g. For example, for state »11« only inputs A and Έ the input terminals of these the condition that the state »3« is present are applied to the circuit. The signals / Γ and S and that there is a transition A , ie, WYZA. are, however, derived by gates (71 and Eq ., From this it follows:

13 14

Condition for reaching the state c an output signal is generated when coincidence

, _1i4 _ _V7Wi enters. Similar impulses which a recognized edge

· "* Z ν % w α in channel 1 are delayed and with a

»13 * = YZWA ^{ώ £: ηι} delayed edge in channel 2 or 3

^li ei flanks that are not supplied by the flank marks 30 d 230

Wo two flanks that

1 Il -YvZji voltage circuits 130 and 230 are not supplied

J? "I Z id d the required conditions

voltage circuits 130 g

are in deck and meet the required conditions, the Boolean algebraic Aus _{io expresses for the} presence of a for channel 2 The detected edges and their corresponding or 3 required error correction signals such as probe pulses (which follows the states "11" to "18":

correspond) are shown in FIG. 7 for PF, PS, NF and _{N Rev} _ falling edge: backward correction NS shown, where the reference symbols have the same meaning - '' _{16 / a} (28 + 25) + 18 / a (27 + 25)

As can be seen in Fig. 4. As can be seen, 15 ρ _Rev _ _rising edge: Backward correction is the pair of tactile pulses that everyone recognizes- "" γ ^ ΐα (24 -I- 21) + 14 / a ( 23 + 21)

corresponding to the th edge, in the time by one cycle. N-For = falling edge: Forward correction
impulse apart. This goes from the Fi g. 8 ' ^ Ia (17 + 15) + 26 / σ (18 + 15)

from which it can be seen that _{p Fo}} is required . __ indicating edge: forward correction

to go through one more state to the end 20 '' 24 '«' 13 < 11) 1 22 / Yi (14 ⁴ 11)
to reach states "12", "14", "18" and "16",

than it is necessary to get the final states "11", "13", the embodiment of FIG. 9a provides a

»15« and »17« can be reached. Consequently , the keying for these correction signals appearing on the Taslim pulses "12", "14", "16" and "18" with respect to points beginning with N Rev., P.Rev., N.For.,

the key pulses "11", "13", "15" and "17" are delayed. a ₅ P.For. are designated. The intermediate Boolean expressions with “12 / a”, “14 / a”, “16 / a” and “18 / a” are shown in the figure the resulting expressions are derived. 50 are generated and discussed later. As before, the most economical use leads

A practical embodiment of the conditions of NAND gates G to reverse the theoretical ones

"11" to "18" are expressions in the right part of FIGS. 6a and 30. The generation of correction signals is shown at 6b. The circuit shown there corresponds to the points marked with V.Rev. 2, H. Rev. 2, etc. in directly the Boolean expressions which are identified above in Fig. 9b (where the designations are given and the required Boolean expressions, "vertical scanning: backward correction conditions for the probe pulses" 11 "to" 18 " appearance to component 2 «, etc.), is made by means of bistable

on the so-called terminals. Again, 35 stages ZtS is controlled, which as inputs via the can be seen that the use of NAND gates gates GBS one or the other of the signals to a general reversal of the theoretical results. N.Rev., P.Rev., N. For., P. For. along with the pressures has resulted. one or the other of the inputs SV, SH

The key pulses "11" to "8" are received at the.

Inputs “11” to “18” of the circuit shown in 40 The Boolean expressions for the output cords Fi g. 9 a and 9 b are shown, which are the grain reversal signals as follows:
parator SO and switch 60 show. It is appropriate- χ / R> · 2 - (NR] ^{/ λ} (PR V) O

took. that the inputs "11" to "18" from the wV. 7 - (NR H) (PR H) O

Edge detection circuit 130 are derived and '. °', '"_ / κ / ρ ·' y \ rni. ' y \ η

that the corresponding inputs »21« to »28. <of 45 ,, 'J"' ~ '__'_,. ,,. · ', λ (Pi 'H) ή

the edge detection circuit 230 are derived. i / p '"' 1 - Ld 1 / pp 1 / Π

The impulses »12 /«, »14 / a«, »16 / a« and »IS / o«, «ΓΓμβι wmn

11 ■ · ι · 1. -> ■ ι w 1 wi / ι Rev 3 </ v K. ti ι [ι κ. Hi

which respective impulses »12«, »14«, »16 <- and» 18 «■ '- y {tnp · y \ h

are that by a fraction of a clock pulse period 'J' ^u \)., ' ';"'" { -τ «

•. I ι ι ι ι «■ · Ii U For. 3 - (Nl-.H) (Pr.H) Q

are delayed by the input circuit of the 50 ^BC

Comparator 50 generates, in which, for example, NR means N.Rev., PR means P.Rev, NF when the pulse »12 Vx is generated, in that the pulse indicates N.For., PF means P.For., V means a» 12 "sent through a resistor Rd . jjang SV. H means input 5.//. and Q, ~ Q is connected to earth via the capacitor Cd. indicates the effect of switch 60. The practical

The values of 180 ohms and 470 pF for the compo- 55 embodiment of these expressions in Fig. 9b erncnieii Rd and (V have proven in practice to require the use of NAND gates, and the net proved and ran ¹ , a (typical) delay Aiisgimgssignale which are obtained represent the order of about 100 ns · Such delayed pulses are periodic represents in the above expressions, the Einder 1 · "ig 7 (Largest:... llt c'ange SV, SU. occur during the verti

The left side of the fip. 9a and 9b (large- 60 kalen and the horizontal Suchlif'jn on, and si ( The comparator dialing presented here is used because / u are derived from the line synchro and voi to determine when two recognized thanks not the frame sync pulses which in the (not shown) are in cover and whether; a recognized flank in each set) monostatic multivibraloreii.; the K, times 2 or 3 occurs before and after one or by any other suitable one

recognized Hanke in channel 1 aulinit. Impulses which 65 directions. The gates fi / iS 'therefore serve to each: a recognized edge in each channel 2 or 3 dar- the signals N.Rev., P.Rev .. Ν.Ι-'οι :. P.lor. to a place, graze vei / ögeil and compared with one not determined \ on two alternative unstable stages zi zÖL'eiU-n Hanke in channel 1, and it will lead, depending on the riveting de

Ao

vertical search lines or the horizontal search lines. Thus, each of the bistable stages BS receives as an input a signal which is defined by the direction of the compared edge, ie rising or falling, by the direction of the required correction, ie, forwards or backwards and by the direction (line or image) of the scanned Search line. The bistable stages BS are reset individually for each image by means of pulses which are sent to the RBS terminal. The bistable stages are numbered BSI to BSS in FIG. 9b, and it can be seen from the figure that the signals N.Rev. are fed to the bistable stage BSI while the signal SV is present and are fed to the bistable stage BSI while the signal SH is present. Thus, the bistable levels BSI and BSI each have the Boolean expressions NR V and NRH. The other bistable stages BS 3 to BSi are labeled similarly. So that an output signal (e.g. V.Rev. 2, etc.) is only generated when a suitable rising edge and a suitable falling edge occur (but not necessarily in this order), the output signals are

gate BSG controlled by two bistable stages BS. One of the bistable stages that each; Output gate β5G is assigned to a falling edge and is associated with the bistable stage with a rising edge in the same direction (ie, either both forward or both backward). The circuit 60 consists of the terminal 60, the NAND gate BSG and the reverse gate G 60, which is shown in FIG. 9 b is shown. The clamp 60 is with a

ίο third input of each of the output gates BSG connected. The switch 60 is only used to switch the signals N.Rev., P.Rev., N.For., P.For. to feed each of channels 2 or 3 as required.

Since it was assumed that the output signal is always fed to each channel 1 or 3, the input 60 only receives a two-state signal Q or Q, which links BSG for channel 2 and a reverse link G 6 (the output Linking elements BSG of the channel 3. The linking element 60 is synchronized with the switch 24 (as described above).

For this purpose 3 sheets of drawings

Claims (16)

Patent claims: 1. Procedure for achieving grid coverage for a color television camera with multiple image pickup tubes, with correction signals for the Grid coverage can be derived from the individual video signals, characterized in that that from at least two image pickup tubes the correction signals during the playback Video information are formed by deriving comparison signals when the video information is a exceeds predetermined amplitude and a lower or equal rise and / or fall time owns as specified. 2. Circuit arrangement for carrying out the method according to claim 1, characterized in that of at least two image pick-up tubes each at least one level comparison stage (111, 112: 211, 212; 311, 312) at a first input (1, 2, 3) a video signal (a) to be reproduced is supplied during the reproduction period for level monitoring, so that each level comparison stage (111, 112; 211, 212; 311, 312) a _{5 is} supplied with a specifiable reference level from the outside at a second input (R 1, R 2) at the same time, that the level comparison stage ( 111,112; 211, 212; 311,312) emits an output signal (b, c) as soon as the video signal (α) to be reproduced exceeds the reference level, so that each level comparison stage (111,112; 211,212; 311,312) continues to have an edge detector (130, 230) for determining the rise - And / or the fall time of the video signals is connected downstream, that the edge rise and / or fall time determined in the edge detector (130, 230) in a Komperalor (50) with a Predeterminable time is compared and that a raster correction stage (60) is triggered by the comparator (50) at a lower or the same determined time. 3. Circuit arrangement according to claim 2, characterized in that in each case two level comparison stages (111, 112; 211, 212; 311, 312) are connected to an image pick-up tube, to which two different reference levels (Rl, R2) are fed, which one serves as a reference level (MG) serving level of the video signal have predefinable differences. 4. Circuit arrangement according to claim 3, characterized in that the two reference levels (R 1, R 2) are arranged essentially symmetrically to the amplitude level (MG) of the video signal, which represents a "medium gray". 5. Circuit arrangement according to claim 2, characterized in that the level comparison stage (111,112; 211,212; 311,312) emits a digital output signal. 6. Circuit arrangement according to claim 2, characterized in that between the level comparison stages (111, 112; 211, 212; 311, 312) and the edge detectors (130, 230), respectively Temporary storage (121, 122; 221, 222) is provided in which the output signals of the level comparison stages (111, 112; 211, 212; 311, 312) be cached. 7. Circuit arrangement according to claim 6, characterized in that in each case a plurality of level comparison stages (211, 212; 311, 312) via a switching device (240) with a single Memories (221, 222) are connected. 8. Circuit arrangement according to one of claims 6 or 7, characterized in that the output signals from the level comparison stages (111, 112; ZiI, 212; 311,312) are queried under the control of an external clock frequency (d) and are transferred to the memory (121, 122; 221, 222). 9. Circuit arrangement according to claim 8, characterized in that the external clock frequency (d) corresponds to the line frequency. 10. Circuit arrangement according to claim 9, characterized in that the external clock frequency (d) consists essentially of clock pulses, the rising edges of which occur in each case essentially in the center of the image area. 11. Circuit arrangement according to claim 10, characterized in that the query of the Output signals from the level comparison stages (111,112; 211,212; 311,312) and the takeover into the memories (121,122; 221,222) respectively occurs when a rising edge of a clock pulse occurs. 12. Circuit arrangement according to one of claims 8 to 11, characterized in that to achieve the horizontal grid coverage, the clock frequency (d) is above the line frequency, and that to achieve the vertical grid coverage, a clock frequency (d) is used which is equal to the line frequency . 13. Circuit arrangement according to one of claims 5 to 12, characterized in that the two digital output signals (b, c) from the level comparison stages (111, 112) assigned to a pickup tube are each fed directly to a memory (121 or 122) and that the digital output signals of the other level comparison stages (211, 212; 311, 312) are fed to two further memories (221, 222) in time division multiplexing via a switching device (240) in such a way that the further pick-up tubes are brought one after the other to coincide with the first pick-up tube. 14. Circuit arrangement according to claim 13, characterized in that the number of remaining pick-up tubes is two and that the switching of the switching device (240) takes place at a quarter of the frame rate. 15. Circuit arrangement according to one of claims 3 to 14, characterized in that a circuit device is provided through which the video signal transitions between the two reference levels (Ri, R 2), which take place at the predetermined or a higher speed, control signals for the raster correction stage ( 60), which indicate both the speed and the polarity of a transition. 16. Circuit arrangement according to claim 15, characterized in that a paired comparison The control signals are carried out by dividing the one control signal against the other by a predetermined value Measure is delayed and / or vice versa, with a predefinable amount being exceeded Deviation between the delayed Signal and the undelayed signal a rasp coverage correction signal is triggered. The invention relates to a method for achieving grid coverage for a color television camera several image pick-up tubes, with correction signals for the grid coverage of the individual Video signals are derived. The invention also relates to a circuit arrangement for carrying out the above method. There are both from the German Offenlegungsschrift 1462 777 as well as from the German Auslegeschrift 1296 173 orders to achieve eioer exact grid coverage known, for which special markings or reference patterns are used, which are arranged in the perimeter of the image. These markings are used to provide reference pulses to be developed, which are compared with each other, if at different pick-up tubes the grid coverage is not exactly given in order to generate corresponding correction signals. Included the amplitudes of the reference pulses are used to check the grid coverage and correct it if necessary. Furthermore, it is known from the German Ausiegeschrift 1 134 703, through extensive improvement to limit the causes of the identity of the individual pick-up tubes to a minimum, which could possibly result in insufficient grid coverage. The invention is based on the object of a method for achieving the grid coverage in a To create color television camera of the type mentioned, in which the grid coverage in particular is guaranteed with particularly high accuracy in the area of the center of the image. Furthermore, according to the invention, a circuit arrangement for performing the inventive Procedure are created. To solve this problem, the invention provides that of at least two image pickup tubes the correction signals during the video information to be reproduced are formed by deriving of comparison signals takes place when the video information exceeds a predetermined amplitude and has a lower or equal rise and / or fall time than specified. A particularly preferred circuit arrangement for carrying out the method according to the invention is characterized in that at least two image pickup tubes each have at least one level comparison stage a video signal to be reproduced at a first input during the reproduction period is supplied for level monitoring, diß each level comparison stage at the same time a predeterminable reference level from the outside at a second input is supplied so that the level comparator emits an output signal as soon as the to be reproduced Video signal exceeds the reference level that each level comparison stage continues to have an edge detector is connected downstream to determine the rise and / or fall time of the video signals, that the edge rise and / or fall time determined in the edge detector in a comparator is compared with a predefinable time and that with a lower or the same determined line from comparator a screen correction stage is controlled. Further preferred embodiments and advantageous developments of the invention Circuit arrangement emerge from the subclaims. According to the invention, the main advantage can be achieved that the grid coverage is most accurate there can be achieved where it is most essential, namely in the area of the center of the image. Furthermore, according to the invention, the advantage can be achieved that the scanning for television image generation Any non-linearities or distortions that occur can be compensated for in a simple manner. In addition, it is not necessary according to the invention to correct the grid coverage in particular To generate reference signals, since according to the invention details of the transmitted image as reference signals be used. In addition to the amplitudes, the rise times and / or use the fall times of those video signals for the offset correction which the Show details of the transmitted image. The invention is described below, for example, with reference to the drawing; in this shows F i g. 1 with a part of a color television camera according to the invention in simplified schematic form three image pick-up tubes, F i g. 2 in lines (α) to (/) are typical signal profiles that occur at points in the F i g. 1 are designated accordingly, F i g. 3, in diagrammatic form, a designation of the parts of the scan sequence during which the scan is performed the video waveform can be performed in a typical manner, F i g. 4 in lines (α) to (/) typical signal curves which can be used for the grid registration correction in the device of FIG. 1 and which occur at points which are similarly designated in FIG. 1,
Fig. 4g explanations, F i g. 5 a from FIG. 4 derived explanations- ♦ 5 scheme, 6a and 6b show the circuit in greater detail part of the camera of FIG. 1, 7 is a graphic illustration for explanation, F i g. 8 one from FIG. 7 derived schernatic explanation and F i g. 9 a and 9 b show the circuit of a further part of the camera of FIG. 1 in greater detail. The in the F i g. The color television camera shown in FIG. 1 comprises three input terminals 1 to 3, to which the video signals derived from the three image pickup tubes (not shown) are fed. The color value signals fed to terminals 1 to 3 are referred to below as components 1 to 3, respectively. Component 1 is fed to the first inputs of two level comparators U1 and 112 , which are used to compare the level of component 1 with two reference levels which are fed to terminals R I and R 2 (hereinafter referred to as level R 1 and level R 2, respectively labeled) and are fed from there to two inputs of level comparators 111, 112 . Components 2 and 3 are fed to first inputs of further level comparators 211, 212 and 311, 312, respectively. The level comparison