DE2030505A1 - Semiconductor arrangement with built-in semiconductor resistor - Google Patents

Description

IBM Germany Internationale Büro-Matcfiinen Gesellschaft mbH

Boeblingen, June 15, 1970
. may

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504, -V-. St. v. A.

Official file number: New registration

File number d. Applicant: Docket FI 968 013

Half leiteranor dnung with a the constructed semiconductor resistor

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The invention relates to a semiconductor arrangement comprising a substrate and an epitaxial layer arranged above it, within which by means of isolation zones from the rest of the substrate that extend down to the substrate Semiconductor material isolated demarcated areas are formed, which which contain electrical circuit elements.

In the manufacture of semiconductor devices such . B. integrated circuits, the circuit elements, such as transistors, diodes, resistors, etc., are formed in a monolithic crystal made of semiconductor material and connected to one another in such a way that the desired
electronic circuit is created. It is generally necessary to isolate the resistances occurring in the circuits so that

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there are no undesirable interactions with other elements of the Circuit result. Suitable methods for this are described, for example, in U.S. Patents No. 3,265,905, No. 3,380153, No. 3,387,193 and No. 3,432,792. However, the existing technologies always set limits to the effort to isolate the resistors, which result in compromises regarding the performance of the circuit. This was often due to parasitic capacitances that are accepted had to. The formation of resistances in the semiconductor material generally resulted in diffusion shifts in later manufacturing steps with it, which increased the parasitic capacitances. In view of these capacities, the design of integrated circuits has been particularly hindered when the circuits operate at high Speeds should work.

The object of this invention is to specify a semiconductor arrangement with a built-in resistor, in which this resistor has a particularly small stray capacitance. The semiconductor arrangement should also be compatible with the conventional manufacturing techniques of monolithic circuits which, in addition to the resistor, can contain numerous elements such as transistors, diodes, etc.

Starting from a semiconductor arrangement comprising a substrate and a overlying epitaxial layer, within which through up to the Isolation zones which are separated from the rest of the semiconductor material and contain the electrical circuit elements are formed, the invention consists in that in such an isolated epitaxial layer area a lateral resistance

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stood in the form of a diffusion area with the same conductivity as the Epitaxial layer is formed.

In the following, exemplary embodiments of the invention are presented in detail with reference to the accompanying drawings.

The diffused resistor of the present invention in a semiconductor shown in Fig. 1 comprises a substrate. 1 with a Bedding area?. of a first conductivity over which an epitaxial layer 3 drawn with opposite conductivity is. Areas 3 of the first conductivity are through the epilaxial layer 3 diffused, which combine with the underlying bedding area 2 of the same conductivity in a pattern which Forms insulating walls that delimit part of the cpitaxialcn layer 3 and form a region 5 in which the desired resistance is to be formed. The resistance consists of one heavily doped area 6, which is formed in area 5 by diffusion. He exhibits a doping with foreign atoms of the same

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Conductivity and a surface concentration which is significantly greater than that of the area 5 of the epitaxial layer 3, which in turn provides a resistance area 6 with a significantly lower resistance value than the surrounding area 5 has them. The surface concentration the foreign atoms of the resistance region & are preferably at least one order of magnitude higher than that of region 5 where the resistance value of the resistance range 6 is at least an order of magnitude below that of the area; 5 cherishes.

Fig. 1 shows a substrate 1 made of calble conductor material such as silicon _t with a region 2 of a certain conductivity, the region 2 being P-conductive in the exemplary embodiment. The substrate 1 has a planar surface 9 on which an N-conductive layer 3 is grown epitaxially.

The substrate has a monocrystalline structure, which in the exemplary embodiment can be formed by known crystal growth techniques. The substrates can e.g. be a silicon crystal, which is appropriately doped when growing up, or part of the

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Substrate becomes after growing with suitable foreign atoms boron is doped to define region 2 with an impurity distribution that corresponds to the desired use. To " known techniques is an epitaxial layer 3 opposite Conductivity (e.g. N-conductive) on the planar surface 9 of the substrate 1 drawn up in such a way that it covers the P-area 2.

In a subsequent manufacturing step, an insulating region 4 with P-conducting foreign atoms is formed in the N-conducting epitaxial layer 3 diffuses in a pattern that defines the island-like resistance area 9 specifies in which the resistor 6 is to be formed. The insulating area 4 is in most cases by the Epitaxial layer 3 diffused with known masking techniques. Regardless of the requirements for forming the remaining parts 8 of layer 3 The technique used, however, it is essential that the resistance region 9 by epitaxial growth like monocrystalline Extension of the area 2 is formed. Usually will the entire layer 3 is formed by epitaxial growth. The epitaxial layer 3 and in particular the resistance region can be placed thereon 9 are doped with corresponding foreign atoms, such as phosphorus and arsenic, to achieve resistance values in the range of 0.1-0.5 ohm * cm below a thickness of 3-8 to achieve.

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In a subsequent step, conventional oxidation masking is used the resistance as a special heavily doped N region 6 by diffusion of suitable foreign atoms, such as Phosphorus and arsenic, formed in a surface concentration that is higher than that of the surrounding parts of the area 9, which forms the resistance area 5. In practice, the concentration of the surface doping is at least around an order of magnitude above the value of range 5, but the lowest value is preferably three orders of magnitude higher. Conversely, the resistance value of the resistance area 6 is significantly smaller than that of the area 5, in practice by at least one order of magnitude, but preferably by two orders of magnitude. For example, to get a resistance range, whose resistance value is at least one order of magnitude below the value of the epitaxially grown region 5 (doped with Phosphorus to a surface resistance value of 0.1-1.3 ohm · cm) can reduce the concentration of surface contamination

20 ^{r of the} resistance range 6 are in the order of magnitude of 10 atoms / cm. In order to obtain a resistance range 6 with a resistance value that is at least two orders of magnitude below the value of the range 5, the resistance range 6 can have a

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Concentration of foreign phosphorus atoms of 10 atoms / ccm if the contradicting values in area 5 are 0.1 0.3 Ohm cm.

The unit shown in Fig. 1 is normal at the end equipped with a passivation mask 10, preferably made of silicon oxide, and with ohmic contacts 11 and 12.

As can be seen from Fig. 1, the resistance area 6 is in the Semiconductor substrate 1 isolated from the remaining parts (e.g. areas 8) by the diodes that are placed between area 5 and the base and Isolaticvnsgebiete 2 and-4 or the substrate 1 and the Areas 2 and 4 and the remaining parts 8 of the epilaxial layer 3 are formed.

The size of the resistance can be seen from the analysis of the opposing area 6, whose resistance value is two orders of magnitude below the value of area 5. Resistance area 6 has 2 - 20 ohms / square, area 5, on the other hand, is 2000 ohms / square. As shown in Fig. 1 represents the resistance area 6 represents a resistor R6 which is parallel to a resistor R5 formed by the area 5.

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The total resistance R of the areas 5 and connected in parallel 6 is easy to calculate. From what has been said it follows that a low resistance R.6 is within 1% of the desired Can form the value, this ratio being further improved when the desired resistance value of the resistance range 6 is more than two orders of magnitude below the value in area 5. For this purpose, the resistance range 6 is z. B. with

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a concentration of 10 foreign atoms / cm (for example 5 ohms / square) and area 5 with a concentration of 10 foreign atoms / cm (for example resistance values of 0.2 ohm · cm).

The connection and interference capacitance of the finished unit is reduced by the formation of the opposing area 6 in area 5 compared to previously common resistance structures in which the diffused resistances were completely in the area that was delimited by the insulating area 4 and the base area 2. The capacitance is reduced by a factor which is equal to the ratio of the doped foreign atoms in the resistance region 6 and in the region 5 to one another. For a resistor structure, the capacitance is determined e.g. B. dur, ch the sidewall and the bottom capacitance of the insulation and substrate surfaces in an epitaxial bed

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with high resistance value. The sidewall capacity is included of the present embodiment at 240 pf / mm and the floor capacity at 110 pf / mm. Conventional resistances with normal, opposite doping have a capacitance of about 415 pf / mm.

Referring now to Figures 2A-2E, sequential steps in Manufacture of another embodiment shown to the compatibility with the existing semiconductor technology using an example of the simultaneous manufacture of the resistor to show with a transistor in an integrated circuit. 2A shows a P-conductive substrate 13 made of semiconductor material, like silicon, with a resistance value of 10 ohm · cm, in which two separate, heavily doped regions 15 and 16 can be formed simultaneously by conventional diffusion. The substrate 13 normally consists of a silicon single crystal, the «lit foreign atoms, for example from boron, is appropriately doped. The one with N foreign atoms, such as phosphorus,

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Area 15 doped to a surface concentration of 10 foreign atoms / cm is as a collector area in the finished unit provided and an N-area 16 represents part of the isolation, which is necessary for the formation of a resistance.

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In a subsequent manufacturing step, which is shown in Fig. ZB, a P-type epitaxial layer 17 with a resistance value of 0.2 ohm · cm on the substrate surface 1 ·} grown and covers the two areas 15 and 16 to a thickness of 3-7 µm, so that the two N areas 15 and 16 are 6 in P-type silicon are embedded. During the epitaxial deposition of the layer 17, the outdiffusion leads to the Areas 15 and 1 6 to expand them into the epitaxial layer and thus to change the dimensions of these areas, if further processing steps are required. The expanded areas are shown at 15A and 16A in Figure 2B. The entire Impurities in the respective areas (resulting from the fabrication steps of FIGS. 2A and 2B) remain the same. By expanding these areas, however, their volumes increase and change or reduce the concentration of the contamination. The resulting reduction in the impurity concentration results in an increase in the resistance value.

Although it was described above that areas 15 and 16 can be formed simultaneously, each of the areas can of course also in separate diffusion steps prior to deposition

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of the epitaxial layer 17 can be formed. In this way · the areas 15 and 16 can be formed with different concentrations of the Doläerungs-Frejndalome. At the same time Diffusion of the areas. 15 and 16 they are naturally formed with the same concentration * of impurities. In in a subsequent processing step, the. Representation in Fig. 2C N -fremdalome, such as phosphorus and arsenic, through the cpitaxialc layer with the help of oxide masking diffused, thereby forming N regions 18 and 19 with a surface impurity concentration of 10 atoms / cm that will extend up to the corresponding one below buried N regions 15A and 1 (> A extend. The N region 18 in connection with the underlying N-area 15A represents an area for the formation of the collector of a Transistor is to be formed as part of an integrated circuit is. The N region 19 forms in the epitaxial layer 17 in connection with the underlying N region 1 6A Island area 20 in which a resistor is to be formed.

The N -regions 18 and 19 can of course be simultaneous or separately in different processing steps with each

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desired change in the surface concentration of the. Impurities are produced. For most prak, -. ";; Tical applications, the two areas are simultaneously ι by diffusion of doping foreign atoms, such as phosphorus and arsenic, produced, for example, the surface concentration;

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have tralions of 10 atoms / cm.

Regardless of the method used to form the remaining parts of the layer 17, however, as already said, it is essential that the island region 10 is epitaxially grown.

In a subsequent procedural step, according to the illustration in FIG. ZD, a heavily P -doped region 22 in the N region 18 due to selective diffusion of acceptor impurities, like boron. The P region 18 is provided as the base region of a transistor, with the rest Areas of the N region 18 together with the underlying N layer 15A form a collector region 23 of a transistor in the Define finished integrated circuit.

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Subsequent to or at the same time as the training of the

P base region 22 becomes heavily P doped in P region 20 Area designed as a resistor. This P -resistive region 24 is obtained by optional diffusion of acceptor impurities, such as boron, up to a surface concentration that is e.g.

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can be 10 atoms / cm. With simultaneous diffusion areas 22 and 24 both have the same surface concentration. As shown in FIG. 2D, the P resistance range becomes 24 through a P-area 25 of the remaining parts of the island area 20 at a certain distance from the insulating area 19 and surround the blocking area 16A.

As shown in Fig. 2E, an N impurity is next into the P base region to form a heavily N doped region with a surface concentration of about 10 atoms per cm diffused and so did the emitter 30 of the transistor 31 defined in the integrated circuit.

After the emitter diffusion can be on the surface of the epitaxial Layer 17 is applied by a suitable method, such as thermal oxidation, a passivating silicon oxide film,

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in which then by conventional photolithographic Techniques formed over the collector, base and emitter area 23, 30 and 32 openings as well as the desired contacts in the Resistance area 24 are attached. Then, a metallic film is deposited on the oxide film 32 and then selectively through a photo mask to form the collector, base and emitter connections 33, 34 and 35 as well as the ohmic ones Contacts 36 and 37 for resistor area 24 are etched away.

One embodiment made had an area 25 5 µm thick with a surface resistivity of 0.2 Ohm / cm and a surrounding P region 24 with a transition depth of 2 μm and an impurity concentration of 10 atoms / cm and represented a resistance of 150 ohms / square.

The previous one was a PNP transistor and a P resistor described. It is clear, however, that NPN transistors and resistors of opposite conductivity are also possible as well numerous combinations with elements not mentioned here.,

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Claims (6)

2J3Ü5Ö5 is PATENT CLAIMS 1.) Semiconductor arrangement consisting of a substrate and an epitaxial layer arranged above it, within which by up to the Isolation zones reaching down against the rest of the substrate Semiconductor material isolated demarcated areas are formed -which contain the electrical circuit elements, thereby characterized in that in such an isolated epitaxial layer area a lateral resistance in the form of a diffusion area the same conductivity as the epitaxial layer is formed. 2. Semiconductor arrangement according to claim 1, characterized in that that the diffusion region forming the resistor is more heavily doped than the epitaxial layer surrounding the resistor. 3. Semiconductor arrangement according to claims 1 and 2, characterized in that the substrate and the above arranged Epitaxial layers are of the opposite conductivity type. 4. Semiconductor arrangement according to claim 3, characterized by a f-substrate, an N-epitaxial layer that is separated by P-isolation zones is divided, and by an N diffuse stood within the N epitaxial layer. is subdivided, and by an N diffusion region for the reflection 5. Semiconductor arrangement according to claims 1 and 2, characterized in that the substrate and the above arranged Epitaxial layer are of the same conductivity type. 6. Semiconductor arrangement according to claim 5, characterized by a P-substrate with N -subcollector regions, a P-epitaxial layer, the is subdivided by N insulation zones reaching down to the sub-collector regions, and by a P diffusion region for the Resistance within the P-epitaxial layer. 009883 / U86 FI 968 103 - 15 - ORIGINAUINSPECTED