DE2029774B2 - Coherent pulse Doppler radar device with variable pulse period - Google Patents

Description

The invention relates to a coherent pulse Doppler radar device, whose transmitter emits high frequency pulses at unequal intervals, with a device to suppress the signal components originating from fixed targets.

In the French patent 15 63 763 circuit arrangements for the suppression of fixed target signal components with delay elements, also called MTI filters, have been described, in which the delay elements consist of memories for digital signals in which the binary words are stored that represent the amplitudes of the Characterize samples of the signals received in the individual pulse periods. The binary words read out from the memory are then used to control evaluation and summing circuits, the analog output signals of which then no longer contain any signal components from fixed targets. The evaluation circuit contains fit + l) groups of ρ current generators, where k is the number of delay elements and ρ is the number of bits of the binary words; the current supplied by the one group of current generators is proportional to the weighting factor; the current generators are controlled by the bits of the binary words. The summation circuit consists of a chain circuit to which the current generators are connected.

In the cited French patent 15 63 763 it is stated that this circuit is also used in a coherent pulse Doppler radar with unequal Pulse intervals can be used; however, this involves suppressing echoes from fixed targets less well.

It is therefore an object of the invention to provide a coherent pulse Doppler radar device with a variable pulse period to specify a device for the suppression of fixed target echoes, in which the suppression of fixed target echoes is just as good as with a pulse Doppler radar device with equidistant pulses.

This object is achieved with the means specified in claim 1. Advantageous further training can be found in the subclaims.

The invention is explained in more detail with reference to drawings; the individual figures show schematically:

F i g. 1 the block diagram of a coherent pulse Doppler radar device,

F i g. 2 the canonical form of a delay line with a plurality of elements for suppression > killing of fixed target echoes,

F i g. 3 the block diagram of a multi-element delay line, in which the delay elements are produced using digital technology,

Fig.4 shows a preferred embodiment of a ι »Circuit for the suppression of target echoes with comparison of three pulses emitted by a pulse Doppler radar device can be assigned with variable pulse spacing,

5 shows the block diagram of a circuit for r> Suppression of fixed target echoes by comparing four pulses emitted by a pulse Doppler radar device can be assigned to a variable pulse interval,

6 shows the block diagram of a circuit for suppressing fixed target echoes with comparison of 2 (i (k + 1) pulses, which can be assigned to a coherent pulse Doppler radar device in which groups of N non-equidistant pulses are transmitted periodically.

Before the individual figures are described, it seems appropriate to briefly explain the principle of the detection of moving targets in the presence of fixed targets due to the Doppler effect. In the case of radar systems that work with pulses during the Ausser.dung, the phase change of the transmitted and received wave from one pulse period to the next is determined if the waves have been reflected on moving targets. For this purpose, the phase of the wave transmitted in each pulse period is stored and compared with the phase of the received wave. This phase change is constant from one pulse period to the next when the waves have been reflected off fixed targets; however, it changes linearly with time as the waves are reflected off targets that have a constant non-zero radial velocity with respect to the radar antenna. So if one feeds a phase detector on the one hand the reference signal, which contains the phase of the transmitted signal stored in each pulse period, and on the other hand the echo signals reflected at fixed or moving targets, one obtains pulses of constant amplitude for echo signals reflected at fixed targets at the output of the phase detector and for Signals reflected from moving targets are pulses whose amplitude changes sinusoidally with a frequency fa, commonly called the Doppler frequency; the Doppler frequency / i / is linked to the radial velocity ν and the wavelength d of the radar system by the formula / </ = 2 v / d .

F i g. 1 shows the block diagram of a coherent pulse Doppler radar device. It contains an antenna 10, which is used for transmission and reception, a transmitter 2, which delivers high frequency pulses over a transmit / receive switch 1, which is also called a duplexer, to the antenna 10 and from this be sent out. The received echo signals are transmitted to a mixer 3 via the duplexer 1 fed to which the output signal of a mixer 4 is also input. The output signals of the Mixer 3 are amplified in an intermediate frequency amplifier 6. The output of the mixer oscillator 4 is also fed to a second mixer stage 5, which also occurs during the transmission of the radar pulse a high frequency signal of the transmitter 2 is input.

The intermediate-frequency output pulse of the mixer 5 hits one at the beginning of each pulse period Oscillator 8, which supplies a signal of the intermediate frequency that has a very specific phase with respect to the Phase of the transmitted pulse. In the manner described, the Oscillator 8 triggered, but then shortly before the beginning of the next following pulse period to suspend the Causes vibrations. This oscillator is known as the "coherence oscillator". Its output signal is input to a phase discriminator 7, which also receives the output signals of the intermediate frequency amplifier 6 are fed. The output signals of the phase discriminator 7 then become any Evaluation device 9 supplied.

The evaluation device can also contain an arrangement for fixed target suppression, for example a delay line with a delay time that is equal to the pulse period of the transmitted one Signals; the output signals are subtracted from the signals received in the course of the pulse period. It can be seen that the signals of equal amplitude, i.e. H. those from always the same distance (from Fixed targets) cancel out while variable amplitude signals originating from moving targets do not cancel each other out, but result in a residual AC voltage signal.

The principle of cancellation of fixed target echoes just described applies to only one fixed antenna; in the case of a rotating antenna, the echo signals from fixed targets do not have permanently the same amplitude as a result of the amplitude modulation introduced by the radiation diagram of the antenna, so that the sum of the signals at the output of the circuit for fixed target suppression with Delay elements is no longer zero.

F i g. 2 shows the canonical form of a device for fixed target suppression, in which the amplitude modulation introduced by the antenna rotation has been taken into account. The output signals of the phase discriminator 7 are fed to a circuit arrangement A 0 and a delay element L \, the delay of which is equal to the distance Γ between two successive pulses; the circuit arrangement A 0 multiplies the output signals of the phase discriminator 7 by a factor aO. The output signals of the delay element L \ are fed to a delay element Li, which is identical to the delay element U , and to a multiplication circuit A I ₁ which is circuit-wise identical to the multiplication circuit A 0, but the multiplication or weighting factor a I. The same is repeated with the output signals of the delay element L ₂ , which are fed to further delay elements up to the delay element Lk and further multiplication circuits A 2 to Ak; the individual multiplication or weighting factors are a 2 to ak. The output signals from the weighting circuits A 0 to Ak are added in an addition circuit 11, the output signal VS of which no longer contains any signal components that go back to a fixed target.

If VO, Vl, V2 ... V2 are the amplitudes of the echo signals from the same target at corresponding times 1 0, 1 1, t 2 ... tk and if applies

(0 <f 1 < 1 2 ... < Ik,

then the factors a 0 to ak must be such that the equation applies:

Ui) VIi 4- al Vk -! + ·· ■

ak - 2 12 + ak - I Vl 4 akVO ■ = 0 (1)

In the above-mentioned French patent

H )schrift 15 63 763 is a device for fixed target suppression with a multiplicity of delay elements according to the method shown in FIG. 2 described in the form shown which the delay elements are designed as digital memories.

The block diagram of such a device for fixed target suppression with digital memory is shown in FIG. 3 shown. The signals supplied by the phase discriminator 7 are quantized in a quantization circuit 13 by means of signals of the frequency Mr , each signal sample thus produced corresponding to a specific range zone calculated from the radar device. The duration of r corresponds, for example, to the duration of the transmitted pulses; the duration of r determines the accuracy of the distance resolution of the

2ϊ radar device. The signal samples continuously supplied by the quantization circuit 13 are then coded in a coding device 14 which supplies a binary word consisting of ρ bits for each signal sample, which binary word characterizes the amplitude of the signal sample.

Ki ized. The binary words, which correspond to the signals received in the course of the pulse period, are entered one after the other to an evaluation and summing circuit 15, in which they are multiplied by the factor a O before they become the k binary words that correspond to the

r. Factors a 1 to ak have been multiplied are added: these Jt binary words correspond to one and the same distance zone, and they have been stored in a memory M during the k preceding pulse periods. After the evaluation and

4 (i summation, the k binary words corresponding to the last k pulse periods that have just passed are rewritten into the memory, from which they are then read out in the course of the next pulse period. This memory can, for example, be a ferrite core memory with ρ levels of k rows and m columns each; in each row the binary words corresponding to the signals received during a pulse period are written, and the column m then denotes the number of the distance, (ι zone in the course of the k successive pulse periods. The various signals that required for the operation of the circuit of FIG. 5 are supplied in front of a clock generator //.

If the radar pulses at regular Zeitabstän> to be sent, the weighting factors need a 0 to ak only one to be determined once and for all, but when the time intervals between the out end th pulses vary, the factors aO must also be varied to al to the same degree dei

wi to achieve fixed target suppression, as with regulari gen time intervals between the transmitted pulses.

If there are three successive echo pulses: Law of the change in amplitude as a result of the amplitude denmodulation through the shape of the radiation slide

h-> gram of the antenna is assumed to be linear, the amplitude of the received pulses al: function of time t can be written as V = 50+ B Ii, where VO = ßO + ßlfO, Vl = S0 + ßl <l

V 2 = B 1 1 2. The solution of equation (1) then gives:

al = aO (l + n / rO) and a2 = aO ■ TVTO

if one sets 1 1 - 1 0 = Γ0 and f 2-f 1 = Ti . If a O = KTO is set, then the other two coefficients have the values

a2 <= KTt and a 1 = -K (TO + Ti) = - (aO + a2).

Figure 4 gives an example for realizing the evaluation and summing circuit 15 of Figure 3 for the case that the number of delay elements is equal to two This includes a pulse generator 16, the pulses of frequency F 2p ¹ delivers when F = MT denotes the mean value of the repetition frequency of the transmitted pulses; also a counter 17 with 2p counting positions; two shift registers R 1 and R 2 , each with ρ stages; electronic gates 18 and 19; a circuit arrangement 20 which supplies two successive pulses for releasing the gate circuits 18 and 19 and a further pulse for resetting the counter 17 to zero; Digital / analog converters DX and D 2, in which the binary words stored in the shift registers R 1 and R 2 are converted into voltages proportional to the binary words, for example; linear amplifiers 21 and 22; Groups Fl to G 4 of ρ current generators, the supply current of which is supplied by the amplifiers 21 and 22, the current generators being controlled by the bits of the three binary words stored in the memory M and supplied by the coding circuit. The three binary words characterize the amplitude of the signal samples from one and the same distance zone. Finally, an attenuator 23 with (p-i) taps is provided, to which the currents generated by the current generators are fed.

The binary word stored in the shift register R 1 defines the time interval H-JO = TO and the binary word stored in the shift register R 2 defines the time interval f 2- 1 1 = Γ L The decoding of these binary words in the digital / analog converters D 1 and D 2 supplies voltages which are proportional to the weighting factors a 0 or a 2; these voltages are the supply voltages for the groups Gi to GA of the ρ current generators; the current generators of the group G \ are controlled by the bits of the binary words supplied by the coding device 14; these binary words correspond to the current time interval; the current generators of group G 4 are controlled by the bits of one of the two binary words which are supplied from the memory M , this binary word corresponds to the penultimate time interval. Since the factor a 1 is the sum of the factors a O and a 2 with the opposite sign, this factor is obtained by using two groups GI and GZ of the current generators, the supply voltage for G1 being proportional to 2 © and proportional to G 3 to ^ 2 is To get the sign, the current generators are controlled by the complementary bits of the binary words that correspond to the last time interval

If it is assumed that the shift registers R i and R 2 each contain a binary word, then the operation of the circuit is shown in FIG. 4 as follows: the counter 17 zihh one step further for each pulse generator 16; when the radar transmitter (block 24, FIG. 4) sends out a pulse, the pulse generator 20 supplies three in Short time intervals successive pulses, the first of which is input to the gate circuit 19 as an enable pulse in order to take over the content of the shift register A1 into the shift register R2 ; the second is input to the gate circuit 18 as an enable pulse in order to transfer the content of the counter 17 into the shift register R 1; the third pulse is the reset pulse for the counter 17. It is assumed that the three pulses during the

occur in the emission of the radar pulse and that during this time the gate circuit 25 is impermeable. As soon as the data exchange has ended, they are on voltages present at the outputs of amplifiers 21 and 22 proportional to the duration of the two

running pulse periods of the radar device and thus proportional to the evaluation factors a 0 and a 2.

With the establishment of fixed target suppression with Comparison of three pulses, i.e. with two delay elements, are the evaluation factors a O, a I and

2 (i a 2 has been calculated in a simple way; however, this applies no longer if more than two delay elements are used. When using more than two However, it is also possible for delay elements to calculate the weighting factors, if only one

r> assumes that the time intervals between the emitted pulses form a series of arbitrary variables, the difference between which is small compared to the pseudo-period Fist. It can then be shown that the (Ar + 1) _{weighting factors} B 0n ■ - ■ a / n - - - atm if Ar is the number

in which the delay element is the solutions of a system of k linear homogeneous equations with (k + \) unknowns are It can thus be written:

^{J) 0} '"-""" lAv -'-'- iJ LV ₊ .'-'- J

In this formula, t means “the times of receipt, a. _{m is} the weighting factor that is fed to the output signal of the delay element with the ordinal number i during the time interval or the pseudo-period of the ordinal number π , Il is the symbol for the product and k is the number 4> the delay element «-.

The theory shows that to achieve one Degree of suppression for fixed targets, of those

is the same for echo pulses with constant

Evaluation factors is achieved, the factor B _0n

5 »must be variable and has the value:

kl T *

Π «t, - uj)

The theory also shows that the degree of oppression is less good if the factor a <> "is constant for example 1 is chosen.

In the event that S _{0n is} variable, the values for the other factors are given by:

-: klT ^k

IjKi ,, -, - U-MtU - ', .-, I Jl «« -. - W

(4) The implementation of a facility for suppressing

; 2

χ ι Il c,,, - f ",) Π c, j μ - r" _ /

\ j-0

10

kung of fixed target echoes according to FIG. 4 with k delay elements, the output signals of which are multiplied by the factors a, "is very cumbersome because of the difficulty of calculating the individual factors according to formula (4), in which additions, multiplications and divisions of the time intervals have to be carried out.

It can be shown that the factors a, “also can be calculated using a formula in which only additions and multiplications are carried out will need. This formula is as follows:

H-I * - I

ι - I * - 2

II U _n -IM-I - '"-j) Μ I'.IH -'" j) I ··· S = O i = i + 1

draw that the above formula (5) is the resolution of the following determinant in which the column with the Ordinal number / has been omitted.

r "

, kl , 11 Λ-I

Ίι-1 · · ■ '.ι i ■ ·''.. k

In the case where the number of delay elements is equal to three (k = 3), the values of the evaluation factors during the fourth pseudo-period must be taken into account.

</ "4 - ΙΊ - h) U _t - I ₁ ) U ₁ - h) = -Ι7Ί + Tl) TXTl

a _u = -U ₁ - U) U ₁ - I ₁ ) U ₂ - U) = (Tl + Tl + Ti) [Tl + 73) 71

« ₂₄ - C ₁ - U) Ci - /.,)(/., - U) = Γ / I + Tl + Ti) [Tl + Tl) Ti

« _U = -U ₁ - U) U ₁ - '.Olf.i - U) = (7" 2 + Ti) Tl ■ Ti

Here f ₂ -fi = 7], ht ₂ = T ₂ and U-h = T _{3 are} set, and 71, T ₂ and T3 mean the duration of the first and second and third time intervals, respectively. It can be seen that when η changes, Tj, T ₂ and Γι mean the last, penultimate or penultimate time interval, respectively.

F i g. 5 shows the block diagram of an exemplary embodiment of a circuit arrangement with the aid of which the evaluation factors ao "to a%" can be prepared.

In Fig. 5 also contains the clock generator 16, as well as the gate circuit 25, the counter 17, the shift registers R 1 and Λ 2 and the gate circuits 18 and 19, which were already used in FIG. The circuit of FIG. 5 furthermore contains a shift register A3 with ρ steps, a gate circuit 26, a clock generator 23 which supplies pulses with a frequency of at least 4 / r, and a pulse generator circuit 27 which sequentially generates the pulses for opening the gate circuits 26, 19 during the duration of the radar pulse and 18 as well as the reset pulse for the counter 17 and the pulse of duration r to close the gate circuit 25 supplies. The function blocks which carry the symbol + inside are adding circuits and those with a symbol χ are multiplication circuits. These circuits carry out the additions or multiplications to be carried out in accordance with the formulas. Such circuits have long been known; they can only be implemented using digital technology or analog technology, or a combination of digital and analog technology.

It is assumed that the output signals of the

Multiplication circuits m0, mi, τη2 and m 3 have amplitudes which are proportional to the factors a _o "or a \" or a _2n or ai " .

After the signals have been amplified in amplifiers 30 to 33, their output signals represent the supply voltages for the groups of current generators 34 to 37, the ρ current generators of each group being controlled by the bits of the binary words that are generated for group 34 by the coding device 14 and for the other groups 35, 36 and 37 from the memory M are supplied. In the case of groups 34 and 36, their current generators are controlled by the complementary bits. The currents supplied by the various current generators are added by means of a chain network 38, the output signal VS of which contains practically no components from fixed targets.

Generally speaking, the construction of a fixed target suppressor using the above formulas becomes more and more complex in terms of circuitry as the number of delay elements increases. There is, however, a fairly good solution which can be implemented if the radar pulses are transmitted periodically in groups of N pulses. If the pulse intervals are known in advance, then the (k + 1) weighting factors - if the number of delay elements is equal to Ar - can be calculated for each time interval of the transmitted pulses using the above formulas. So N (k + 1) evaluation factors have to be calculated, the binary values of which are then written into a memory.

that has ρ levels with N rows and (k + 1) columns each. The memory is organized in such a way that each of the lines contains the (k + 1) binary words which define the weighting factors over a time interval. This memory is scanned cyclically in synchronism with the series of pulses that have just been sent out. 6 shows the canonical form of such a circuit arrangement.

The circuit arrangement according to FIG. 6 contains a memory 40 with ρ levels of N rows and (k + 1) columns each, into which the N (k + 1) weighting factors are written in the form of binary words each consisting of ρ bits; it furthermore contains a selection circuit 41 in order to select the different lines of the memory 40, furthermore shift registers RQ to Rk, into which the (k + \) binary words which characterize the weighting factors during the time interval just started are written at the beginning of each pulse period; It also contains digital / analog converters OO to Dk for the (k + \) binary words, amplifiers CO to Ck for amplifying the analog output signals of the digital / analog converters, groups GO to Gk of each ρ current generators, their supply voltages from the amplifiers CO to CK are supplied and which are controlled by the bits of the individual binary words which characterize the amplitude of the signal samples; the binary words are supplied for the current time interval from the encoder 14 and for the previous k time intervals from the memory M ; Finally, a chain network 42 is also provided, by means of which the currents supplied by the current generators are added.

The selection circuit 41 for selecting the different lines of the memory 40 is actually used as a processing circuit for the N pulses of the pulse

H) groups to consider. For purposes of explanation it is assumed that the pseudo-period is Γ = 256 microseconds, that the time intervals with respect to the pseudo-period are a whole multiple of 4 microseconds, and that N is equal to 8 dies

ι -, the maximum frequency is then 2.5 MHz; this frequency is in the form of pulses from a circuit 43 delivered. These pulses are fed into a counter 44 which has 512 counts. The counter 44 is assigned to a decoding matrix 45 for

jo decoding of eight codes is provided, of which each corresponds to a pulse of the pulse group. The code are obviously near a whole multiple of 64, which is a counting time equal to Is pseudo-period. The decoding matrix 45 has eight

ji outputs that indicate the lines of memory to be selected 40 correspond.

IUlMVU 4 BIaIT

Claims (7)

Patent claims: 1.Coherent pulse Doppler radar device with a device for suppressing the signal components originating from festivals, the transmitter of which sends out high-frequency pulses at uneven time intervals and the receiver, which receives the echo pulses, contains a phase discriminator to which on the one hand the output signals of the receiver and on the other hand the output signals of a Coherence oscillator are input, the output signals of a quantization circuit and the signal samples obtained on the output side are then fed to a coding device in which the amplitudes of the signal samples are coded as binary words with a certain number of bits and the binary words corresponding to a predetermined number of pulse periods are written into a memory, the Binary words are written one after the other into the rows of the memory and then output again at the same time in columns according to the temporal occurrence of the signal samples in the successive pulse periods are read, in which the binary words read out from the columns, which correspond to the number of the last, past pulse periods, as well as the binary word corresponding to the current pulse period are rewritten in the corresponding columns of the memory, and in which the respective columns according to the Time of the occurrence of the signal samples read out binary words from the memory and the binary word just coded at this point in time are fed to an evaluation and summing circuit, characterized in that the evaluation factors (a _ant am) of the evaluation and summing circuit (15) with which the from echo signals originating from the same target are evaluated, are proportional to the distances between the transmitted pulses. 2. Coherent pulse Doppler radar device according to claim 1, characterized in that the Evaluation factor ao "is equal to 1. 3. Coherent pulse Doppler radar device according to claim 1, characterized in that the weighting factor ao " by the equation «On - k ! 7 * II (("- f. J) i = I is determined, where T is the mean pulse period, t _{n are} the times at which a pulse is received, π is the ordinal number of the pulse, k is the number of stored values of the pulse periods and 11 is the symbol for product. 4. Coherent Fuls Doppler radar device according to claim 2 or 3, characterized in that the evaluation factors a, " by the equation / Y ₁ Il 5. Coherent pulse Doppler radar device according to claim 2 or 3, characterized in that the Evaluation factors a, "by the equation i = I i, = 1 k- 1 II U _n -k - i »-j) II Cn-ii - :» - j'i k - 2 j = i + 1 x III (ί ,, -; - Γ- '»-j! i -1 are determined, where i can assume values between 0 and A :. are determined. 6. Coherent pulse Doppler radar device according to one of claims 1 to 5, characterized in 2i) net that the evaluation and summing circuit (15) contains a digital measuring device (16, 17) for the time intervals between the transmitted high-frequency pulses, that this measuring device is one of the specific number (p) of bits _>) existing number of binary words for the individual time intervals of the last transmitted (k + 1) pulses provides that these binary words in a number (k) of shift registers (R) corresponding to the number of pulse periods (k) , each with one of the in number (p) of bits of a binary word corresponding number (p) of stages are stored, that a plurality of gate circuits (18, 19,26) is provided, which the output of the digital measuring device (16,17) with the input of the first J-. Connect the (k) shift register (R) or the output of the (k) shift register (R) to the input of the next shift register (R) , so that a pulse distributor (20, 27) is provided at the beginning of each time interval Number (k) on top of each other Hi the following impulses that are necessary to take over the Signal content of the shift register in the next following shift register the gate circuits (18, 19, 26) are supplied as enable pulses, that furthermore a plurality of addition, multiplication r, division and possibly division circuits (+, x) are provided in order to combine the number (k) of binary words contained in the shift registers (R) , and a number (k + 1) for the entire duration of a time interval v) to obtain signals which are proportional to the number (k + \) of weighting factors, and that an equal number (k + \) of groups of current generators (G, 34-37) corresponding to the number (p) of bits of a binary word are also provided v, whose supply voltages are proportional to the weighting factors (number Jt-M) and whose current generators (G, 34-37) are controlled by the bits of the binary words that are characteristic of the amplitude of the signal samples. Wi den, and that finally a chain-ladder network (38,42) is provided. to which the output currents of the current generators are fed for addition. 7. Coherent pulse Doppler radar device according to claim 6, characterized in that at one h> periodically repeating transmission of groups of a certain number (N) of pulses each a second memory (40) for storing the N groups of fit + I) binary words each ρ bits is provided, which correspond to the (k + \) current weighting factors of the (N) time intervals of the pulse group that the N (k + \) weighting factors are determined by the fact that at the beginning of each time interval the (k + \) binary words, the the (k + \) evaluation factors of the current time interval are read out from the second memory (407) that furthermore (k + 1) groups of ρ current generators (Gjdem are assigned to the second memory, whose supply voltages are proportional to the (k + \) binary words and which are controlled by the ρ bits of the individual binary words, which characterize the amplitude of the signal samples, and that finally a chain network (42) is provided to which the currents supplied by the (k + \) groups of the ρ current generators (G) are fed for addition will.