DE202005011864U1 - Ternary flip flop pre driver based on ternary and quaternary logic has pnp logic or or dual gate and and p binary and gate and carry signal - Google Patents
Ternary flip flop pre driver based on ternary and quaternary logic has pnp logic or or dual gate and and p binary and gate and carry signal Download PDFInfo
- Publication number
- DE202005011864U1 DE202005011864U1 DE200520011864 DE202005011864U DE202005011864U1 DE 202005011864 U1 DE202005011864 U1 DE 202005011864U1 DE 200520011864 DE200520011864 DE 200520011864 DE 202005011864 U DE202005011864 U DE 202005011864U DE 202005011864 U1 DE202005011864 U1 DE 202005011864U1
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- binary
- signal
- trinary
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0002—Multistate logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/34—Digital stores in which the information is moved stepwise, e.g. shift registers using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/038—Multistable circuits
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Amplifiers (AREA)
Abstract
Description
Die Erfindung betrifft einen trinären Flip-Flop Vortreiber auf der Basis trinärer und quasi quartärer Logiken zur Anwendung in digitalen Computern und anderen digitalen Signalverarbeitungsanlagen.The Invention relates to a trinary Flip-flop pre-driver based on trinary and quasi-quaternary logics for use in digital computers and other digital signal processing equipment.
Stand der TechnikState of the art
In
der
Durch
Verwendung eines trinären
Logikübertragungskanals
werden Daten von einer ersten binären Koinzidenzschaltung (
Die
Diesen Lösungen sind in bezug auf eine hohe Datendichte, einer schnellen Datenverarbeitung und der notwendigen Anzahl der Anschlüsse Grenzen gesetzt.this solutions are in terms of high data density, fast data processing and limits the necessary number of connections.
Schließlich beschreibt
die
Diese Schaltungen haben den Nachteil, das bei Pegelschwankungen Informationsfehler auftreten.These Circuits have the disadvantage that with level fluctuations information error occur.
Insgesamt kann mit den bekannten Schaltungen kein trinärer Flip-Flop Vortreiber realisiert werden, der in kompletten trinären oder auch quartären Systemen einsetzbar ist.All in all can be realized with the known circuits no trinary flip-flop pre-driver be in complete trinary or even quaternary systems can be used.
Aufgabe der ErfindungObject of the invention
Aufgabe der Erfindung ist es, einen trinären Flip-Flop Vortreiber auf der Basis trinärer und quartärer Logiken zu schaffen, der in kompletten trinären oder auch quartären Systemen einsetzbar ist und mit dem höhere Übertragungsraten und – geschwindigkeiten sowie fehlerfreie Ergebnisse auch bei schwankenden Pegeln erreichbar sind.task The invention is a trinary flip-flop Predictor based on trinary and Quaternary To create logics in complete trinary or even quaternary systems is usable and with the higher transfer rates and speeds as well as error-free results even with fluctuating levels achievable are.
Die Aufgabe wird mit den Merkmalen des 1. Schutzanspruchs gelöst. Vorteilhafte Ausgestaltungen sind Gegenstand der Unteransprüche.The Task is solved with the features of the first protection claim. advantageous Embodiments are the subject of the dependent claims.
Einem trinären Schalt- und Rechensystem, das bekannterweise drei Potentialpegel, z. B. 0 (Masse), +5V, –5V, verwendet, wird ein weiterer Zustand, 0 (hochohmig) hinzugefügt, so dass nunmehr vier unterschiedliche elektrische Potentialpegel (Masse, +5V, –5V und hochohmiger Zustand) gebildet sind, die jeweils durch eine arithmetische und logische Zahl ersetzt werden (0, 1, 2, 3).a trinary Switching and computing system known to have three potential levels, z. 0 (ground), + 5V, -5V, used, another state, 0 (high impedance) is added, so that now four different electrical potential levels (ground, + 5V, -5V and high-impedance state) are formed, each by an arithmetic and logical number are replaced (0, 1, 2, 3).
Durch den hochohmigen oder auch offenen Zustand (3) sind quasi vier Zustände realisiert, so dass auch von quartären Logiken gesprochen werden kann.By the high-resistance or open state (3), virtually four states are realized, so that too of quaternary Logics can be spoken.
Außerdem sind durch die wechselweise Verschaltung von P-, N-, NP- und PN- Binärlogikarten zusammen mit den vier Signalzuständen verschiedene trinäre und quartäre Logiken darstellbar.Besides, they are by the mutual interconnection of P, N, NP and PN binary logic types together with the four signal states different trinary and quaternary Logic representable.
Ein N- polarer Eingang und ein P- polarer Ausgang wird derart verknüpft, dass der N- polare Eingang nur einen Zustand 2 (Signal 2) und der P- polare Ausgang nur den Zustand 1 (Signal 1) erkennt oder umgekehrt.One N-polar input and a P-polar output is linked such that the N-polar input only a state 2 (signal 2) and the P-polar Output recognizes only state 1 (signal 1) or vice versa.
Auf dieser Grundlage ist ein trinärer Flip-Flop Vortreiber realisiert, der in einfachster Weise aus binären, dualen und trinären Gliedern geschaltet ist.On this basis is a trinary one Flip-flop pre-driver realized in the simplest way from binary, dual and trinary Is switched limbs.
Dabei werden in den binären Gliedern, die die logischen Grundbauelemente bzw. -gatter bilden, zwei logische Zustände trinärer oder quartärer Eingangssignale in zwei logische Zustände an einem Ausgang Q gewandelt.there be in the binary Members that form the basic logic components, two logical states trinary or quaternary Input signals in two logic states at an output Q converted.
Demgegenüber bestehen die dualen Glieder aus einer Verschaltung von zwei binären Gliedern, so dass zwei Ausgänge Q1 und Q2 binärer Signale gebildet sind.In contrast, the dual elements consist of an interconnection of two binary elements, so that two outputs Q 1 and Q 2 of binary signals are formed.
Durch den Aufbau von Endstufen können die Ausgangssignale der binären und dualen Glieder trinär oder quartär gewandelt werden.By the structure of power amplifiers can the output signals of the binary and dual members trinary or Quaternary be converted.
BeispieleExamples
An Hand von Zeichnungen werden der Aufbau und die Wirkungsweise der Erfindung näher erläutert.At Hand of drawings are the structure and operation of the Invention closer explained.
Es zeigen:It demonstrate:
In
So
zeigt
Somit wird ein Signal 2 an den Eingängen A oder B zum Signal 1 am Ausgang Q ODER verknüpft, denn ein N- polarer Eingang wandelt nur ein Signal 2 zu einem Signal 1 am P- polaren Ausgang. Die in unterschiedlicher Kombination an den Eingängen A ∨ B angelegten logischen Zustände (0, 1, 2, 3) werden demzufolge in die binären logischen Zustände 0 und 1 am Signalausgang Q gewandelt. A(2)∨B(2)=Q(1).Consequently becomes a signal 2 at the inputs A or B to the signal 1 at the output Q OR linked, because an N polar input only converts a signal 2 to a signal 1 at the P-polar output. The logical states applied at inputs A ∨ B in different combinations (0, 1, 2, 3) are consequently in the binary logic states 0 and 1 at the signal output Q converted. A (2) ∨B (2) = Q (1).
In
Somit wird ein Signal 1 (P- polar) an den Eingängen A oder B zum Signal 2 (N- polar) am Ausgang Q ODER verknüpft. Die in unterschiedlicher Kombination an den Eingängen A ∨ B angelegten vier logischen Zustände (0, 1, 2, 3) werden in binäre logischen Zustände (0, 2) am Signalausgang Q gewandelt. A(1)∨B(1)=Q(2).Consequently becomes a signal 1 (P polar) at the inputs A or B to the signal 2 (N polar) at the output Q OR linked. The four logical inputs applied in different combinations at the inputs A ∨ B conditions (0, 1, 2, 3) are in binary logical states (0, 2) at the signal output Q converted. A (1) ∨B (1) = Q (2).
Ein
P- binäres
logisches ODER-Gatters
Ferner
wird für
den trinären
Flip Flop Vortreiber
Ein
ODER-ODER- Dualgatter
Die
Somit
wird Signal 1 an den Eingängen
A, B oder C zum Signal 1 am Ausgang Q1 NAND
und an den Eingängen
A, B oder C zum Signal 2 am Ausgang Q2 NAND
verknüpft.
Es ergibt sich: (A∧
Die
Figuren
Die
trinäre
Endstufe
In
der trinären
Endstufe
In
der trinären
Endstufe
- 11
- NP binäres ODER-Gatter (Signal 2 am Eingang, Signal 1 am Ausgang)NP binary OR gate (signal 2 at the input, signal 1 at the output)
- 22
- PN binäres ODER-Gatter (Signal 1 am Eingang, Signal 2 am Ausgang)PN binary OR gate (signal 1 at the input, signal 2 at the output)
- 44
- PN binäres UND-Gatter (Signal 1 am Eingang, Signal 2 am Ausgang)PN binary AND gate (signal 1 at the input, signal 2 at the output)
- 55
- P binäres ODER-Gatter (für Signal 1)P binary OR gate (for Signal 1)
- 77
- P binäres UND-Gatter (für Signal 1, Eingänge sind auf Signal 1 abgeP binary AND gates (for Signal 1, inputs are abge on signal 1
- stimmt)Right)
- 88th
- N binäres UND-Gatter (für Signal 2)N binary AND gates (for Signal 2)
- 99
- ODER-ODER GatterOR OR gate
- 1313
- ODER-ODER Gatter, Nullpegel EndstufentreiberOR OR Gate, zero level power amplifier
- 1414
- NAND-NAND Gatter, Highpegel EndstufentreiberNAND NAND Gate, high-level power amplifier
- 1515
- Endstufefinal stage
- 1616
- Endstufe mit Highpegeltreiberfinal stage with high level driver
- 1717
- Endstufe mit High- und Nullpegeltreiberfinal stage with high and zero level driver
- 3030
- Flip Flop Vortreiberflip Flop pre-driver
Claims (4)
Priority Applications (1)
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DE200520011864 DE202005011864U1 (en) | 2005-07-21 | 2005-07-21 | Ternary flip flop pre driver based on ternary and quaternary logic has pnp logic or or dual gate and and p binary and gate and carry signal |
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DE200520011864 DE202005011864U1 (en) | 2005-07-21 | 2005-07-21 | Ternary flip flop pre driver based on ternary and quaternary logic has pnp logic or or dual gate and and p binary and gate and carry signal |
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Publication Number | Publication Date |
---|---|
DE202005011864U1 true DE202005011864U1 (en) | 2005-10-27 |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE202011107796U1 (en) | 2011-11-14 | 2011-12-05 | Claudia Krupop | Elastic silicone band for people's arms or feet |
-
2005
- 2005-07-21 DE DE200520011864 patent/DE202005011864U1/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE202011107796U1 (en) | 2011-11-14 | 2011-12-05 | Claudia Krupop | Elastic silicone band for people's arms or feet |
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Effective date: 20090203 |