DE202005000512U1 - Sequence switching of light emitting diode groups used a shift register of D type flip flops with a half pulse delay - Google Patents

Abstract

A number of light emitting diodes, LED, are operated in a sequence switching mode using a control circuit based around a shift register [403a-403e] of D type flip flops. The data output is fed to a clock detector circuit [408] and is delayed by a half clock pulse. This provides a latch signal [418] to a selector [417] coupled to a second set of D type flip flops [402a-402d] and control signal is generated.

Description

technical area

The The invention relates to series-connected light-emitting diode groups, which the system stability increase and reduce the number of signal lines.

State of technology

The Light-emitting diode groups can be sequenced, each LED group controlled independently can be.

• 1. Eine Steuerdose ist vorgesehen, die über ein Kabel mit den Leuchtdiodengruppen verbunden ist. Bei dieser Steuerung werden die Herstellungskosten durch die Kabel erhöht. Zudem ist die Installation schwer, da die Kabel unterschiedliche Länge haben.
• 2. Jede Leuchtdiodegruppe ist mit einer Steuerschaltung versehen und hat eine ID-Adresse. Die Leuchtdiodengruppen sind über Stromleitungen und Signalleitungen miteinander gekoppelt. Bei dieser Steuerung werden die Herstellungskosten durch die Controller für jede Leuchtdiodegruppe erhöht. Zudem wird die Herstellung und die Reparatur durch die Definition der ID-Adresse erschwert.
• 3. Die Leuchtdiodengruppen werden reihengeschaltet, wobei die Leuchtdiodengruppen identisch sind, so daß die Verkabelung, die Installation und die Reparatur erleichtert werden.

The series-connected light-emitting diode groups are usually controlled as follows:

• 1. A control box is provided, which is connected via a cable to the light-emitting diode groups. With this control, the manufacturing costs are increased by the cables. In addition, the installation is difficult because the cables have different lengths.
• 2. Each LED group is provided with a control circuit and has an ID address. The light-emitting diode groups are coupled to one another via power lines and signal lines. With this control, the manufacturing costs are increased by the controllers for each LED group. In addition, the manufacture and repair is made more difficult by the definition of the ID address.
• 3. The light-emitting diode groups are connected in series, the light-emitting diode groups being identical, so that the wiring, installation and repair are facilitated.

7 shows a block circuit of the series-connected light-emitting diode groups, the five light-emitting diode groups ( 101 - 101b ) contains. The signals ( 102 . 103 ) are interconnected via six lines including a data line, a clock line, a latch line, an output power line, a power line, and a ground line. All light-emitting diode groups ( 101 - 101e ) are connected via these lines with the signals ( 102 . 103 ) connected.

8th shows a circuit arrangement of the light-emitting diode group ( 101 - 101e ) according to 7 that contains four loops that are for illustration only. The signals 210 stand at the signal input and the signals 211 are at the signal output. Four D flip flops ( 203a - 203d ) form the SR shift registers. According to the clock signal at the clock input (CLKI), the data signal at the data input (DATI) in the D flip-flops ( 203a - 203d ) saved. At the same time, the internal data is sent through the data output (DATO) to the next light-emitting diode group.

Thereafter, the output data of the four D flip-flops ( 203a - 203d ) by the latch signal at the latch input (STBI) of the other group of D flip-flops ( 202a - 202d ). The output data of the D flip-flops ( 202a - 202d ) are applied to a light-emitting diode driver circuit ( 201 ), which light emitting diodes ( 213a - 213d ). The buffers ( 204 . 205 . 206 . 207 ) are used for buffering the clock signal at the clock output (CLKO), the data signal at the data output (DATO), the latch signal at the latching output (STBO) and the output energy signal at the output energy output (OEO). The four signals described here (data signal, clock signal, latch signal and output energy signal) are the basic signals of this system. If an additional function is provided, the number of signal lines is increased.

Due to the high number of signal lines, a transmission error can occur ( 4 to 6 ), so that the system stability is low.

Task of invention

Of the Invention is based on the object, series-connected light emitting diode groups to create, which increase the system stability and the number of signal lines can reduce.

These Task is inventively characterized solved, that the Latch line replaced by an internal Latency signal and the starting date delayed by half a clock pulse which reduces the number of lines and increases system stability.

Short description the drawings

1 shows a block circuit of the coupling of the light emitting diode groups of the invention,

2 shows a circuit arrangement of the light-emitting diode group of the invention,

3 shows a timing sequence of the invention,

4 shows a representation of the delay of the date of the invention,

5 shows a further illustration of the delay of the date of the invention,

6 shows a clock sequence according to 4 and 5 .

7 shows a block circuit of the coupling of the light-emitting diode groups of the conventional solution,

8th shows a circuit arrangement of Light-emitting diode group of the conventional solution.

Ways to execute the invention

1 shows a block connection of the coupling of the light emitting diode groups of the invention, which contains only two signal lines (CLK and DAT) apart from the power lines (VDD, GND). With the numbers ( 301 - 301e ) five light-emitting diode groups are called. The number ( 302 ) stands for the entrance and the number ( 303 ) stands for the exit. The light-emitting diode groups are coupled to one another only via four lines.

2 shows a circuit arrangement of the light-emitting diode array, which differs from the conventional solution in 8th only distinguished by the following:

First, the data output (DATO) is a D flip-flop ( 403e ), which can delay the output data by half a clock pulse. Second, an additional clock detector circuit ( 408 ) intended. After applying the data signal to the data input (DRTI and 502 in 3 ) has the clock signal (CLKI and 501 in 3 ) an interrupt, whereby the clock detector circuit ( 408 ) a latch signal ( 418 ) to a latch signal selector ( 407 ), whereby the latch signal ( 417 ), that of the other group of D flip-flops ( 402a - 402d ) which supplies the output data ( 415 ) of the SR shift registers ( 403a - 403b ) and control signals ( 414 ) produce. These control signals ( 414 ) are applied to the light-emitting diode driver circuit ( 401 ), whereby the light emitting diodes ( 419a - 419c ). This eliminates the latch line. The latch signal selector ( 407 ) serves to increase the flexibility of the circuit. The system designer can select the internal or external latch signal as needed. The selection of the latch signal is effected by the latch mode selector ( 411 ), which is not part of the invention.

The buffers ( 404 . 405 ) for the clock signal have the same function as the buffers in 8th ,

The clock sequence in 3 serves to illustrate the operation of the clock detector circuit ( 408 ), with the delay time Tlos ideally being 20us-100us. However, the delay time is not limited to this.

In the 4 to 6 the delay of the starting date is described. As shown, the first D flip-flop locks ( 610a ) ( 4 ) at the first clock edge ( 611 ) of the clock signal ( 601 ) the starting date ( 602 ). At the second clock edge ( 614 ) of the clock signal ( 601 ), the next D flip-flop ( 610b ), whereby the starting date ( 603 ) of the D flip-flop ( 610a ) is delayed by half a clock pulse. From the D flip-flop ( 610b ) an initial date ( 604 ) receive. The next D flip flop ( 610c ) ( 5 ) locks at the rising clock edges ( 620 . 621 . 622 ) of the buffered clock signal ( 605 ) the starting date ( 604 ) from the last D flip-flop ( 4 ). Therefore, each D flip-flop locks ( 610a - 610c ) only the date when it becomes stable (before or after the change) so that the correction of the date taken in each measure can be ensured.

6 shows a timing sequence image where the date is unstable in the shadow areas. The formation of these shadow areas is due to the fact that the integrated circuits have a manufacturing tolerance, whereby the clock signal can be output faster or slower than the data signal.

In addition, the digital signal can be affected by the capacitor and resistor of the circuit since it is not binary (0 and 1). When the clock level of the D flip-flops ( 610a - 610c ) of the integrated circuits is different (about +/- 20% VDD), a deviation will also be caused.

In the conventional solution according to 8th Both the clock signal and the data signal are output almost simultaneously (time difference of only a few ns to a few tens ns). When multiple integrated circuits from different manufacturing processes are connected together, a data error can occur. This data error has only a small influence on a single circuit board. When two D flip-flops are 100 mm apart, the influence of this data error is very large. The date ( 603 ), which in the clock sequences ( 631 . 632 ) of the clock signal ( 605 ), as happens in the 4 to 6 is shown in the shadow areas, so that a 100% correction of the acquired date can not be guaranteed.

By a command for luminous efficiency, a serial signal can be generated, with which the internal logic circuit can perform a control of the light output, so that the output power line (OE in 8th ) can be omitted. This technique is known and will not be described in detail here.

In summary It should be noted that the invention the system stability increase and can reduce manufacturing costs.

Claims (4)

Series-connected light-emitting diode groups containing a plurality of shift registers, D flip-flops and a light-emitting diode driver circuit, characterized ge indicates that the latch line can be replaced by an internal latch signal and the output data can be delayed by half a clock pulse, which reduces the number of lines and increases system stability. Series-connected light-emitting diode groups according to claim 1, characterized in that the light emitting diode groups only over four lines are coupled together, the two power lines and two signal lines. Series-connected light-emitting diode groups according to Claim 1, characterized in that the data output (DATO) is a D flip-flop ( 403e ), which can delay the output data by half a clock pulse, and that an additional clock detector circuit ( 408 ) is provided, wherein after the application of the data signal to the data input, the clock signal has an interrupt, whereby the clock detection circuit ( 408 ) a latch signal ( 418 ) to a latch signal selector ( 407 ), whereby the latch signal ( 417 ), that of the other group of D flip-flops ( 402a - 402d ) which supplies the output data ( 415 ) of the SR shift registers ( 403a - 403b ) and control signals ( 414 ), which are connected to the light-emitting diode driver circuit ( 401 ), whereby the light emitting diodes ( 419a - 419c ), wherein the latch signal selector ( 407 ) is used to increase the flexibility of the circuit and the system designer can select the internal or external latch signal as needed. Series-connected light-emitting diode groups according to claim 1, characterized in that the D flip-flop at the first clock edge of the clock signal, the output date of the the latter D flip-flops latched and at the second clock edge the clock signal the next Flip-flop is activated, reducing the starting date by half Clock pulse to be delayed can, so that every D flip-flop only locks the date when it becomes stable, which is why the correction of the date taken in each measure is ensured can be.