DE2014155A1 - Process for producing a semiconductor structure and semiconductor structure produced by this process - Google Patents

Description

PATENT ADVOCATE

β Munich 7i, 24th March ζ I97O

MelchlontraBe 42

MalnZdchin: M97P-J56

Method of manufacturing a semiconductor structure as well as semiconductor structure produced by this process

The present invention relates to a method. for the production of a semiconductor structure and in particular a method for the production of an improved semiconductor structure with near-surface pn junctions and short switching times as well as a semiconductor structure produced by this method. In the context of the present invention, the term “structure” encompasses both discrete semiconductor components and monolithic integrated circuits and integrated hybrid circuits (IOs).

Numerous known methods are used to manufacture transistors and integrated Circuits thermal oxides used as diffusion masks. For example, it is common to on a semiconductor wafer a mask made of thermal To form oxide, such as silicon oxide, to limit the transverse dimensions of the base and emitter diffusion of a bipolar transistor.

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In a conventional manner, the thermal oxide is left on the semiconductor wafer after the aforementioned diffusion steps have been carried out the pn junctions at the points where they come to the surface of the semiconductor structure kick, protect and stabilize. In cases where the diffusion mask is made of thermal Silica initially took the form of defining and limiting the outer dimension of the base diffusion of the transistor and then (by a subsequent renewed oxide growth step) the shape for definition and limiting the transverse dimension of the emitter diffusion, which ultimately possesses over The oxide layer obtained at the pn junctions has a stepped shape. After that you have to go through these levels Metallization layers for the formation of ohmic contacts on the transistors or other passive ones Components, such as applied resistors formed in the semiconductor structure will.

These steps in the protective and stabilizing oxide on the semiconductor surface represent an obvious one Disadvantage. They make it difficult to get good, cohesive and adherent Metallization grid for the ohmic contacts of the active zones of a transistor, a To apply diffused resistance or similar elements on the oxide surface. An enlargement the number of steps in the surface oxide on which the metallization grid must be applied, increases the possibility of cracks, breaks and other defects in the metallization, leading to Committee on the elements and integrated circuits in the semiconductor structure leads.

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About those arising from the stepped oxide layers To avoid disadvantages, various methods are known in which the surface oxide is removed from the semiconductor structure after the last diffusion step. at this known method is after removing the entire diffusion mask from thermal Oxide on the surface of the semiconductor structure a single contiguous. Layer of thermal Oxide grown. In this new layer, for example, by etching, new windows are made in which the metallization is used to form Ohmic contacts are introduced on the active and passive elements in the semiconductor structure can. However, by removing the entire oxide layer from the semiconductor structure after all diffusions also all pn junctions of the semiconductor structure are temporarily exposed, whereby these pn junctions can be contaminated. You must also apply a new protective Surface layer on the surface of the semiconductor structure creates new windows in this layer for the Base and smitter contact are provided. The manufacture of these windows in the protective upper ' surface layer for the ohmic contacts leads especially with very small geometric structures difficulty aligning the masks.

It would therefore be desirable to have these critical alignment steps involved in manufacturing the windows in the protective surface layer are required for the contact metallization, to be able to eliminate.

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It would also be advantageous to have a semiconductor structure to be able to create the protective surface layer, such as a silicon dioxide layer has uniform thickness and at which all pn junctions of the structure before manufacture the last protective surface layer are not exposed.

The present invention therefore resides in. Object is based on a method for producing an improved passivated semiconductor structure with short switching times, such as a integrated circuit (IC) and improved semiconductor structures produced using this process to specify. The semiconductor structure should in particular be relatively easy to metallize be.

'./ Furthermore, in the production of a uniform Passivation layer on the semiconductor structure, the pn junctions during the manufacture of the semiconductor structure exposed as little as possible. In particular, the method according to the invention is intended here for piercing diffused resistance and transistor zones in thin semiconductor structures with near-surface pn junctions and high packing density.

Finally, in the method according to the invention the critical mask alignment in making a window for the emitter contact of a transistor omitted.

To solve the above problem is at a

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Method for producing a semiconductor structure according to the invention provided that on the surface of a semiconductor body, a mask is formed that for the formation of a zone .in the semiconductor body a dopant is introduced into the semiconductor body through a window in the mask, that on the exposed part of the zone and on one part of the mask a thin protective layer is applied that a photomask is applied to the thin protective layer, and that the thin protective layer serves as a holder for the photomask during a selective etching of the mask.

A further development of the invention is a semiconductor structure produced according to the method defined above characterized by the following features: A transistor with on the surface of the semiconductor body emerging pn junctions in the semiconductor body, a passivating, applied from the gas phase, the protective oxide layer covering the pn- * junctions of a first layer of silicon dioxide and a second layer of phosphosilicate 'on top of the Semiconductor body ,. Window in the protective oxide layer, which expose the emitter and base zones of the transistor and metal contacts made in the window for ohmic contacting of the transistor,

According to a special feature of the invention with a transistor structure with near-surface pn junctions one or more at low temperatures applied oxide passivation layers after Manufacture; the base zone of the transistor and after completely removing the diffusion mask made for the base zone.

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According to a special feature of the invention, a thin oxide layer applied at low temperatures is used by thermal growth of a layer of phosphorus silicate over previously prepared Oxide passivation layers and made over the emitter region of the transistor. This thin that The oxide layer covering the emitter zone is used for the base contact during the etching of a window the transistor protected by a photo mask; then the thin oxide layer is covered by a Controlled step removed or 'grown out'. The emitter zone is thus exposed again for the production of an ohmic contact without a additional critical photoresist and masking step is required. That way it becomes Alignment problem with an additional photoresist and masking step to produce the ohmic Basic contact eliminated.

According to a further feature of the invention, a transistor has pn junctions close to the surface and fast switching time, a passivating oxide layer of uniform thickness to protect the pn junctions intended. There is only one pn junction during the manufacture of the transistor exposed, so that in the production of a surface oxide layer of uniform thickness the exposure is kept to a minimum by pn junctions.

Further details of the invention emerge from the following description of exemplary embodiments based on the figures. It shows:

1 shows a p ~ 3 substrate or a starting semiconductor material

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figure

Figure figure

figure

Figure figure

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for the method according to the invention; the fabrication of an n ⁺ buried layer in the p ~ 3 substrate; the production of an η-type epitaxial layer on the p ~ substrate; fabricating the base of a bipolar transistor, a p ⁺ isolation region and a diffused p ⁺ resistor in the previously fabricated epitaxial layer; the deposition of a plurality of oxide layers from the gas phase on the surface of the previously produced epitaxial layer; the manufacture of the emitter region of the transistor in the semiconductor structure; the production of a very thin oxide layer on the oxide layers previously produced by deposition from the gas phase and the production of a photomask on the thin oxide layer; ·

the selective removal of surface oxide on the semiconductor structure to expose the. Base region of the transistor for a subsequent metallization step; the removal of the thin oxide layer for exposure the emitter region of the transistor; and the finished one made according to the invention Semiconductor structure with a surface metallization.

In the semiconductor structure produced according to the invention with near-surface pn junctions and short switching times, the base zone is first of a transistor using a diffusion mask

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either

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made either from thermal oxide or from oxide deposited from the gas phase. After that, will the oxide diffusion mask is completely removed from the semiconductor structure, with new ones being made Oxide layers applied to the gas phase for the diffusion of the emitter zone of the transistor into the Structure to be made. The emitter zone of the transistor is then through a window in diffused into the oxides applied from the gas phase Then there is a very thin protective layer on the surface of the oxides applied from the gas phase produced, with a window in the surface oxides to expose a base contact area is trained. The thin oxide layer is then removed from the emitter zone by controlled etching of the transistor removed in order to facilitate their ohmic contact. In the case in question the emitter-base-nn-junction of the transistor will never again be after the production of the emitter zone exposed. The finished structure has a protective passivating oxide layer of uniform thickness on their surface. This uniformly thick oxide layer facilitates the subsequent application a layer of metallization on the surface of the structure, eliminating the disadvantages of stepped Oxide layers are avoided.

FIG. 1 shows a substrate or a starting semiconductor material 14. For example, a substrate 14 made of relatively high-resistance p ~ material is assumed. In the following, semiconductor material of p-, p- and p ⁺ -conductivity type is referred to as material 'of a conduction type ", while n ⁺ and n-conductive

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Material is referred to as material of the `` opposite conduction type ''.

Using either thermal oxidation or gas phase oxidation, an oxide layer 16 is deposited over the entire surface of the substrate 14-. A window 19 is then produced in the oxide layer 16 using photolithographic processes known per se. Because of this window 19, the oxide layer 16 serves as a diffusion mask for producing "an n ⁺ - ■ 'buried layer" 18. A so-called "buried layer" of this type is known per se in semiconductor technology. The buried layer 18 enables the use of a relatively high-resistance epitaxial layer for the collector of the transistor, with a small collector capacitance being ensured. At the same time, the collector-emitter saturation voltage Vq-d eßATO is kept ^{at a} relatively low value. The high collector sheet resistance experiences a shunt due to the small sheet resistance of the diffused buried layer 18, which results in an extremely small collector series resistance and thus a low collector-emitter ■ saturation voltage. After completion of the diffusion for the n ⁺ -buried layer 18, the thermal oxide layer 16 is removed, for example by using an etchant containing hydrofluoric acid (HF). -

According to Figure 3 is on the surface of the substrate 14 · and the surface of the buried layer 18 is an n-type Layer 21 applied epitaxially. One of those

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epitaxial process is known per se in semiconductor technology. An oxide layer 22 is produced on the finished epitaxial layer 21 either by thermal oxidation or by application from the gas phase. Windows 24, 26, 28 and 30 are made in this oxide layer. The windows 14 and 28 enable a p ⁺ dopant, such as boron, for example, to be diffused through the epitaxial layer 21 into the surface areas of the substrate 14. This diffusion produces a coherent circular ring 32 which provides an insulating pn junction for the integrated structure represents according to the invention.

In many integrated circuits it is desirable to produce ^{one or more diffused resistors 31 together with the production of the p +} insulation zone 32 and the p-conducting base zone 32 of the transistor. The p ⁺ -Isolationsζone 32, the diffused p ⁺ -resistor 31 and the p-conducting base zone 34- are only examples of many possible p-diffusions and p ⁺ -zones for ohmic contacts (not shown), which can be produced simultaneously in one diffusion step. Therefore, many transistor isolation regions and diffused resistors can be produced simultaneously in an integrated structure by a single diffusion step.

After the completion of the p-diffusions shown in FIG. 4 , the oxide mask is thinned on the surface of the semiconductor structure by using an oxide etchant, such as, for example

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Hydrofluoric acid (HP) removed. Then it is applied to the surface A new oxide diffusion mask is produced from the semiconductor structure, as shown in FIG is shown. The one described above, shown in FIG Oxide mask is referred to below as the first mask, while that of individual oxide layers existing oxide mask according to FIG. 5 is hereinafter referred to as the second mask ". The materials for the first and second diffusion mask according to the invention are not limited to pure oxides * '' Various other mask types, e.g. made of mixed oxides, oxides doped with phosphorus, For example, mixed oxides, oxides doped with phosphorus and nitrides can also be used in the context of Invention can be used.

According to FIG 5, a first deposited from the gas phase oxide layer 36 is prepared, for example in that the epitaxial layer is a gaseous mixture of oxygen and silane at atmospheric pressure and a relatively low temperature in the range of about 359 ° 0 exposed to 900 ⁰ O. The deposition temperature is preferably in a range from A-OO ⁰ C to 500 ⁰ C. A layer of oxide 38 doped with phosphorus is then applied to the oxide layer 36 in that it is a gaseous mixture of silane, phosphine and oxygen at atmospheric pressure and a relatively low deposition temperature between about 400 ⁰ C and ⁰ C is 4-5O .ausgesetzt. The thickness of the oxide layer 36 is typically in the order of magnitude of 5000 Å, while the thickness of the oxide layer 38 doped with phosphorus .; typically

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M97P-356 is on the order of 500 to 2000 2nd.

After applying the oxide layer 36 and the with Phosphorus doped oxide layer 38, with a total thickness of about 0.2 microns, is placed on the surface of oxide layer 38 using known photolithographic techniques Method applied a photo mask 40. A window 42 is made in the photo mask 40 produced, then the oxide exposed through this window by etching by means of a suitable Oxide etchant, such as dilute hydrofluoric acid, is removed. If the through the window 42 removed the exposed part of the oxide and thus the underlying part of the epitaxial Layer 21 is exposed, the photomask 40 is doped with phosphorus from the surface Oxide layer 38 removed.

Thereafter, an n-dopant with the opposite conductivity type to the base zone 34 is in a part of the zone 34 to form a Emitter zone 48 of the transistor to be produced diffused. During the diffusion of the emitter zone 48 in the semiconductor structure, a thin layer 50 of phosphosilicate glass is thermally applied the surface of the second zone 48 and the exposed surface of the oxide layer 38 is grown. This thin layer 50 of phosphosilicate glass minimizes the diffusion depth of the emitter zone 48, which ensures that this emitter zone 48 is very close to the surface.

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Such a near-surface emitter zone is required for transistors with short switching times.

The thin layer 50 of phosphosilicate glass is now according to FIG. 7 with a photo mask. 52 covered »with windows 5 ^ and in this photo mask 52 using known photo etching processes are made »these windows 54 and 56 lay Portions of oxide layers 36, 38 and 50 free the are to be removed in a subsequent etching step.

By using an oxide etchant such as; diluted elusic acid, windows 58 and (Figure 8) produced; at this stage of the proceedings are all p-leltenden to be contacted Zones by similar etching of the oxide layers 36, 38 and 50 to expose. As stated above, are the transistor shown in the drawing and the resistance shown is only an example of many possible active and passive elements - which one at the same time using the in question Process integrated in a monorithic Circuit- can be made. Are: the windows and 59 according to FIG. 8 in the oxide layers 36, 38 and 50; the photomask 52 is made under Use ^ of a fetal sec- ond remedy removed. Examples of such etchants are those used in the semiconductor industry under the trade name J * 100 and AZ-IOO are available-, Durelt controlled etching of the thin Layer 5P of phosphosilicate glass can then an emitter window 60 according to FIG. 9 is exposed again be to the subsequent application of a To enable metallization on the emitter surface.

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A controlled etch cycle used to remove thin layer 50 is characterized by the following times, temperatures and materials. First, layer 50 is exposed to chromic acid for about 5 minutes. An etchant available in the semiconductor industry under the trade name 1514 is then applied to the oxide layer 50 for about 15 seconds. This etchant 1514 contains 15 parts ammonium fluoride, one part hydrofluoric acid and 4 parts water (H ₂ O). This etchant results in an etching rate of about 30 Å per second. Then the surface of the structure shown in FIG. 8 is cleaned in a nitric acid bath for about 5 minutes, then rinsed in deionized water and then etched in the etchant 1514 for a little more than 5 seconds. Finally, the structure shown in FIG. 8 is rinsed again in deionized water, after which the structure shown in FIG. 8 results in that shown in FIG.

FIG. 10 shows the applied metallization for an emitter contact 62 and a metallization strip 64 which forms the base zone 34 of the transistor connects to the neighboring diffused resistor '44. The metallization strip 64, which typically made of aluminum, is deposited on the oxide layers 36 from the gas phase and 38 evaporated. This creates an electrical contact between the base zone 34 and the diffused zone Resistor 44, while at the same time insulation to the semiconductor structure by the oxide layers 36 and 38 is created.

It should be noted that the method according to the invention

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not on the manufacture of bipolar transistors is limited. The method can, for example, also be used to produce junction field effect transistors be used. When producing a junction field effect transistor accordingly the above-described structure of the bipolar transistor corresponds to the base zone 34 of the bipolar transistor in the geometry typically the channel zone of the junction field effect transistor. In the same Way corresponds to the emitter zone 48 of the vorbeschrjebenen bipolar transistor of the control zone of the field effect transistor. With a field effect transistor Of course, the metalization grid does not correspond to that of a bipolar transistor, since the first one Zone 34 of the field effect transistor has two contacts as a source and drain electrode on the sides of the channel requires. Such modifications of the contact are known per se.

It should also be noted that the present invention is not limited to diffusion processes is. An ion implantation can also be used instead of diffusion processes to produce active areas Find use in the ions, such as boron ions, in an electric field be accelerated. Due to the high-energy acceleration, the ions penetrate through the window into a mask in the semiconductor surface. Such ions can be used instead of solid-state diffusion can be used to form the two zones in the embodiment described above.

The masking steps described require additional

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the use of photoresist to form the desired oxide pattern on the semiconductor surface. One possible photoresist which can be used for this purpose is available from the Kodak Company at sold under the trade name KLIER. Instead of this masking material, various others can also be used Masking materials used to produce the oxide masks within the scope of the teaching of the present invention will.

Finally, the materials for the diffusion masks are used to limit the side of the diffusion of dopants not necessarily limited to oxides. Different nitrides can also be used and glasses doped with phosphorus, such as phosphorus silicate, as doping masks in the context of the teaching can be used in the present invention.

In summary, it can be said that according to a special Embodiment of the invention in one Semiconductor structure with near-surface pn junctions and short switching times using a base zone of a conduction type in a semiconductor body photolithographic process is produced. After that, one or more oxide layers are made the gas phase produced at relatively low temperatures on the surface of the structure. In the Oxide layers applied from the gas phase then form a window through which a dopant for the production of an emitter zone is opposite Line type is introduced in the base zone. After that, a thin layer of oxide is placed on the exposed Part of the base zone and thermally on the exposed surface of the oxide layers applied from the gas phase

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grew up. One or more windows are then selectively produced in the surface oxide in order to enable electrical contacts to be attached to the base zone of the transistor and further zones of the same conductivity type in the semiconductor structure According to the method described, the thin thermally grown oxide layer is "washed out" from the emitter zone by controlled etching. Such controlled etching does not require a critical masking step, which would otherwise be required to produce the emitter contact for the base and emitter zones can be produced by a conventional method, such as vapor deposition of aluminum, since all of the oxide masking is removed after the production of the base zone, the final O has Oxide masking on the surface of the structure of uniform thickness. ^: '-_ ".-. ■ -'.--

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Claims (7)

M97P-356 Claims •1. Method for producing a semiconductor structure, characterized in that on the surface
of a semiconductor body (14, 21) a mask (36, 38) is formed that a dopant through a window (46) in the mask (36, 38) is formed to form a zone (48) in the semiconductor body (14, 21)
is introduced into the semiconductor body (14, 21) that on the exposed part of the zone (48)
and a thin protective layer (50) is applied to part of the mask (36, 38), that a photomask (52) is applied to the thin protective layer (50), and that the thin protective layer (50) is applied during selective etching of the mask (36, 38) serves as a holder for the photo mask (52). 2. The method according to claim 1, characterized in that for re-exposing part of the zone (48) by forming a new window (60) the thin protective layer (50) over the zone (48) selectively
is removed, whereby the application of an ohmic contact (64) to the zone (48) is possible without further masking and etching steps to expose the surface of the zone (48) again. 3. The method according to claim 1 or 2, characterized in that to form the mask (36, 38) - 18 - one 109816/1321 '201 k 155 M97P-556 a first silicon dioxide layer (36) from the gas phase on the surface of the semiconductor body (14, 21) and on the layer (36) a mixed oxide layer composed of silicon dioxide and phosphorus endoxide (38) is applied from the gas phase. 4. The method according to any one of claims 1 to 3, characterized characterized in that the thin protective layer (50) is thermal by growing a thin layer Oxide on the exposed part of the zone (48) - and on the exposed part of the mask (36, 38) is formed that then the zone (48) for attaching the ohmic contact (64) through selective etching of the thin protective layer (50) is exposed and that the mask (36, 38) during their selective etching to expose further areas of the semiconductor body (14, 21) for the purpose the attachment of further ohmic contacts (64) through the photo mask (52) and the thin protective layer (50) is partially covered for protection. 5. Method according to one of claims 1 to 4, characterized characterized in that prior to the production of the mask (36, 38) a first mask (22) on the surface of the half ~ Conductor body (14, 21) is formed that by introducing a dopant through a window (26) in the first mask (22) a first zone (34) of a conductivity type is introduced into the semiconductor body (14, 21), and that then the first mask (22) is removed from the surface of the semiconductor body (14, 21) and the mask (36, 38) is produced. 6. The method according to any one of claims 1 to 5 _S, characterized in that a plurality of windows (24, 28, 30) are formed in the first mask (22) and that - 19 - to 109816/1321 for the formation of isolation zones (32) or monolithic integrated circuit components (44) of the one conduction type in the semiconductor body (14, 21) a dopant generating the one conduction type through the window (24, 28, 30) in the semiconductor body is introduced. 7. Semiconductor structure produced by a method according to one of claims 1 to 6, characterized through a transistor (48, 34, 21) with stepping to the surface of the semiconductor body (14, 21) pn junctions in the semiconductor body (14, 21), a passivating, applied from the gas phase, the Protective oxide layer (36, 38) covering pn junctions and made of a first layer (36) of silicon dioxide and a second layer (38) made of phosphosilicate on the semiconductor body (14, 21), window (58, 60) in the protective oxide layer (36, 38), which is the emitter and base zone (48, 34) of the transistor uncover and through introduced into the window (58, 60) Metal contacts (62, 64) for ohmic contacting of the transistor. - 20 109816/1321