DE20023747U1 - Memory system for personal computer, has data bus terminator that balances impedance between memory controller and memory device - Google Patents

Abstract

Memory controller (10) is connected to memory devices (D 1-DN) through data bus (12) having impedance (Z 1) between memory controller and memory device (DN) and impedance (Z 2) between memory device (DN) and data bus terminator (14). The active terminator places another impedance in parallel with impedance (Z 2), so as to balance the impedances (Z 1,Z 2). An independent claim is also included for balancing impedance along data bus in memory system.

Description

AREA OF INVENTION

The The present invention relates to high speed storage systems. In particular, the present invention relates to an expandable high speed memory system with an electronically mobile degree.

BACKGROUND THE INVENTION

Constant demand for improved memory performance has led to the redesign of conventional memory systems that allow for significantly higher data throughput. 1 illustrates such a conventional memory system in a simple block diagram. The memory system includes a memory controller (M) for writing data to and reading data from memory devices (D) over a bidirectional data bus. The memory system is configured with at least one memory device but not more than N memory devices connected to the predetermined typical data bus having a predetermined impedance.

The bidirectional data bus has a number of signal lines, but for the sake of simplicity, only one signal line is shown in the drawings. Each signal line terminates at one end with an input / output (I / O) terminal (pin) of the memory controller and terminates at the other end with a terminator (T). The termination (T) resistance is closely matched to the load impedance of the signal line to minimize reflections on the signal line and to absorb signals transmitted along the signal line in the direction of termination. The other end of the termination (T) is connected to a power supply (V _T ) which provides an AC ground and establishes the DC termination voltage on the signal line.

Since the signal line is nominally pulled to the value of the termination voltage, this voltage can serve as one of the logic states for digital signals transmitted on the signal line. Switched current sources, such as open-drain NMOS devices, can then be used as signal driver circuits either in the main or memory devices. These simple signal drivers produce the logical data signals either by turning off or picking up the stream as needed to produce logic states ("1" and "0"). For example, the termination voltage (V _{H I} ) may serve as the high voltage state and low logic state "0", and a low voltage state (V _LO ) may serve as the high logic state "1", where V _LO = (V _T - I _O Z _L ) and I _{O is} the nominal current consumed by a power source driver when it is turned "ON".

The use of this data signaling scheme has at least two advantages. First, no energy is needed to generate one of the logic states (V _LO ). Second, the power source drivers provide high output impedance to the signal line, thereby minimizing the loss of signal energy as signals on the signal line propagate toward the memory devices toward both ends of the data bus.

When the memory controller sends signals to one or more of the memory devices, it "sees" the entire impedance, Z _L , of the signal line and generates full magnitude V _SWING = (V _{HI -V LO} ) signals which propagate along the signal line I / O connections to the memory devices form short, high-impedance stubs, low energy is lost, and minimal spurious reflections are generated as the signals propagate along the signal line and the memory devices pass through. As a rule of thumb, the stubs can be considered short The signals sent by the memory controller propagate along the signal line, pass through all the memory devices where they can be detected, and eventually terminate at the termination.

The situation is a little different when a storage device sends to the storage controller. Each driver circuit in the memory device actually "sees" two signal lines, one leading to the memory controller and the other leading to the terminator Thus, the net impedance seen by each driver circuit is 1/2 Z _L also I _o current, the signals originating from the I / O terminals of the memory device split on the signal line, with half of the signal voltage propagating in the direction of the memory controller and half of the signal voltage in the direction of the termination -V _SWING signals propagating toward the termination pass through each occurring memory device and then terminate only at the matched impedance of the termination, but the half-V _SWING signals propagating in the direction of the memory control pass through each occurring one Storage device and then encounter open circuits when they reach the I / O ports of the memory controllers. This state of actually open circuits causes the signals from the memory device at the I / O terminals of the memory device doubled in voltage because the signal energy is reflected back along the signal line in the direction of termination. Thus, the memory controller nevertheless receives a full voltage oscillation signal at its I / O terminals due to the signal reflection, although only half of the normal signal voltage has been sent by the memory devices towards the memory controller. This is on the premise that the signal line on the memory controller is terminated with a high impedance (ie, an open circuit). The other memory devices in the system see half-normal amplitude signals that pass their I / O ports at least twice per memory device transfer. However, since the memory system is designed to send data from a memory device to the memory controller and not between the memory devices, this signal line state is acceptable. Consequently, a full wave signal appears at the input of the intended receiving device, regardless of which device in the storage system is transmitting data.

The foregoing description has been made with reference to the exemplary, in 1 illustrated storage system and in the context of individual, a data bus bus-mounting storage devices (D) made. However, practical storage systems often populate the data bus with memory modules rather than individual memory devices. Accordingly, as in 2 As illustrated, each branch along the data bus may be occupied by a memory module having a plurality of individual storage devices.

If the memory system the data bus with memory devices or with a plurality of memory devices owning memory modules stocked, Each storage device is specifically assigned in the system and later indicated by a device identification (ID). Every storage device For example, a device identification (ID) register which of the memory controller after a memory system initialization is assigned a unique device ID. During later storage system operations Each storage device is activated and transfers data to the storage controller in accordance with the device ID.

As From the foregoing, the impedance of the memory system is a critical system design and performance parameter. If missing careful balance between the various components of the storage system mentioned above, the signal line impedance will deviate from its desired impedance. Mismatching the signal line impedance becomes undesirable Signal reflections at the conclusion and to increased, with such unwanted Reflections associated signal line noise. Increased signal line noise can in some cases the distinction of data signals on the memory devices or prevent the memory controller.

The Need to adjust the signal line impedance so far the implementation of a truly expandable high-speed storage system locked out. This means, because the signal line impedance necessarily coincides with additional, by connecting additional storage devices or memory modules changed load on the data bus needed the Storage system extension a high degree of technical support and significant hardware-level interventions, such as swapping of the existing degree against a new degree, which is a with the additional burden has compatible impedance.

alternative can be a physically movable conclusion between the stocked, one first impedance section of the data bus and the unpopulated, with a predetermined impedance completed and a second, from the first different impedance section of the data bus be attached. This physically mobile degree, or Impedance compensating connector, is inserted in the first unoccupied "slot" (slot) on the data bus to a maintain appropriate data bus impedance under variable load conditions. The U.S. Patent 4,595,923 this procedure closer.

Both this conventional A method of maintaining signal line impedance, which includes connecting additional ones Track devices need direct technician intervention. That means, a trained technician the one special, additional Part (i.e., a new conclusion or impedance of the same Connector) is needed to maintain the signal line impedance and the extra Compensate signal line load.

In a commercial marketplace, where customers demand the ability to customize storage system capacity to customer needs and / or field-upgrading storage system capacity, the need for direct technician intervention is unacceptable. Workstation (PC) manufacturers also require an easily definable and easily expandable storage system that can be configured in the factory with just about any reasonable number of storage devices without the cost to adapt or compensate for variable signal line impedance issues.

SUMMARY THE INVENTION

The The present invention provides an easily expandable high speed storage system. For storage systems, along a variety of memory devices, memory modules or slots Include the data bus, an extension is provided. By the use of an active completion can be a memory control balance the data bus impedance if one or more additional Memory devices, memory modules are added to a storage system.

In In one aspect, the present invention provides a storage system ready, which has; one with a plurality of storage devices (or Memory modules) via memory controller connected to a data bus, wherein the data bus a first section having a first impedance and a second one Section having a second impedance, wherein at least one the plurality of memory devices (or memory modules) one active termination having a third impedance, so that at the activation of the active termination the third impedance in parallel is arranged to the second impedance to the first and the second Balance impedance.

In In another aspect, the present invention provides a storage system ready, which has; a memory controller connected to a data bus, wherein the data bus has a plurality of slots, each one Slot is adapted to accommodate a memory module, and a has active termination responsive to a control signal from the Memory control responds.

In Still another aspect, the present invention Method of equalizing the impedance between a first and a a second section of a data bus in a storage system ready, wherein the memory system, a memory controller and a Has a plurality of memory devices, which has a serial initialization line and a data bus containing channel associated with the method; Determine one the data bus last arranged memory device in the memory controller and Activating an active termination in the one storage device, to balance the first and second sections of the data bus.

SUMMARY THE DRAWINGS

1 Fig. 10 is a block diagram of a conventional memory system incorporating memory devices on the data bus;

2 Fig. 10 is a block diagram of a conventional memory system incorporating memory modules on the data bus;

3 Fig. 10 is a block diagram of a memory system incorporating memory devices in accordance with the present invention;

4 Fig. 10 is a block diagram of a memory system incorporating memory modules according to the present invention;

5 Fig. 12 is a schematic diagram illustrating another aspect of the present invention in which an active termination is associated with a data bus slot;

6A and 6B show exemplary circuits implementing the active termination used in the present invention; and

7 Fig. 10 is a block diagram illustrating the control connections between the memory controller and a plurality of memory devices in a memory system according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

It a high-speed storage system is disclosed which has a includes electronically movable financial statements. The electronic movable termination is a switchable component, preferably a memory device, a memory module or a with a Memory system data bus associated Slot is assigned. The term "data bus", which is used throughout, denotes a or multiple signal lines through which data between a Memory controller and one or more storage devices or one or more memory modules are transmitted. It is noticed that the actual Data bus is part of a longer one Channels can be, what additional Contains signal lines, the Convey address and control information or which is a multiplexed one Group of signal lines, the data information, control information and convey address information.

Of the Term "memory control" is used around a broad class of generic and application-specific Describe processing devices that are capable of data read from one or more storage devices and data to write in one or more memory devices.

The Phrase "electronic movable "is used about the ability of the switchable component to be described by the memory controller or some other command devices sent control signals to appeal.

These Phrase also serves to differentiate between the present Invention and the above explained, usual, emphasize physically movable termination components.

conceptional the present invention provides a system and method by the number of memory devices, memory modules or data bus slots be implemented with the preceding switchable component. The switchable component can take any shape, and several Examples are given below. Regardless of their actual Form or the type of institution in which it is incorporated the switchable component is referred to as an "active completion" each of the memory devices, memory modules or data bus slots, the includes the active completion may by the storage device switched or "activated" to be the right one Memory system operation to provide necessary data bus impedance.

typically, Each storage device or storage module takes one Active completion so that "standard" parts are made and everywhere along of the data bus can be placed without using the data bus impedance related Distinctions. Is the data bus once with a suitable number memory devices or memory modules has been populated the last of these devices activates their active completion have, i. switched to ON. This system and procedure will be described below with respect to several exemplary embodiments explained in more detail. The embodiments are taken from currently preferred storage system configurations. They have been simplified in many ways to the following Discussion of the present invention and not to others well understood To address aspects of storage system design. The examples must be in given context to be useful. However, that is the present invention is not limited to the teaching context or the specific, exemplary, presented here embodiments limited. Storage System Design is a flexible and evolving by its special kind Aspiration. Thus, many variations of the simple, below given examples within the scope of the present invention, as defined by the following claims.

3 is a block diagram of a memory system according to the present invention, in which a memory controller 10 with a variety of storage devices 20 (D ₁ , D ₂ , ..., containing D _N ), each memory device having an active termination 21 includes. The storage devices are through a data bus 12 connected and along a data bus 12 positioned, which in a connected to a terminal voltage V _T conclusion 14 concludes. The impedance along the data bus 12 can be considered as having two components; a first component Z ₁ between the memory controller and the "last" memory device D _N and a second component Z ₂ between D _N and the data bus termination.

The term "last" or storage device "D _N " will be used in the following examples to show the last storage device (or memory module in later examples) mounted on the data bus. Conventionally, this memory device is mounted in a position farthest from the memory controller along the data bus. However, this is just a present convention that is adapted to minimize the signal propagation time between the memory controller and the memory devices on the bus.

The impedance Z ₁ is typically different from the impedance Z ₂ . Ideally, Z ₁ and Z _{2 should have} the same impedance to avoid unwanted signal reflections on the data bus and unbalanced signal propagation through the memory devices on the data bus. The presence of an active terminator in the memory device D _N provides the memory system with the ability to equalize the impedances and balance the respective portions of the data bus. In fact, Z ₁ = Z _{A T} ‖ Z ₂ , where Z _{A T is} the internal impedance of the active termination in the memory device D _N when it is turned ON. In a presently preferred example, the combined load impedance for Z _{1 is} about 25 ohms. The impedance of Z ₂ is typically 50 ohms. Accordingly, the impedance Z _{AT is} defined as 50 ohms.

Thus, once the data bus is populated with a desired number of memory devices, the active termination of the last memory device is activated to equal Z ₁ and Z ₂ . The data bus impedance is not dependent on a statistical, predefined number of memory devices arranged along the data bus. Furthermore, if one or more additional memory devices are added to the data bus, there is no need to change the data bus terminator (T) or be physically busy moving completion on the data bus. Rather, in the system initialization following attachment of additional memory devices, the memory controller recognizes the new "last" memory device D _N and sets the corresponding active termination to ON recognizes and identifies the storage system.

An analogous example in which the memory system has one or more memory modules 30 (B ₁ , B ₂ , ..., B contains _N ) is in 4 shown. Here, each memory module preferably has one or more memory devices (D ₁ , D ₂ , ..., D _N ) and an active termination 31 on. Many memory systems rely on various engineered memory modules to provide sufficient data bandwidth for memory control during read / write operations, memory system redundancy, and so on. Each memory module is connected to the data bus via a slot. The term "slot" is used to generally indicate any electrical and / or mechanical assembly that operatively connects a memory device or module to the data bus slot. "Slots include interfaces (ports), chip sockets, parallel connector pairs, etc. Typically a data bus configured to receive one or more memory devices or one or more modules includes a corresponding number of slots.

In the present invention, the active termination on the last memory module B _N is turned ON by the memory controller during memory system initialization. Thus, Z ₁ and Z ₂ are assimilated as described above to eliminate unwanted signal hitting on the data bus.

Alternatively, the active terminator may be associated with each slot along the data bus, as in FIG 5 is shown. Here, the storage system references each data bus slot 40 an active degree 41 instead of relying on the storage device or module (which may be manufactured by a number of different vendors) to provide the active termination. The last memory module filled (or populated) slot receives a signal from the memory controller during memory system initialization to toggle active termination to ON.

Active completion itself can be implemented in many ways. 6A and 6B are simple examples of the active termination implementing circuits. In 6A the circuit comprises a resistance device 51 with a selected resistor approximating the desired impedance Z _{A T} , and a switching element 50 receiving a control _signal V _Cntrl from the memory controller. Similarly, the in 6B shown circuit only one of the desired impedance Z _AT bereitstellendes switching element 53 on. In each of the examples, the circuit between the terminal voltage V _T and the I / O terminal is connected to the data bus from the memory device, the memory module or the slot. A coupling capacitor may be included in these circuits between V _T and the switching element to reduce the ON current.

The activation or switching of the active termination can be achieved by the memory control in various ways. For example, the in 7 shown memory controller 70 a serial initialisation line (SIL) 72 or a channel 71 to communicate an active terminal enable signal to each of the memory devices D ₁ , D ₂ , D ₃ , ..., D _N.

Typically, the SIL or the like, the memory devices with the memory controller outside a channel 71 connecting signal line used to assign a unique identification number to each memory device after a memory system initialization. Once the memory system initialization is complete, the memory controller knows which memory device (D _N ) is the last one on the data bus. With this information, the memory controller releases active termination in D _N using the SIL. Alternatively, an appropriate command from the memory controller may be sent to the memory device D _N via the control / address portion of the channel to enable the active termination. This instruction may be accompanied by data on the data bus portion of the channel depending on the designation of the particular instruction. Once received in a memory device D _N , the enable command may cause activation of the active completion by a register value of a stored data value. Each of the signaling schemes may be applied to an active termination in a memory module or slot.

Whether the active terminator has been switched in the last memory device, the last memory module, or the last populated slot, memory devices on the data bus "see" balanced impedances as between sections of the data bus going in the direction of memory control and data bus termination explained ½V _SWING signaling scheme well the matched impedances exclude unwanted signal reflections on the data bus, thereby eliminating a potentially significant noise source.

Claims (17)

Integrated semiconductor memory device, wherein the storage device comprises: a register to save a value indicating whether a deal is in the storage device is to be activated; a data pin for receiving data; and a conclusion to complete the data pin in accordance with the value, where: the conclusion associated with the data pin if the value indicates activation of the deal; and of the Termination is disconnected from the data pin if the value is a deactivation of the financial statements. The memory device of claim 1, wherein the termination contains a semiconductor resistor. Storage device according to claims 1 or 2, wherein the termination includes a capacitor. A memory device according to claim 1, 2 or 3, wherein the termination between a switch and a voltage connection coupled, wherein: the switch completes with the data pin connects if the value indicates activation of the deal; and the switch disconnects from the data pin when the value indicates a deactivation of the financial statements. The memory device of claim 4, wherein the switch is a semiconductor transistor. Storage device according to one of the preceding Claims, further comprising a plurality of additional statements, and a lot of extra Data pins, where for every additional one Data pin of the multitude of additional data pins and a corresponding additional degree the multitude of additional ones statements: of the additional Graduation with the additional Data pin is connected if the value is an activation of the additional Indicating completion; and the additional conclusion of the additional Data pin is disconnected if the value is a deactivation of the additional Completion indicates. Storage device according to one of the preceding Claims, further comprising a control pin for receiving a control signal, the control signal and the value stored in the register both indicate whether to enable completion in the storage device is. Storage system with: a memory controller, the above a data bus connected to a plurality of memory devices wherein the data bus is at a first end in the memory controller and terminating at a second end at a terminating resistor; in which the data bus has a first section with a first impedance and a second portion having a second impedance; in which at least one of the plurality of memory devices has an active one Termination having a third impedance, so when activated of the active termination, the third impedance parallel to the second Impedance is placed to compensate for the first and second impedances. The memory system of claim 8, wherein each of the plurality of memory devices active completion with the third Has impedance. The memory system of claim 9, wherein the plurality of memory devices between the first and second ends [along] of the data bus is arranged by a first memory device, the closest to each other to the memory controller, to a last memory device, which is farthest from the storage device. The memory system of claim 10, wherein the memory controller a first circuit for identifying the last memory device and a second active termination activation circuit in the last memory device. Storage system with: a memory controller, the above a data bus is connected to a plurality of memory modules; in which the data bus has a first section with a first impedance and a second portion having a second impedance; in which at least one of the plurality of memory modules active termination having a third impedance, such that upon activation of the active termination, the third impedance parallel to the second Impedance is placed to compensate for the first and second impedances. The storage system of claim 12, wherein each of the Variety of memory modules active completion with the third Has impedance. The memory system of claim 13, wherein the plurality of memory modules are along the data bus is located from a first memory module closest to the memory controller to a last memory module farthest from the memory device. The memory system of claim 14, wherein the memory controller a first circuit for identifying the last memory module and a second circuit for activating active termination in has the last memory module. Storage system with: a memory controller, which is connected to a first end of a data bus; one Terminator connected to a second end of the data bus connected is; wherein the data bus has a plurality of between has slots arranged on the first and second ends of the data bus, wherein each slot is adapted to receive a memory module and a responsive to a control signal from the memory controller has active completion. The storage system of claim 16, further comprising a number of memory modules arranged in adjacent slots are from a first memory module that is closest to Memory controller is located, to a last memory module, the is furthest from the memory controller; in which the memory controller further comprises: a first circuit to capture a last occupied slot containing the last memory module stops, and a second circuit for applying the control signal to one with the linked last occupied slot active degree.