DE2000882A1 - Digital-to-analog converter - Google Patents

Description

IBM Germany Internationale Büro-Maichinen Getellichaft mbH

Applicant:

Official, file number:

Applicant's file number;

Boeblingen, January 8, 1970 ne-gn-sk

International Business Machines Corporation, Armonk, N.Y. 10504, USA

New registration

Docket YO 968 062

Digital-to-analog converter

The invention relates to a circuit for generating an analog Phase signal from digital input data. In particular, it relates to a circuit that converts digital input data into a signal generated to control the movement along one or more axes of one or more numerically controlled machine tools, which signal has a variable phase shift with respect to a reference signal.

It is known, the control information the control circuits for each Movement axis of a machine tool in the form of two square-wave signals to feed. One of the square-wave signals serves as a reference signal and has a predetermined frequency, while the other Right corner signal is a control command β signal that has a variable phase shift compared to the reference signal shows «The changes in

008832/1689

this phase shift is related to the desired relative movement between the workpiece and the cutting head of the machine tool.

The reference signal forms the basis of the time control for all axes the machine tool. It is usually obtained by monitoring the top level of a reference counter that ends with a swinging free Reference oscillator is connected. The reference signal has a frequency that is the frequency divided by the number of stages of the reference counter of the reference oscillator. For each axis of the machine tool an axis position counter is provided with an input also with is connected to the reference oscillator. More input signals for everyone Axis position counters are supplied together by a linear interpolation circuit. Provide these additional input signals Represent pulse trains containing the distance and direction information. Depending on the desired direction of movement, the Pulses containing the distance information are either added to or subtracted from the content of the axis position counter. That The control command signal is obtained by monitoring the highest level of the Axis position counter received.

A disadvantage of the prior art described above is that That an axis position counter is required for every axis of the machine tool · Also, it does not become part of any axis position counter shared by another axis position counter

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since a common reference oscillator has a frequency of the order of magnitude of 250 KHz, each axis position counter will be able to Perform additions and subtractions at a speed which is greater than 250,000 operations per second so that it can both can sum the reference pulses as well as the incoming range pulses.

The disadvantages mentioned are for a digital-to-analog converter for a numerically controlled machine tool system with a device for generating a control command signal that is in the phase is shifted with respect to the reference signal, thereby avoided that it s according to the device for generating a control command signal from an n-stage connected to a source of input data Phase control register consists of an n-stage adder whose first inputs are connected to the η stages of a reference counter, in a manner known per se from a. Reference oscillator fed and whose highest level supplies the reference signal, and whose second inputs are connected to the levels of the phase control register, while the highest stage of the adder is the trigger input of a bistable flip-flop element and a NOT element to its reset input connected.

According to a further feature of the invention is for each axis of movement of the machine tool system, a phase control register and a bistable flip-flop are provided and the phase control registers are

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each other via gate circuits with the first inputs of the adder and the bistable flip-flops can be connected to the highest output of the adder via gate circuits in the same time sequence.

An advantage of the circuit according to the invention is that the k adding unit is common to the devices for several axes of movement of the machine tool. Since the adder is generally the most expensive and complicated part of the system, its division among the devices for several axes reduces the overall cost and complexity of the digital-to-analog converter.

Another advantage of the invention is that the phase control registers Received input pulses of a much lower frequency than the prior art axis counters. For this reason can be used for phase control! ^ circuits for low speeds which are not that expensive.

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Docket YO 968 062

200088?

Further details of the invention emerge from the more detailed description of preferred exemplary embodiments in conjunction with the drawings of which shows:

Fig.1 is a general block diagram of a

numerically controlled machine tools ™ systems;

Pig.2 is a block diagram of a digital-to-analog converter according to the invention for a single axis of a machine tool;

5 shows a reference signal with control command signals of different phase shifts;

4 shows a preferred embodiment of the

Invention that provides steep command signals for five different machine axes;

FIG. 5 shows another exemplary embodiment of a device for transmitting clock pulses to various gate circuits which are contained in the system shown in FIG .

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1 shows a block diagram of various elements of a numerically controlled machine tool system according to the prior art. An interpolation circuit 1 receives the numerical data indicating the distances to be traveled along each axis for rectilinear machining. From this data, the interpolation circuit generates a series of pulses for each movement axis, in which each pulse indicates a movement step. In addition, the interpolation circuit generates a signal for each axis which indicates the direction of movement. A reference oscillator 2 supplies signals for a reference counter 3, the highest stage of which generates a square-wave reference signal on line 4. The output of the reference oscillator 2 is also connected to an X-axis counter 5 and a Y-axis counter β. (In the case of a machine with more than two axes, there would also be a counter for each additional axis). The X-pulses and the direction control signals of the interpolation circuit are fed to the X-axis counter 5. The / axis counter 6 receives the Y pulses and the direction control signals of the interpolation circuit. The pulses received by the interpolation circuit are added to the counter readings or subtracted from them in accordance with the appropriate direction control signals. The highest level of the X-ache counter is used to generate a rectangular a X-relationship ail on the line 7. The highest level of the Y-axis counter is used for this. Docket YO 968 062 0 0 9 8 3 5/16 89

on line 8, a square-wave Y-setting command signal to create. The reference signal on line 4 and the Control command signals on lines 7 and 8 are fed to the safety control units and the machine tool 9. Within the control circuits and the machine tool provides the variable phase shift between one Steep command signal and the reference signal the control information for driving a movable guide carriage. Within the control circuits and the machine tool there are phase discriminators, position sensors, amplifiers, pulse shaping circuits and devices for movement of the workpiece or the cutting head. All of the mentioned ingredients are known and therefore need here not to be described.

The invention relates mainly to the in Pig.1 between the interpolation circuit 1 and the control circuits and the machine tool 9 shown device. A simplified form of the device according to the invention is shown in FIG. It consists of one free-running oscillator 10, which has a reference counter 11 feeds, the highest level of which is monitored in order to generate a reference signal on line 12. A phase control register 1J receives its input signals from the interpolation circuit 1 and counts according to the

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Docket / 0 yo8 062

carried direction control information forwards or backwards. A parallel adder 14 receives its input signals from the reference counter 11 and the phase control register 13 * wherein the highest stage of the adder is monitored in order to generate an actuating command signal. A bistable

W flip-flop 15 serves as a buffer store for the steep command signal. In order to trigger the bistable trigger element 1p, the highest stage of the adder 14 is connected to the trigger input and via an inverter 16 to the reset input of the bistable trigger element 15. The "1" output 17 of the bistable flip-flop 15 supplies the control command signal. It should be noted that the phase control register 15, instead of counting individual pulses supplied to it, could also receive a number from the source for the input data,

fc which corresponds to the count at which a change in the Steep command signal is desired. Although in the following description the phase control registers are used as counters are described, it is clear to those skilled in the art that this term also includes the case where a Number is fed to the phase control register. This number would of course be fundamentally changed after every change of the positioning command signal.

The mode of operation of the circuit according to FIG. 2 is now under With reference to the Sicnaldiagrams of Fig. 3 explained.

Docket YO 908 ü62 009832/1689

In the explanation of FIG. 5 it is assumed that the reference counter 11, the phase control register and the adder 14 are three-digit binary devices. The output signals (the reference signal or the control command signal) generated by the highest stage of the reference counter 11 or the adder 14 are arbitrarily defined as "high" output signals when the device is in one of the states 0-5 and as "low" Output signals when the device assumes one of states 4-7. In FIG. 3, the signal a reproduces the reference signal generated on the line 12 of FIG. It is high during time periods 0-5 and low during time periods 4-7. Signals b, c, d and e are command signals generated on line I7. They have a phase shift with respect to the reference signal a, which depends on the content of the phase control register I5. As the signal b shows, the control command signal is exactly in phase with the reference signal if the phase control register I5 contains one. As the signal c shows, when the phase control register 15 counts up to the value 1 (or counts down to the value -7) the control command signal, which was derived from the highest Stufci dea adder 14 , after adding the content of the reference counter 3 and the Contents of the phase control register 15 ahead of the reference signal by one time period (or by 7 time periods -, 0

after). The signals d and e show control command signals that is obtained when the phase control register I3 up to the value 2 counted up (or counted down to the value -6) and counted up to the value 5 (or up to the value -3 counted backwards). In the case of the signal d, the control command signal is applied Two units ahead of (or six units behind) the reference signal. As the signal e shows, the steep command signal leads the reference signal by five units (or by three time units). As shown in Fig. 3, the control command signal has which is generated by the circuit of Figure 2, a phase shift with respect to the reference signal, the is the same as that generated by the prior art circuit shown in FIG.

The simplified version: - · generated in the game according to Fig.2 only a single steep command signal. In this case, the buffer store (the bistable flip-flop 15 and the inverter 16) is not required for the control command signal. However, as will be described in more detail below, In the preferred embodiment of the invention, the adder 14 is common to a plurality of phase control registers and therefore a buffer memory is generally required for each actuating command signal.

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YO Q68 062

4 shows a preferred embodiment of the invention, which generates a steep command signal for each of five machine tool axes, which is an analog signal identifies the phase. The axes can relate to one or more machine tools. For example the output signals of the circuit according to Pig. 4 ' Feed two different machine tools, one of which has three axes and the other two axes.

A free-running oscillator 18 is provided for generating a reference signal and feeds a reference counter, the highest level of which is monitored in order to generate the reference signal. A parallel adder 20 is fed by the reference counter 19. For the correct counting of the pulses indicating the distance for each machine axis, five phase control registers 21-25 are provided, one for each axis. The contents of each phase control register can be fed to the parallel adder 20 via one of the gates 26 - J> 0. Each of the phase control registers 21-25 receives distance and direction pulses from an interpolation circuit.All phase control registers can either be fed by an interpolation circuit or the registers are combined into groups (generally one group for each machine tool)

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obtained from an interpolation circuit. Of course, instead of counting pulses, numbers from a suitable data source could also be fed to the phase control registers. In order to provide a buffer memory for each control command signal, five bistable circuits 31-35 are provided. The trigger input of each of the bistable circuits 31-35 is fed via a gate circuit 36-40 from the highest stage of the parallel adder 20. The reset input of each of the bistable circuits 31-35 is connected to the output of an inverter 46-50 via a gate circuit 41-45 whose Kinganc is connected to the highest stage of the adder 20. To supply the control signals for the gate circuits of the system according to FIG. 4, the free-running oscillator 18 is connected to a circuit 5I which generates a short clock pulse each time it receives a singing pulse. (Circuit 5I can also include a frequency divider, as will be described below ). The clock pulses generated by circuit 5I are applied to a series of delay elements 52-56, each of which, except for the last, is connected to a subsequent delay element. If the various gates of the system must be actuated once during each reference cycle, then the sum of all of the delays introduced by delay elements 52-56 should be

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Docket / 0 9OCJ OGcl

be less than a reference period (usually 4 microseconds). The clock pulse generated on the line 57 is delayed by a time unit, the clock pulses on lines 58-6I are by 2, 3, 4 and 5 units of time, respectively delayed. The reason all clock pulses are delayed is because it allows is to query the various registers that feed the adder 20 only after their content has been checked by a Input pulse has been increased (or decreased).

Assuming that all query operations are done once while each reference period is to be made, the circuit according to Fig. 4 operates in the following way: Increase the pulses supplied by an interpolation circuit (or several interpolation circuits) (or decrement) the contents of each of the phase control registers 21-25. The impulses of the free-swinging oscillator 18 continuously increase the content of the reference counter 19 · The highest level of this counter is monitored for a bus signal on line 62, (if polling once takes place per period, the delay element 63 can be omitted). The content of the reference counter 19 forms one input variable for the parallel adder 20 Every reference cycle is a short clock pulse at the output of circuit 51 generated. The clock pulse reaches after

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short delay by the delay element 52 the line 57 the gates 26, 36 and 41. The Clock pulse opens the gates 26, 36 and 41, see above that the content of the 'phase control register 21 to the second Input of the parallel adder 20 is supplied. If the sum of the contents of the payer 19 and the register 21 fails so that the highest stage of the adder 20 contains a 1, the bistable flip-flop 31 is triggered, when the sum of the contents of the counter 19 and the register 21 is such that the highest stage of the adder 20 contains a 0, the bistable flip-flop 31 is reset. The output signal of the bistable trigger element 31 forms the steep command signal for an axis of a machine tool. Since each of the delays introduced by delay elements 52-56 is slightly greater than the duration of the clock signal, the gate circuits 26, 36 and 41 have been blocked again before a second clock signal appears on line 58. The clock signal on line 58, delayed by two time units, opens the Gate circuits 27, 37 and 42 to the contents of the, phase control register 22 to be fed to the second input of the parallel adder 20. The bistable flip-flop 32 is then triggered or reset according to the state of the highest stage of the adder 20. In the following parts of the reference cycle, clock signals appear on the lines 59, 60 and 61 to successively select the associated groups

to switch through gate circuits (28,38,43), (29,39,44) and (30,40,45) so that they trigger or reset the ^{bistable flip-flops 33> 3 j +, 35 assigned to them.} It may be desirable to provide additional delay elements (not shown) to additionally delay the clock signals that control the gates at the inputs of each of the bistable flip-flops 31-35 to ensure that the correct sum has been generated by the parallel adder 20, before the content of the highest stage of the adder is ^{switched through to the trigger and "11} UCkSe set inputs of the bistable flip-flops. The output signal of each of the bistable flip-flops 31-35 is fed to the ocrvo control circuits for the axis of the machine tool assigned to it.

In the machine tool system commonly used is (the frequency of the generated by the reference oscillator 18 Pulses often in the order of 250 kHz and the frequency of the reference signal and the control command signals is generally about 250 Hz. Since the reference signal · and the control command signals in comparison to the If the signal of the reference oscillator changes slowly, it is at the use of the invention is generally advantageous to use the contents of the various phase control registers query a speed that is slightly lower than the frequency of the reference oscillator. This can

O62QQ9832 / 16 69

Conveniently this can be achieved in that a frequency divider is provided within the circuit 51 which generates an output pulse after it has been supplied with a predetermined number of input pulses. In this case the total total delay achieved by the delay elements 52-56 could be greater than one period of the reference oscillator 18. An advantage of this solution is that for all the circuits according to FIG. ¹ I with the exception of the reference oscillator 18 and the Bjzugszählers I9 circuits can be used which operate relatively slowly and are therefore cheap. A possible disadvantage of this approach is that the phase shift between a given command signal and the reference signal may not be exactly that which is desired. If, for example, each of the gate circuits of the system switches through once for every n reference cycles (ie that the frequency divider within circuit 5I divides by a factor of 10), the time at which a given steep command signal changes its state can be delayed by an amount which corresponds to up to ¹ J periods of the reference oscillator 18. On average, the delay for a given change in the state of a given control command signal would in this case correspond to 4.5 reference periods (18 microseconds if the reference oscillator has a frequency of 250 KHz). When the interpolation circuit (or the interpolation circuits) match the phase control registers d \ - 25 pulses with a

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maximum speed of 10 KHz are supplied, the total phase error contained in a given steep command signal would be equivalent to an error of no more than one movement step along an axis in the machine tool for a given linear machining. This error would be within % of generally accepted tolerances. If, however, it is desired to approximately compensate for the phase error, the train signal could be delayed by a delay element 63 by a period of time which corresponds to the average delay of the control command signal. In the case of the example given above, the delay element 65 should cause an 18 microsecond delay. Hand out of the maximum phase error for a given otellbefehlssignal of J6 microseconds j (corresponding) periods of the reference oscillator), the maximum error + or-i8 microseconds would be.

other Möglichkii it, clock pulses relatively low frequency to obtain, would consist of the clock pulses to one of the outputs of the bistable flip-flops to decrease 19 of the reference counter, it tfonn eg desirable would be to the various gates shown in Figure 4 after every thirty-second Inipuln of B; to switch oBzillators through, the clock pulses of

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the "θ" (or the "1") output of the fifth stage of the counter I9, where it is assumed that the counter I9 is a binary counter. This eliminates the need for a frequency divider in circuit 5I.

Fig.5 shows another possibility of a circuit for Generation of the clock pulses for the various gate circuits of the system shown in Fig. 4. the Delay elements shown in Fig.4 5 ^ -56 can can be replaced by a counter 64 which has a number of counting positions which is at least equal to that Number of steep command signals that must be generated. If the counter 64 take any of η-states can and the frequency divider included in the circuit 51, an output signal for the respective ni input signals is generated, then the delay element 63> if it is desired to compensate for the average phase shift of the steep command signals generated, have a delay time that is approximately the same in.n / 2 periods of the reference oscillator 18. The output lines 57-61 of the counter 64 carry the control signals for the various gate circuits of the one shown in FIG Systems.

Since the contents of the various phase control registers that are used according to the invention , relatively

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are seldom queried, it is practical to use the invention to generate the control command signals for each axis of the various machine tools. Since the
most complicated and expensive part of the system, the adder, is common to the circuits which are provided for the individual control command signals, the advantages of the invention over the prior art increase with the number of stall command signals that are generated according to the invention. If the invention is used to generate control command signals for the axes of several machine tools, the Ek-Zugssignal is generally used for each machine tool
transmitted together with the steep command signals for this machine tool.

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Claims (2)

PATENT CLAIMS / l. j Digital-to-analog converter for a numerically controlled machine tool system with a device for generating a periodic reference signal and a device for generating a Control command signal that is in phase with respect to the reference signal ■ k is shifted, characterized in that the device for Generating a control command signal from a with a source of Input data connected n-stage phase control register (13, Fig. 2) consists of an n-stage adder (14), the first Inputs are connected to the η stages of a reference counter (11), which is controlled in a manner known per se from a reference oscillator (10) is fed and whose highest stage supplies the reference signal, and its second inputs to the stages of the phase control register ^ are connected, while the highest stage of the adder is connected to the Trigger input (A) of a bistable flip-flop element (15) and via a NOT element (16) is attached to its reset input (R). 2. Digital-to-analog converter according to claim 1, characterized in that that a phase control register (21-25; Fig. 4) and a bistable flip-flop element for each axis of movement of the machine tool system (31-35) are provided, and that the phase control registers one after the other via gate circuits (26-30) with the first inputs the adder and the bistable flip-flops via gate circuits (36, 41, 37, 42, 38, 43, 39, 44, 40, 45) in the same time Docke «YO 968 06 ₂ 009832/1689 Sequence can be connected to the highest output of the adder. 009832/1689