DE2000607B2 - CLOCK STATUS CONTROLLED TOGGLE SHIFT - Google Patents

Description

1 2

A pulse-controlled flip-flop circuit, influenced transient effects, cause undesirable disturbances

differs from a clock edge-controlled tilting of the clock pulses and the respective information

circuit. In the case of the latter, only that during a position signal. Moreover, in such a large

Clock pulse edge of the flip-flop fed internal unit also a certain time until

formation signal influence on the final state 5 the effect at the output of an upstream

the toggle switch. With a clock-controlled toggle switch as information supply at the input

On the other hand, flip-flop has an effect for the duration of a subsequent flip-flop, since

of the clock pulse of the flip-flop circuit, these lines also have transit times - in particular

mationssignal influence the final state special when in such lines additionally

the toggle switch. With a clock state controlled io gates are inserted.

Toggle switching can already occur before the start of the time shifts that occur

Clock pulse an information signal of the toggle switch - the toggle circuits each controlling clock

processing are supplied, the pulses from the flip-flop circuit and because of the additional running time of this

is not taken over. The final information signals on the way between the

Information determining the state of the flip-flop 15 Outputs and inputs of these flip-flops

tion signal is only used during the clock pulse from and because of the associated temporal

taken over by the toggle switch. Postponements from takeover and impact of

The invention is based on a clock state-controlled information signals, so it happens that the internal flip-flop circuit is determined by the supply of an information signal in comparison to the respective setting state of the flip-flop circuit, not only from ao relevant flip-flop circuit , arriving too late or too early. In addition, the presence of a clock pulse can also be pleasantly due to crosstalk in particular. During the duration of the clock pulse of the information signal fed between the different lines of this size flip-flop, the unit receives the information signal because of the interference caused by the final state of the flip-flop, 25 the delay time shifts, but not additionally distorted outside the clock pulse duration, so that the information signal fed to a first flip-flop. In the case of the flip-flop circuit under consideration here, the second and third flip-flops connected downstream, it is essential, because of the crosstalk, whether the successive clock pulses no longer function properly,
30 To avoid such interferences between two successive clocks in larger units, it is per se impulses different, since the invention possible, through careful planning, the length of the measure is independent of the respective transit times of the information signal in the toggle switch position between two clock pulses and between the toggle switches and which can be used. 35 Length of the running times of the flip-flops

In the case of a flip-flop circuit, it is often provided that the controlling clock pulses are carefully coordinated with one another the information taken over by the flip-flop circuit, often through careful selection of the mation signal immediately, d. H. even during the clock flip-flops tight tolerance requirements for the impulses, at the output of the flip-flop circuit as off transit times in the flip-flop circuits and thus past signal affects. Often, however, it is also provided that 40 bound gates must be adhered to. Height that there are requirements taken over by the flip-flop with regard to such tolerances Information signal only after the end of the clock - especially necessary if the clock pulse is high affects the output of the flip-flop. Pulse frequencies, d. H. high computing speed-one so-called master-slave flip-flop is one that should be achieved.

Flip-flop circuit of the latter type, namely in which to 45 The object of the invention is, in particular next the information signal only in the master part due to information signal interference and / or clock and only after the end of the clock pulse from the master pulse interference or due to the delay effects is taken over into the slave part, so that interference in a new way was avoided, so the signal only after the end of the clock pulse at the end of the component tolerances the toggle switch can affect. 50 ren unity and the care in planning the running

When interconnecting several clock-controlled times, lower wiring requirements

ter flip-flops can be used in particular to build stanchions,

larger units in data processing systems The subject of the invention relates to a

does the running time of the clock pulse between clock pulse state-controlled toggle switch

the clock pulse generator and the various 55 devices. The toggle switch is characterized by

clock-controlled flip-flops are often very uncomfortable that the supply of the information signal during a

the end. Because of the running time of the clock pulse, part of the duration of the clock pulse is carried out by a block

probably the takeover of the flip-flops kieinrichtung is blocked.

rend of a clock pulse supplied information due to the blocking according to the invention is

signals in truth in each case at different times, 60 partially achieved that the

as well as the effect of the information transfer ßen flip-flop supplied information signal only

at the outputs of the respective flip-flops during part of the clock pulse duration of the

also at different times. In this case, flip-flop switching can be taken over. Disturbed

Chen larger units often the outputs of such information signals, which during the duration of the

clock-controlled multivibrators with the inputs 65 blocking of the multivibrator are fed,

clock-controlled flip-flops connected, so that despite the simultaneously supplied clock pulse

Acceptance of incorrect information signals may no longer be accepted by the flip-flop

are borrowed. Also especially due to run times. In particular the harmful effects

3 4

of run-time effects, which are taken by the various. This version of the toggle switch is

Runtimes between the clock pulse generator and the in particularly advantageous when the clock pulse T

a larger unit with the clock pulses compared to the supply of the information signal

caused flip-flops to occur and, moreover, this flip-flop arrives relatively late. These

Delays in running time and crosstalk appearances are particularly advantageous when

gen, which are on the connecting lines between when through crosstalk towards the end of the

the outputs of such flip-flops and input clock pulse T of the flip-flop

gen such flip-flops occur or in this mationssignal is disturbed.

Flip-flops occur, can thus occur even in a third embodiment of the invention

very large units very effectively restricted.

will. opposite polarity, so that the auxiliary clock pulse

The invention is based on the implementation of HTl enables the action of the information signal

play or explained in more detail by drawings. and one between the beginning of the clock pulse T.

Fig. La and Ib show the course of a clock pulse and the beginning of the auxiliary clock pulse HT 1 take place

impulse and takeover; 15 change of one input of the toggle switch

Fig. 2 shows a larger unit; The information signal supplied has no influence

3a, 3b, 4a, 4b, 5a and 5b show differently the final state of the flip-flop.

dene exemplary embodiments. This design is particularly advantageous when

In a preferred solution, according to FIG. 1 a, the clock pulse T is provided in comparison to this one, so that an information signal supplied after the beginning of the clock pulse T, which is unpleasant, but before the end of the clock pulse T, arrives too early. This execution is beginning, blocked in an auxiliary clock pulse generator according to the invention for the duration il and generated auxiliary clock pulse HTl on an input which only during the duration? 2 enabled, so that the flip-flop circuit takes effect. This auxiliary clock pulse does not necessarily have to have the same duration as the clock pulse or the clock pulse T during the duration il no pulse. Advantageously, one can have detrimental effects on the final aid of the auxiliary clock pulse HT1 blocking the status of this embodiment. This embodiment of the flip-flop circuit according to the invention can be achieved or controlled in different ways, in particular in the case of master-slave flip-flop circuits, with flip-flop circuits designed in particular being advantageous, since such three cases can be distinguished; of which 3 ° flip-flops have similar properties as counters, each of which has other special advantages: and have a certain number of faults, e.g. B.

The flip-flop can firstly be carried out so the supplied clock pulse during the period that it would count by a clock pulse within the duration of il, which is controlled without the use of erfindungsil + ti lying auxiliary clock pulse edge. Corresponding measure leads to false effects on In this embodiment, the output according to the invention can lead to these flip-flops.
Flip-flop with regard to the clock pulse T takt- In particular, the last version can be controlled according to the invention, but with regard to the auxiliary clock can be developed according to the fact that the pulse HT1 is edge-controlled. The control flip-flop on after the beginning of the in Fig. La through the edge of the auxiliary clock pulse HTl has the auxiliary clock pulse HTl shown, but before the advantage that the information transfer in the flip-flop 40 end of the clock pulse T beginning blocking clock circuit according to FIG. 1b only during a short pulse HT2 is supplied, which blocks the effect of the time segment after the duration il within that of the information signal, so that a duration of the clock pulse T takes place. When planning the input of the flip-flop for the duration t 4, therefore, with regard to the information signal that is supplied to an input of the flip-flop during the duration t 4 in this embodiment 45 no longer has to be applied to all of the information signal during the time shown in FIG. 1 a shown influence on the final state of the toggle switch for the entire duration rl - ¹ - ti of the clock pulse T may. In this refinement, the intrinsic delay time shifts or disturbances in the information signal are only taken over into the information signal or disturbances in the clock flip-flop circuit during the duration i3. Advantageously, the pulse can be taken into account, but with this development similar advantages as are with regard to the relevant flip-flop circuit in the above-mentioned first, with regard to the aid of planning at most the edge-controlled execution during the comparison clock pulse, the duration of the relevant auxiliary clock is sufficient . Since with this development possible shifts or disturbances of the duration of the clock pulse state ti + ti must be taken into account. 55 relatively long takeover times / 3 can be achieved

In a second embodiment of the invention, this further development can, in many cases, be flip-flop, the auxiliary clock pulse advantageously also has a relatively slow polarity such that it can be equipped with the effect of the information-working transistor type,
The flip-flop circuit according to the invention can advantageous auxiliary clock pulse HTl change in the auxiliary clock pulse generators which are also fed to the information signal, which is also not supplied to the auxiliary clock pulse flip-flop circuit, in various ways:
circuit has. In this embodiment, therefore, in one embodiment, according to FIG. 2 provided, rend the duration ti of the clock pulse T the information that the auxiliary clock pulse generator transferred the auxiliary clock pulse tion signal in the flip-flop. Since the 65 HTl respectively generated from the clock pulse T, by the auxiliary clock pulse HTl blocks the flip-flop, each of the clock pulse generator TG the clock during the duration ti of the clock pulse T no pulse T a the auxiliary clock pulse generator form information signal more in the multivibrator exceeds the delay element V the running time ti .

5 6

The output of the delay element V is then sometimes not very expensive and requires the auxiliary clock pulse in each case. The clock pulse generator only conventional means, all of the above in the TG supplies the clock pulse sequence here in each case via a connection with the blocking clock pulse specified clock amplifier TV and clock gate Tg with blocking pure advantages. Advantageously, output Sp via line 1 to the series-connected 5 can also this further delay element or the th trigger circuits FF1, FFn. Blocking clock pulse generator is connected to line 1 together with the Kippdas delay element V , which has a running time ti combined to form a module unit, so that the in be on line 2, whereby in particular the series production of FIG. 1 a shown auxiliary clock pulse HTL occurs. This flip-flop circuit and the planning of the auxiliary clock pulse with this flip-flop is simplified in the larger units constructed in the circuit shown in FIG. This module unit / UC inputs can be fed to the multivibrator circuits, including in the form of a monolithic block, whereby the auxiliary clock blocks the information signal transfer through advantageously the external dimensions in the multivibrator circuits, depending on the polarity of the auxiliary and thus also the delay effects within the clock pulse HTl or releases, as long as 15 building block units are kept particularly low, via line 1, the toggle switch connected in series. The monolithic building block unit is suitable for circuits FFl, FFn supplied with the clock pulse T, therefore, in particular for the construction of a very large input. As long as these flip-flops do not have cycles with a high clock frequency,
Pulse T is supplied, can also be made from this toggle The fact that the delay of the further interconnections no information signal is taken over ao delay element according to the need can advantageously be adjusted later of run-time effects and pulse generator V containing component unit of crosstalk phenomena and similar interference, which advantageously eliminates series production, even if the interference units that occur can be facilitated when planning the flip-flop circuit and planning larger units. If, in addition, or runtime effects, the building block unit was not considered to be a monolithic one. The adjustability of the delay block forms, so the delay time of the blocking clock pulse generator can advantageously also allow outer dimensions of the flip-flop circuit to be very small, i.e. in particular lower demands on the and thus the running times to be taken into account, in some cases particularly low The effect of the auxiliary clock pulse or block that this embodiment according to the invention also kiertaktimpulses on the rocker switch according to the invention for the construction of very large units with high device can advantageously be suitable in different clock pulse frequencies. Way to be trained. Thus, the auxiliary clock pulse can When the delay of the delay element 35 V often directly a signal input of flip-flop zunach basis of the needs is adjustable, it can be performed such. B. in Fig. 2 with JK-Kipp is shown advantageously especially after the interconnection. The blocking device build on larger units, the delay is here so only from the connection of the auxiliary clock can be adjusted so that a proper signal pulse generator is connected to a signal input.
Transfer to the flip-flop circuit in each case particularly 40 The auxiliary clock pulse or the blocking clock pulse is secured. The adjustability of the delay can, however, also be applied to a runway of the toggle switch attached to the information signal input time to correct these one-time shifts as required . This switch disturbances and clock pulse disturbances retrospectively 45 thus acts as at least largely suppressing the above-mentioned blocking device. In addition, the device which selects the supply of the information signal allows the adjustability of the delay term of a part of the duration of the clock pulse block V, so that the planning of the larger unit is often detected, so that at least during a large part it is considerably simplified because the selectable On the clock pulse duration the effect of the information position of the delay ti of the delay element 50 tion signal or the flip-flop is blocked. The running time differences and side-effects that occur are advantageously associated with this design of the blocking speech effects without a great deal of effort in advance equipment as a special switch with little effort, calculation or planning in general, without a signal input which can be rendered harmless. circuit with the auxiliary clock pulse or blocking clock if the delay element has to occupy an amplifier pulse. This even only needs to hold, so on the one hand the one single switch provided for both pulses can advantageously be changed and / or changed to the polarity of the auxiliary clock pulse HT1 by also transferring the auxiliary clock pulse HT1 together or on the other hand to the energy of the auxiliary clock pulse with the blocking clock pulse HT 2 on this single or whose voltage or current values act according to the switch.

can be chosen according to the needs. 60 The switch can be operated by a trans-

In a further embodiment, the inventive transistor can be formed, via its emitter-collector-

moderate toggle switch is the one shown in FIG. 1 block route shown the information signal of the flip-flop to-

kiertaktimpuls HT2 is performed from the clock pulse T, the auxiliary clock pulse or the

testifies by the clock pulse T or from the blocking clock pulse in each case of the control electrode of this

Clock pulse generated auxiliary clock pulse HTl is fed to a white transistor. Advantageously is a

direct delay element is supplied, the form of which is formed in such a way switch or in

output supplies the blocking clock pulse HTl. Such a blocking device designed in such a way with

The construction of the blocking clock pulse generator is particularly easy to manufacture. The tran-

Sistor can be a multi-emitter transistor in which at least one of the emitters is used as a control electrode.

Such an embodiment is shown in FIG. 3b shown. There the clock pulse T is simultaneously fed to a control electrode or emitter which enables the feed of the information signal /, Q and also to a Miller integrator V corresponding to a delay element. The Miller integrator V generates, because of the temporal stretching of the rising edge of the clock pulse it causes, an auxiliary clock pulse which has edges which take up much longer than the clock pulse edges. This auxiliary clock pulse, which is, as it were, delayed with respect to the clock pulse, is fed to another emitter of the aforementioned multi-emitter transistor, which in turn blocks the feed of information signals J, <2. The in F i g. The embodiment shown in FIG. 3b has been designed in particular for production using monolithic technology and represents the left half of the embodiment shown in FIG. 3 a shown J-, (2-flip-flop circuit with the inputs /, ~ Q and Q, K.

In Fig. 4 a and 4 b is another embodiment of the one shown in FIG. 3 b indicated Miller integrator, namely by instead of the according to FIG. 3 a a total of two different Miller integrators provided, the only one in FIG. 4b shown Miller integrator is provided, which acts on the inputs /, 3 'K-> Q assigned multiemitter transistors. The in F i g. 4b shown Miller integrator has the in F i g. 4 a function shown.

The superposition of the clock pulse with the auxiliary clock pulse for generating the blocking provided according to the invention can also be carried out according to the method shown in FIG. 5 a specified embodiment be formed. The clock pulse on the one hand directly and on the other hand, an AND gate in each case fed via an auxiliary clock pulse generating HTL V delay element with appropriate polarity so that g at the output of the AND gate only during the in F i. 1 a shown duration 1 1 or 1 2, a pulse controlling the tilting device K is supplied via the control pulse input Te. Via the inputs E of the tilting device K , an information signal is only accepted into the tilting device K when the supply is enabled by the gate pulse supplied to the input Te.

The tilting device K can for its part also be controlled by the cycle state, so that the in FIG. 5 a shown, the delay element V also containing flip-flop is also clock state-controlled. This flip-flop can, however, also be state-controlled with regard to the clock pulse T , but be edge-controlled with regard to the auxiliary clock pulse HT1 , if the flip-flop K is clock edge-controlled here and the one in FIG. 5 shown clock pulse T and auxiliary clock pulse HTl is superimposed in the AND gate with such polarity that at the output of the AND gate only during the in F i g. 5 b and F i g. 1 a shown duration ti a gate pulse is fed to the input Te . The exemplary embodiment shown in FIG. 5a thus represents a flip-flop which can be produced in an advantageous manner with little effort and which is clock edge-controlled with regard to the auxiliary clock pulse and clock state-controlled with regard to the clock pulse.

If the in F i g. 5 a tilting device shown K a master-slave-tilting mechanism, the acquired information signal at the output A may affect advantageously only after the end of the clock pulse T, or after the end of the Dauert2. It can thus be achieved in particular that one of the tilting device K of the in FIG. 5 a flip-flop shown during a first clock pulse received information signal from a downstream further, z. B. according to Fig. 2 nachgischaltcten flip-flop FFn is only taken over during the next clock pulse.

There are also advantageously various configurations for the delay element. Above the design as a Miller integrator has already been specified. However, the delay element can also be designed as an ÄC member, which is advantageous is very easy to manufacture, especially in integrated technology. The delay element can, however also in other ways, e.g. B. designed as an LC element be, whereby the delay element according to in particular with regard to transit times and edge steepnesses can be adapted to the known rules of filter technology as required. The delay element can advantageously also itself be formed by a further monostable tilting device, which in often advantageously very steep flanks and possibly also very high output energies may have.

For larger units, z. B. corresponding to the in F i g. 2 advantageously also be provided that the auxiliary clock pulse generator not only a flip-flop, but at least another flip-flop is supplied with auxiliary clock pulses. Advantageously, this measure when building larger units, the cost of auxiliary clock pulse generators is significantly reduced without losing the advantages of the invention.

All measures according to the invention are in principle suitable for all types of trigger circuits, not just for master-slave trigger circuits. Advantageously, the measure according to the invention is also not limited only to trigger circuits with specific input signals. The measures according to the invention can namely be applied to / iC flip-flops as well as D flip-flops or, for example, R, S, RS or DF flip-flops, the advantages according to the invention also being achievable in each case.

Claims (30)

Patent claims: 1. A flip-flop circuit controlled by clock pulses, characterized in that the supply of the information signal (Q, K) is blocked during part of the duration (ti + ti) of the clock pulse (T) by a blocking device (3 in FIG. 4 b). 2. flip-flop circuit according to claim 1, characterized in that after the beginning of the clock pulse (T), but before the end of this clock pulse beginning, in an auxiliary clock pulse generator (V) generated auxiliary clock pulse (HTl) acts on an input (3) of the flip-flop circuit . 3. Toggle circuit according to claim 2, characterized in that it is provided by a within the 109 514/346 Clock pulse duration (rl-hi 2) lying auxiliary clock pulse edge is controlled. 4. flip-flop circuit according to claim 2, characterized in that the auxiliary clock pulse (HTl) blocks the action of the information signal, so that a change in the information signal supplied to an input of the flip-flop circuit during the auxiliary clock pulse (HTl) has no effect on the final state of the flip-flop circuit. ίο 5. flip-flop circuit according to claim 2, characterized in that the auxiliary clock pulse (HTl) enables the action of the information signal, so that between the beginning of the clock pulse (T) and the beginning of the auxiliary clock pulse (HTV) occurring change of the information signal supplied to an input of the flip-flop has no influence on the final state of the trigger circuit. 6. flip-flop circuit according to one of claims 2 ao to 5, characterized in that the flip-flop circuit is supplied to a blocking clock pulse (HT 2) beginning after the beginning of the auxiliary clock pulse (HTl) but before the end of the clock pulse (T), which the action of the information signal blocked, so that an input of the flip-flop between the beginning of the clock pulse (T) and the beginning of the auxiliary clock pulse (HTl) and an input of the flip-flop between the beginning of the blocking clock pulse (HT 2) and the end of the clock pulse (T) supplied information signal has no influence on the final state of the flip-flop. 7. flip-flop circuit according to one of the preceding claims, characterized in that the auxiliary clock pulse generator (V) generates the auxiliary clock pulse (HTl) from the clock pulse (T) in that the clock pulse generator supplies the clock pulse to a delay element (V) forming the auxiliary clock generator, the output of which feeds the Auxiliary clock pulse supplies. 8. flip-flop circuit according to claim ?, characterized in that it has the auxiliary clock pulse generator also forms the building block unit. 9. flip-flop circuit according to claim 8, characterized in that the building block unit has a forms monolithic block. 10. Toggle circuit according to one of claims 7 to 9, characterized in that the delay of the delay element is adjustable as required. 11. Toggle switch according to one of the claims? to 10, characterized in that the delay element contains an amplifier. 12. Trigger circuit according to one of claims 6 to 11, characterized in that the blocking clock pulse (HT 2) is generated from the clock pulse (T) in that the clock pulse or the auxiliary clock pulse (HTT) generated from the clock pulse is fed to a further delay element whose output supplies the blocking clock pulse. 13. flip-flop circuit according to claim 12, characterized in that it has the further delay element also forms the building block unit. 14. flip-flop circuit according to claim 13, characterized in that the further delay element containing building block unit forms a monolithic block. 15. Toggle circuit according to one of claims 12 to 14, characterized in that the delay of the further delay element can be adjusted as required. 16. Toggle circuit according to one of claims 11 to 15, characterized in that the further delay element contains an amplifier. 17. Toggle circuit according to claim 6 or one of claims 12 to 16, characterized in that that the blocking clock pulse from a first applied to the information signal input, this one The input blocking or releasing switch is effective. 18. Toggle circuit according to one of the preceding claims, characterized in that that the auxiliary clock pulse on a second attached to the information signal input, this one Input blocking or releasing, the blocking device forming switch acts. 19. Toggle circuit according to claims 17 and 18, characterized in that the first switch also takes over the function of the second switch, in that the auxiliary clock pulse (HTL) also acts on this first switch. 20. Toggle switch according to claim 18 or 19, characterized in that the switch in each case is formed by a transistor, via the emitter-collector path of which the information signal the flip-flop is supplied, and that the auxiliary clock pulse and the blocking clock pulse, respectively the control electrode of this transistor is supplied. 21. Trigger circuit according to claims 19 and 20, characterized in that the transistor is a multi-emitter transistor (3) and that at least one of the emitters of this multi-emitter transistor is used as the control electrode of this multi-emitter transistor (Fig. 3b and 4b). 22. Trigger circuit according to one of the preceding claims, characterized in that the delay element (V) contains an ÄC element. 23. Trigger circuit according to one of claims 4 to 21, characterized in that the delay element (F) contains an LC element. 24. Toggle circuit according to claim 22 or 23, characterized in that the delay element (F) contains a monostable further tilting device. 25. Toggle circuit according to claim 22 and at least one of claims 11 and 16, characterized characterized in that the amplifier together with the delay element as a Miller integrator is trained. 26. Toggle circuit according to one of the preceding claims, characterized in that that the auxiliary clock pulse generator supplies at least one further flip-flop with auxiliary clock pulses. 27. Toggle circuit according to one of the preceding claims, characterized in that that it is a master-slave flip-flop. 28. Toggle circuit according to one of the preceding claims, characterized in that that it is a /.^ toggle switch. 29. Toggle circuit according to one of claims 1 to 27, characterized in that it has a D toggle switch is. 30. Toggle circuit according to one of the preceding claims, characterized in that that the clock input (Te) of its flip-flop device (K) is connected to the output of a gate and that the clock pulse (T) and the auxiliary clock pulse (HTl) or the blocking clock pulse is fed to the gate inputs (Fig. 5 a). 1 sheet of drawings