DE20002608U1 - DC converter - Google Patents

DC converter

Info

Publication number
DE20002608U1
DE20002608U1 DE20002608U DE20002608U DE20002608U1 DE 20002608 U1 DE20002608 U1 DE 20002608U1 DE 20002608 U DE20002608 U DE 20002608U DE 20002608 U DE20002608 U DE 20002608U DE 20002608 U1 DE20002608 U1 DE 20002608U1
Authority
DE
Germany
Prior art keywords
transistor
arrangement according
circuit arrangement
circuit
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE20002608U
Other languages
German (de)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to DE20002608U priority Critical patent/DE20002608U1/en
Publication of DE20002608U1 publication Critical patent/DE20002608U1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Description

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßt The description text was not recorded electronically  

Der Beschreibungstext wurde nicht elektronisch erfaßtThe description text was not recorded electronically

Claims (15)

1. Schaltungsanordnung für einen Gleichspannungsumsetzer mit einem Übertrager und einem im Umsetzerausgangskreis angeordneten Synchrongleichrichter in Form eines MOSFET- Transistors, dessen Schaltstrecke mit einer Ausgangs­ wicklung des Übertragers und einem Ladekondensator in Reihe liegt, dadurch gekennzeichnet, dass der Gleich­ spannungsumsetzer als selbstschwingender Sperrwandler in der Weise ausgebildet ist, dass im Steuerkreis des MOS- FET-Transistors (T1) eine diesen sperrende Transistor­ sperrstufe (R1, T2) angeordnet ist, die durch eine Steu­ erwicklung (W3) des Übertragers (T) über ein Verzöge­ rungs-RC-Glied (R3, C3) derartiger Bemessung gesteuert wird, dass der MOSFET-Transistor (T1) unmittelbar vor dem Ende des Abbaus der im Übertrager (T) gespeicherten Energie gesperrt wird.1. Circuit arrangement for a DC converter with a transformer and a synchronous rectifier arranged in the converter output circuit in the form of a MOSFET transistor, the switching path with an output winding of the transformer and a charging capacitor, characterized in that the DC voltage converter as a self-oscillating flyback converter in the manner is formed that in the control circuit of the MOS-FET transistor (T1) this blocking transistor blocking stage (R1, T2) is arranged, which by a control development (W3) of the transformer (T) via a delay RC element ( R3, C3) is controlled in such a way that the MOSFET transistor (T1) is blocked immediately before the end of the degradation of the energy stored in the transformer (T). 2. Schaltungsanordnung nach Anspruch 1, dadurch gekenn­ zeichnet, dass die Steuerwickung (W3) über einen Begren­ zungswiderstand (E1) mit der Steuerstrecke des MOSFET- Transistors (1) in Verbindung steht und an die Verbin­ dung zwischen diesem Begrenzungswiderstand (R1) und der Gate-Elektrode dieser Steuerstrecke der Kollektor eines Sperrtransistors (T2) angeschlossen ist, dessen Emitter mit dem gemeinsamen Verbindungspunkt der Steuerwicklung (W3) mit der Source-Elektrode des MOSFET-Transistors (T1) verbunden ist und dessen Basis an das Verzögerungs- RC-Glied (R3, C3) angeschlossen ist.2. Circuit arrangement according to claim 1, characterized in that the control winding (W3) via a limita tion resistor (E1) with the control path of the MOSFET transistor ( 1 ) is connected and to the connec tion between this limiting resistor (R1) and The gate electrode of this control path is connected to the collector of a blocking transistor (T2), the emitter of which is connected to the common connection point of the control winding (W3) to the source electrode of the MOSFET transistor (T1) and the base of which is connected to the delay RC element (R3, C3) is connected. 3. Schaltungsanordnung nach Anspruch 2, dadurch gekenn­ zeichnet, dass dem Begrenzungswiderstand (R1) ein Rei­ hen-RC-Glied (R2, C2) parallel liegt. 3. Circuit arrangement according to claim 2, characterized shows that the limiting resistor (R1) has a row hen RC element (R2, C2) is parallel.   4. Schaltungsanordnung nach Anspruch 2 oder 3, dadurch ge­ kennzeichnet, dass mit dem Widerstand (R3) des Verzöge­ rungs-RC-Glieds (R3, C3) ein Parallel-RC-Glied (R4, C4) in Reihe liegt.4. Circuit arrangement according to claim 2 or 3, characterized ge indicates that with the resistance (R3) of the delay RC-links (R3, C3) a parallel RC-link (R4, C4) in line. 5. Schaltungsanordnung nach einem der Ansprüche 2 bis 4, dadurch gekennzeichnet, dass der Kollektor-Basis-Strecke des Sperrtransistors (T2) eine Diode (D2) antiparal­ lel geschaltet ist.5. Circuit arrangement according to one of claims 2 to 4, characterized in that the collector-base route the blocking transistor (T2) has a diode (D2) antiparal lel is switched. 6. Schaltungsanordnung nach einem der Ansprüche 2 bis 5, dadurch gekennzeichnet, dass im Emitterkreis des Sperr­ transistors (T2) eine Bezugsspannungsquelle (D4) zur Kompensation des Spannungsabfalls an der Steuerstrecke des Sperrtransistors (T2) angeordnet ist.6. Circuit arrangement according to one of claims 2 to 5, characterized in that in the emitter circuit of the barrier transistor (T2) a reference voltage source (D4) for Compensation of the voltage drop on the control path of the blocking transistor (T2) is arranged. 7. Schaltungsanordnung nach Anspruch 6, dadurch gekenn­ zeichnet, dass die Bezugsspannungsquelle eine vorge­ spannte Diode (D4) ist.7. Circuit arrangement according to claim 6, characterized records that the reference voltage source a pre tensioned diode (D4). 8. Schaltungsanordnung nach Anspruch 7, dadurch gekenn­ zeichnet, dass die Vorspannung für die Diode mittels ei­ ner an die Steuerwicklung (W3) des Übertragers (T) ange­ schlossenen Gleichrichter- und Glättungsschaltung (R9, D5, C7, R8, C6) gewonnen ist.8. Circuit arrangement according to claim 7, characterized records that the bias for the diode using ei ner to the control winding (W3) of the transformer (T) closed rectifier and smoothing circuit (R9, D5, C7, R8, C6) is won. 9. Schaltungsanordnung nach einem der Ansprüche 2 bis 8, dadurch gekennzeichnet, dass mit dem Sperrtransistor (T2) ein weiterer Transistor (T3) in Kaskade geschaltet ist. 9. Circuit arrangement according to one of claims 2 to 8, characterized in that with the blocking transistor (T2) another transistor (T3) connected in cascade is.   11. Schaltungsanordnung nach einem der Ansprüche 2 bis 10, dadurch gekennzeichnet, dass der Steuerstrecke des MOS- FET-Transistors (T1) eine Diode (D1) antiparallel ge­ schaltet ist.11. Circuit arrangement according to one of claims 2 to 10, characterized in that the control path of the MOS FET transistor (T1) a diode (D1) antiparallel ge is switched. 12. Schaltungsanordnung nach einem der Ansprüche 2 bis 10, dadurch gekennzeichnet, dass für den MOSFET-Transistor (T1) eine Treiberstufe mit einem Transistor (T4) vorge­ sehen ist, der eingangsseitig an den Begrenzungswider­ stand (R1) angeschlossen ist.12. Circuit arrangement according to one of claims 2 to 10, characterized in that for the MOSFET transistor (T1) a driver stage with a transistor (T4) is seen, the input on the limit resistor stand (R1) is connected. 13. Schaltungsanordnung nach Anspruch 12, dadurch gekenn­ zeichnet, dass die Betriebsspannung für den Treibertran­ sistor (14) mittels einer an die Steuerwicklung (W3) des Übertragers (T) angeschlossenen Gleichrichter- und Glät­ tungsschaltung (R9, D3, C5) gewonnen ist.13. Circuit arrangement according to claim 12, characterized in that the operating voltage for the driver transistor ( 14 ) is obtained by means of a rectifier and smoothing circuit (R9, D3, C5) connected to the control winding (W3) of the transformer (T). 14. Schaltungsanordnung nach Anspruch 12, dadurch gekenn­ zeichnet, dass im Steuerkreis des Treibertransistors (T4) eine Zenerdiode (Z) zur Begrenzung der Steuerspan­ nung angeordnet ist.14. Circuit arrangement according to claim 12, characterized records that in the control circuit of the driver transistor (T4) a Zener diode (Z) for limiting the control chip is arranged. 15. Schaltungsanordnung nach einem der Ansprüche 12 bis 14, dadurch gekennzeichnet, dass der Treibertransistor (T4) mit einem als Impedanzwandler arbeitenden Transistor (T5) in Kaskade geschaltet ist.15. Circuit arrangement according to one of claims 12 to 14, characterized in that the driver transistor (T4) with a transistor working as an impedance converter (T5) is cascaded. 16. Schaltungsanordnung nach einem der Ansprüche 12 bis 15, dadurch gekennzeichnet, dass zwischen dem Kollektor des Treibertransistors (T4) und der Basis des Sperrtransi­ stors (T2) ein Abgleichwiderstand (R6) vorgesehen ist.16. Circuit arrangement according to one of claims 12 to 15, characterized in that between the collector of the Driver transistor (T4) and the base of the blocking transistor stors (T2) a trimming resistor (R6) is provided.
DE20002608U 2000-02-15 2000-02-15 DC converter Expired - Lifetime DE20002608U1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE20002608U DE20002608U1 (en) 2000-02-15 2000-02-15 DC converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE20002608U DE20002608U1 (en) 2000-02-15 2000-02-15 DC converter

Publications (1)

Publication Number Publication Date
DE20002608U1 true DE20002608U1 (en) 2000-08-03

Family

ID=7937286

Family Applications (1)

Application Number Title Priority Date Filing Date
DE20002608U Expired - Lifetime DE20002608U1 (en) 2000-02-15 2000-02-15 DC converter

Country Status (1)

Country Link
DE (1) DE20002608U1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2826523A1 (en) * 2001-06-25 2002-12-27 Cit Alcatel SELF-CONTROLLED SYNCHRONOUS RECTIFIER

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2826523A1 (en) * 2001-06-25 2002-12-27 Cit Alcatel SELF-CONTROLLED SYNCHRONOUS RECTIFIER
US6707650B2 (en) 2001-06-25 2004-03-16 Alcatel Self-synchronized synchronous rectifier

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Legal Events

Date Code Title Description
R207 Utility model specification

Effective date: 20000907

R156 Lapse of ip right after 3 years

Effective date: 20030829