DE19926580A1 - A predictive process for jump instructions is used in a computer system to improve the speed of access to main memory data and uses historical data in a cache memory - Google Patents

Abstract

The computer system has a cache memory (10) in which there is stored a second tag field (13) together with additional history data. Multiple jump addresses for each branch address are stored. This data is used in a forecast process to improve the speed of access to data within the main memory of the system. A first tag field (12) having address information of branch command is compared with content of second tag field to forecast jump target address.

Description

The invention relates to methods and apparatus for Predicting jump destination addresses when processing Branch instructions.

In modern computer systems, measures have to be taken to the relatively slow main memory accesses to the in Relative to this, fast processing of these accesses adapt available data in the processor (s).

In computer systems with superscalar processor architecture and Pipeline techniques are several instructions from the Program for processing by the processor or processors kept and processed. Follow the instructions sequentially and independently of each other in the program one another, there are no problems. More complicated is the situation when branch instructions (for, if, switch, Etc. . .) to be processed in a pipeline. Here in addition to the result of a branch, its Jump destination address to be known. Branches are for this usefully distinguishable between conditional and unconditional, as well as after direct and indirect branches.

The destination addresses are always for direct branches the same, mostly by an offset of the address of the Branch instruction given itself. For this is the Branch target buffer (BTB) Memory for each branch instruction of that Jump destination address has been an effective way to to predict this at the time of retrieval.  

The existence of indirect branch instructions that are dependent from the current parameters of the program, i.e. dynamically to Program runtime to different jump destination addresses branching, increases the effort for the right one Predict jump destination address since the current one Parameter assignment at the time of loading the pipeline with the instructions are not yet clear. During the term create branch history tables a possible means of doing this.

This means that the jump destination address is an indirect one Branching can be different every time it is performed. Therefore, it is difficult to find the right one Predict jump destination address even if the direction of the Branching, d. that is, whether it occurs, i.e. H. jumps or not is known. A branch destination memory (BTB) would be for this not the appropriate remedy, since this is usually only the last jumped jump destination address keeps stored.

So far, for better prediction of jump destination addresses, for example in Chang, PY, Hao, E., Patt, YN in "Predicting Indirect Jumps Using a Target Cache", Proc. 24 ^th ann. International Symposium On Computer Architecture, 1997, pp. 274-283 proposed to use a cache memory for the jump destination address, in which several addresses can be stored for one and the same branch instruction, arrangements with or without a tag field being presented. The tag field contains information that is intended to make access to the correct jump destination address more secure by means of a suitable index formation from address and history information.

This is the address for accessing the cache memory using the address of the branch instruction as it is known from BTB technology, as well as using generated from history information, the information as for the current branch instruction characteristic, previously executed command addresses  save and be used to switch between each To be able to select jump destination addresses.

Here either so-called global pattern history or alternatively, path history information is processed.

The first embody information in bit sequences about which of the last m branches jumped and which not, only the sequence jumped / not jumped is saved, but not the associated command addresses. Only 1 bit per branch instruction is required for this.

The latter (path history) embody in bit sequences Information about the last n branch instruction addresses itself. This does not include full addresses, but usually only the significant, least significant bits, for example, two bits are stored.

Both types of history information are on the current branch instruction related to one Jump destination prediction should be made. However, you are different densities - one or two bits per Branch instruction.

In the procedure mentioned above, however, must be avoided a disproportionately large cache memory at the Arrangement without a tag field the addresses with the history Information is subjected to a hash function. This has the disadvantage that for different Branch instruction addresses and different history Information on the same jump destination entry could be accessed. That means that for different branches the same jump destination address would be predicted.

When arranged with a tag field in the cache memory, the above publication three different methods  introduced how the tag field is formed and on the cache Memory can be accessed. It does not succeed exclude that at different Branch instruction addresses and different history Information on the same jump destination entry can be accessed. In addition, there is Possibility that for a known branch none at all Jump destination address can be predicted if the Branch not yet together with the current history Information was encountered.

The object of the present invention is therefore a method and to create a device that uses the selection mechanisms while avoiding the latter disadvantages of missing Improve and uniqueness of the jump destination address generalize.

The object is achieved by the method specified in claim 1 and the device specified in claim 8 solved.

The idea on which the present invention is based exists in that a branch target address of a branch instruction by predicting that on those Jump destination address entry is accessed in the cache memory, which results from an upstream comparison of high order bits of the branch instruction address, one further comparison of low-order remaining bits of the Branch instruction address in a first tag field of the cache Memory, which initially creates the identity of the stored Branch instruction with the current branch instruction is ensured, and a subsequent comparison the greatest possible agreement between those in the second tag field saved history information with those the current history.

The inventive method with the features of the claim 1 and the device according to the invention with the features of  Claim 8 point over those outlined above Approaches the advantage of having a cache for Jump destination addresses (target cache) into a conventional one Branch destination memory (BTB) can be integrated, whereby only slightly more mispredictions are accepted have to. Furthermore, a jump destination address can also be used be predicted if for an already known one Branch instruction has an as yet unknown history.

There are advantageous ones in the subclaims Developments of the method specified in claim 1 and the device specified in claim 8.

According to a particularly preferred development, the second tag field bit history determined as history information Episodes saved from an XOR of global history and path history are obtained, whereby in the in most cases the forecast quality is further increased can be.

The following exemplary embodiments of the invention serve the explanation of the inventive principle. You are in the Drawings shown and in the description below explained in more detail.

Show it:

FIG. 1 shows the schematic structure of an entry of an integrated embodiment of the cache memory according to the invention;

Fig. 2 shows an embodiment of the procedure of the method of the cache memory according to the invention in cooperation disposed in a schematic overall view in a further embodiment with a separate, conventional branch target storage (BTB);

Fig. 3 shows a schematic representation of a detail of the embodiment of FIG. 2.

With reference to FIG. 1, an expedient embodiment of an entry of the cache memory 10 according to the invention is first explained, as it also includes the data structure of a conventional BTB in an integrated form.

The entry in the cache memory 10 contains a first tag field 12 , which contains a certain number of low-order address bits of branch instruction addresses. In the present exemplary embodiment, which is aligned to an address width of 32 bits, it contains, for example, the low-order 24 bits of the branch instruction address 30 for which the branch target is to be predicted. Furthermore, according to the invention there is a second tag field 13 which serves for additional differentiation in the selection of the jump destination address, with exactly one jump destination address in a field 14 being assigned to every second tag field in an n-fold set-associative data structure. In the present case, n = 4 should apply.

Another field 16 , which comprises several bits, is provided for several flags. Various information regarding the branches can be encrypted here, the flags, for example, to allow statements, such as:
whether there is a conditional or unconditional branch,
whether there is an identified return address or not,
whether there is an identified call address or not,
whether or not there is a branch instruction with several, ie varying, jump destination addresses, etc.

By adding the second tag field 13 , according to the invention, a plurality of jump destination addresses for one and the same branch instruction address 30 can be stored in the cache memory 10 , since their unique assignment is given via the second tag field.

With reference to FIG. 2, the method according to the invention in connection with the cache memory 10 according to the invention will now be explained in a modified form, this interacting in a spatially separated form with a conventional branch instruction memory 20 according to the method according to the invention.

The branch instruction memory 20 , which is designed here for example as a 4-fold set-associative memory, is the cache memory 10 as a separate, small and fast memory module for storing the different branch target addresses for the purpose of processing a branch instruction with varying branch target addresses assigned. Such a structure can be recommended in particular if a slightly reduced frequency of hits must not be tolerated, or if the addition of the second tag field for each entry would cause an unacceptable increase in the area of the branch instruction memory 20 . In such a case, the associativity of the cache memory 10 should preferably be between 8 and 16, so that most of the possible branch target addresses of the branches with multiple branch target addresses fit into one set.

If a jump target address is now to be predicted for a current branch instruction to be loaded into the pipeline, in a first step the comparator 32 compares the higher order address bits of the branch instruction address 30 by branch 34 and the lower order in the first tag field 22 of the memory 20 stored address bits by branch 36 each with the corresponding address bit sequences of the current branch instruction address 30 for which the branch destination address is to be predicted. The result identical / not identical is forwarded to a decision logic 39 .

If there is an identity, it is determined by querying the flag 26 in the field 16 of the branch instruction memory 20 via branch 40 and a decision logic 41 whether or not it is a branch with a varying jump destination address. If not, it is in most cases the simple case of a direct branch, which does not require the cache memory 10 according to the invention for prediction. Then the branch destination address stored in field 24 of branch destination memory 20 after initialization is provided by branch 38 and decision logic 39 for prediction.

If there is a varying jump destination address, the cache memory 10 is accessed to determine the suitable jump destination address. The flag 26 can be written after the branch instruction has been encountered twice during the initialization phase, since it is then certain whether the associated jump destination addresses have differed or not. If they differ, the flag 26 is set so that the cache memory 10 is to be accessed. The access can then take place the next time the branch instruction occurs via the written flag 26 and the branch 40 . The other flags mentioned above can also be processed via decision logic 41 .

When accessing the cache memory 10 , it is ensured analogously to the above-described comparison of the higher or lower-order address parts of the branch instruction that the bit sequence stored in the first tag field 12 corresponds to the low-order bits of the current branch instruction address 30 .

This address comparison takes place in the right part of FIG. 2 in branches 42 , 44 and in comparator 46 , with the proviso that the low-order bits come from the first tag field 12 of the cache 10 . Next place through branch 48 of the above-described access to the second tag fields 13 of the cache 10 and in node 52 an XOR comparison of history information stored in accordance with the current history information 53 of branch 54 instead. This comparison is described in more detail below. In a decision logic 56 , the second tag field 13 is determined with the best possible match with the current history patterns. The associated jump destination address from field 14 is selected via the multiplex control of the decision logic 60 as a selection from the 4-fold set-associative memory 10 via the branches 57 and 58 and the decision logic 60 . Decision logic 62 is the same. inter alia with the control bits from field 16 and makes the jump destination address available for further processing.

With additional reference to FIG. 3, which represents a detail section from FIG. 2, which in this respect comprises the logic circuits 46 , 52 and 56 , the access to the cache memory 10 and the processing of the history information therein are described in more detail.

After the alignment of the branch instruction address at 46 , the content of the second tag fields 13 is compared in decision logic 52 with the corresponding information of the current history pattern for the best possible match. The second tag fields 13 preferably contain bit sequences as information patterns with regard to the direction of the branch instructions (global pattern history) previously run by the program, or with regard to the jump destination addresses of the branch instructions leading to the current branch instruction (path history) of the associated one, by the information in branch instruction described in the first tag field. In this regard, reference is made to the explanations given in the introduction to the description for further details.

The jump destination address whose second tag field best matches the current history bit sequence is then selected by comparison. This selection is made in a particularly preferred manner by comparing the identity of the bit sequences, starting from the left with the most significant bits corresponding to the more recent past and progressing to the right toward the older past. The longest, matching bit sequence, which can expediently be determined by bitwise XORing with the corresponding bit sequences of the current history, determines the branch destination to be predicted via branch 58 by the multiplex control in the decision logic 60 . These method steps of the bit-wise comparisons are all carried out in the decision logic 56 , which can be implemented, for example, as a programmable logic arrangement (PLA).

In Fig. 3, the above-mentioned, bitwise XOR operations are represented by arrows. Continued to the right in the figure, the comparisons with the other associatively assigned members of the set of associated history information of the branch instruction address are shown. The output arrow 70 signals the cache hit in the event that no jump destination address for a prediction was found in the memory 20 . The arrow 70 opens into an AND gate 71 in FIG. 2, which compares with the control bits of the flags from the field 16 . The arrow 72 represents the connection to the evaluation step, the arrow 58 represents the connection to the multiplex control for the selection of the correct jump destination address.

In the event that a jump destination address was incorrectly predicted, which only results from a comparison of the result of the evaluation step, the field 14 of the cache memory 10 storing the jump destination addresses should be updated.

For this reason, a result representing the quality - total agreement or partial agreement of the compared bit sequences - of the XOR comparison is forwarded by branch 72 to the evaluation step. If there is a total match, the jump destination address in field 14 , which has led to the incorrect prediction, is overwritten with the new address found by the evaluation step. If there is a partial match, which means that an entry with the special history information does not yet exist, the field 14 in the cache memory 10 which has not been used for a long time is overwritten with the new address.

In connection with the cache memory 10 according to the invention, the method according to the invention enables a cache memory for a plurality of destination addresses to be integrated into a conventional branch destination memory (BTB). Only slightly more false predictions have to be accepted.

Usually either history information patterns with regard to those that have been run by the program so far Branch commands (global pattern) or history Information pattern regarding the jump destination addresses of the to current branch instructions leading branch instructions (Path History Pattern) saved.

Both have their specific advantages and disadvantages, each lead to different good results after benchmarking.

It has been found, however, that in most cases an XOR combination of the two history information patterns despite their unequal density and as a result of the different numbers m and n of the branch instructions described by them with the same bit length, cf. Introduction to the description leads to the best prediction results. This combination is therefore proposed as being particularly preferred for storage in the second tag field 13 of the cache memory 10 .

Although the present invention is based on preferred Embodiments described above, it is not limited to this, but in a variety of ways modifiable.

In particular, the length of the mentioned tag fields can vary Expediency vary. Next are changes and Adjustments to the process foreseeable if - by the Peculiarities of the underlying program High-level language or due to the task of the program, or for another reason - the frequency of Branch instructions and the number of one Jump destination addresses assigned to the branch instruction vary.  

Reference list

10th

Cache memory

12th

first tag field

13

second tag field

14

Field for jump destination address

16

Identifier field

18th

Prediction field

20th

Branch destination store

22

Tag field f. low Bits

24th

Field f. Jump destination address

26

Flag

30th

Branch instruction address

32

Comparator

34

,

36

,

38

,

40

,

42

,

44

,

48

,

54

,

58

Branches

39

Decision logic

41

Decision logic

46

Comparator

52

Decision logic

53

History information

56

Decision logic, PLA

60

Decision logic

62

Decision logic

70

Branch with partial agreement

71

AND gate

72

Branch in complete agreement

Claims (10)

1. A method for predicting jump destination addresses during the processing of branch instructions of a program stored in a first memory of a computer, said branch instruction addresses ( 30 ) together with history information for writing and evaluating a tag field obtained from the program sequence associated with them in a second memory ( 10 ) with a shorter access time than that of the first memory, in order to enable selective access to the jump destination address to be predicted, certain address information to be assigned to the branch instruction addresses ( 30 ) being stored in a first tag field ( 12 ) of the second memory ( 10 ), characterized in that the history information is written into a second tag field ( 13 ) of the second memory and the selection of the jump destination address to be predicted by comparing the first tag field ( 12 ) with the address information of the branch instruction and by comparing the content of the second tag field ( 13 ) with the current history information ( 53 ) of the branch instruction to be processed. 2. The method according to claim 1, characterized in that the comparison is done bit by bit and the best Match by the length of the matching Bit sequence is set. 3. The method according to claim 1 or 2, characterized in that on the most likely jump destination address of a branch instruction without evaluating the history information ( 53 ) at a certain memory location in an integrated branch target memory ( 10 , 20 ). 4. The method according to claim 1 or 2, characterized in that in the event of incorrect jump destination prediction and complete agreement of the content of the second tag field ( 13 ) with the history information ( 53 ) of the currently processed instruction, the jump destination address of the associated entry in the branch destination memory ( 10 , 29 ) is overwritten with the correct jump destination address and, if there is partial agreement, the entry that has not been used for the longest time is preferably overwritten. 5. The method according to any one of the preceding claims, characterized in that in each case global pattern history information and / or path history information are stored in the second tag field ( 13 ). 6. The method according to the preceding claim, characterized in that a bit sequence is stored in the second tag field ( 13 ), which results from a combination of the global pattern and the path history information containing an XOR operation. 7. Device for performing the method according to one of the preceding claims, comprising the second memory ( 10 ) as a multiple-entry cache memory, the first tag field ( 12 ), the second tag field ( 13 ) and contains a field ( 14 ) for a jump destination address. 8. The device according to the preceding claim, characterized in that the second memory ( 10 ) additionally contains one or more identifier fields ( 16 ) for storing control information. 9. Apparatus for carrying out the method according to one of the preceding claims 1 to 6, characterized in that it contains a branch destination memory ( 20 ) which is set up for each branch instruction address ( 30 ) for storing at least one, preferably exactly, a branch destination address and in an integrated, Form with the second memory ( 10 ) is provided according to claim 8, wherein at least one additional identifier field ( 26 ) is provided for controlling the evaluation of the information present in the tag fields ( 12 , 13 ). 10. Device according to one of the preceding claims 7 to 9, characterized in that the second memory ( 10 ) is designed as a cache memory for storing a plurality of jump destination addresses with an associativity of preferably 8 to 16 and in a separate arrangement for cooperation with the branch destination memory ( 20 ) is set up, which in turn contains a branch destination address and control information ( 26 ) for each branch instruction address.