DE19919367A1 - Code-multiplex signal transmission - Google Patents

Abstract

The method includes the steps of encoding binary data to be transmitted with a predetermined spread code and a predetermined shuffling code, and filtering the thereby encoded data. The filtered data are weighed with a predetermined power weight factor, the weighed data are converted to an analogue signal, and the analogue signal is transmitted to a receiver. The binary data are especially complex data of a complex signal, which are preferably multiplied with a complex shuffling code, whereby produced individual components of the data are separately filtered and weighed, and are subsequently combined to form data of an in-phase component and a quadrature component.

Description

The present invention relates to a method and a Device for transmitting code division multiplex signals, esp special of WCDMA signals (Wideband Code Division Multiple Access).

When using code division multiplexing, for example in a digital (mobile) radio system all share Participants simultaneously the entire available System bandwidth. To avoid collisions between the individual parts To avoid participants, the binary data of each Provide participants with different code sequences, what leads to a spread of the respective transmission signal, so that the code sequences are also referred to as spreading code. The Receiver works synchronously with the code sequence of the transmitter and reverses the spread on the transmission side. By the despreading process in the receiver becomes only that signal relaxed again and thus reduced again in the range which has the same and synchronous spreading code as the Transmitter used.

For digital radio transmissions, especially when used the WCDMA method, the transmission signals must be in the data processing chain of the transmitter through a pulse shape filter before being mixed into the high frequency band and on be transmitted to a recipient. This pulse shape filter can be both analog behind a digital / analog converter Data processing chain of the sender as well as digital before Digital / analog converter can be arranged.

To avoid phase errors and because of the problemati The manufacturing tolerances of analog components are shown above described pulse shape filter, however, preferably digitally  leads, as a rule digital FIR filters (Finite Impulse Response) can be used. These digital FIR filters have the disadvantage that they have a large number of adders and Multipliers need those with a large data word are wide to operate. In addition, such filters are used the preferred application in the present case in digital Mobile radio systems operated with very high clock frequencies. A typical FIR filter is used in this application for example 33 multipliers (each 8 bit data words multiply by 9 bit data words) and 32 adders (8 bit + 8 bit) and is loaded with a frequency of 32 MHz drove. The fact described above has the consequence that on the one hand, a large number of such digital FIR filters of gates and on the other hand the power consumption is high.

An example of a known WCDMA transmitter is shown in Fig. 7, wherein the currently known solutions assume that the binary data of the individual data streams A, B are first spread with the aid of multipliers 1 with a channel-specific spreading code and then with the aid of further Mul tiplier 2 weighted with an also channel-specific performance factor, ie evaluated. Subsequently, the data of further channels are added simultaneously with the aid of adders 3 and the results are scrambled with the aid of a scrambling code. This is usually a complex scrambling code that is applied to also complex binary data (A + jB). For multiplication with the scrambling code, multipliers 4 for the real scrambling code component and multipliers 5 for the imaginary scrambling code component and adders 6 are thus provided separately.

The resulting I and Q components are then either passed directly via a digital / analog converter 8 (D / A converter) and then filtered or (as shown in FIG. 7) first filtered using a digital filter 7 and then changed. In addition, methods are also known in which filtering takes place both before and after the D / A converter 8 .

The present invention is based on this state the technology based the task, a method and a pre direction to transmit code multiplex signals fen, which simplifies the construction of the Im pulse shape filter is enabled.

This object is achieved by a method with the features of claim 1 and a device with the Features of claim 5 solved. The subclaims be write preferred and advantageous execution form men of the invention.

According to the present invention, those to be transmitted binary data of a channel is only encoded with a spreading code, d. H. spread, then with a scrambling code (Scrambling Code) encoded, i.e. H. scrambled, and then filmed tert. That is, the binary data is filtered before using weighted according to the respective power factor and with the data other channels are overlaid.

The advantage of this structure is that it ver applied digital pulse shape filter can be easily constructed can, because the data supplied to the filter due to the binary only two values (+1, -1) can.

The filter can, for example, by combining a Spei chers, in which individual samples of the filter impulse response are stored with a shift register for addressing the Memory.

There is also the possibility of filtering through several re parallel filter branches to which individual Im  pulse response parts of the filter are divided, which on concluding the final impulse response of the filter be binated.

According to a further preferred exemplary embodiment, a Logic is provided for the filter, which ensures that the usually with transient or decay processes related problems of the filter structure described above ver can be avoided.

The present invention is preferred in the field of Mobile radio, in particular in WCDMA transmission units from Mobil share or base stations used. Beyond that use in other areas of application also possible those using spreading / scrambling and pulse shaping is made such. B. in Powerline communication.

The invention is described below with the aid of a preferred embodiment Rungsbeispiele explained with reference to the drawing.

Fig. 1 shows an exemplary structure of a erfindungsge MAESSEN WCDMA transmitter for explaining the principle of the invention vorlie constricting,

Fig. 2 shows schematically the structure of a filter assembly shown in FIG. 1 according to a first embodiment of the invention,

Fig. 3 shows schematically the structure of a filter assembly shown in FIG. 1 according to a second embodiment of the invention,

Fig. 4 schematically shows the structure of a filter assembly shown in FIG. 1 according to a third embodiment of the invention,

Fig. 5 shows schematically the structure of a filter assembly shown in FIG. 1 according to a fourth embodiment of the invention,

FIG. 6 schematically shows the structure of a filter arrangement shown in FIG. 1 according to a fifth exemplary embodiment of the invention, and

Fig. 7 shows an example of the structure of a known WCDMA transmitter.

As shown in FIG. 1, the known structure shown in FIG. 7 is modified in such a way that the binary data A, B of a channel are first spread using a multiplier 1 using a spreading code and then immediately using corresponding multipliers 4 , 5 scrambled with a scrambling code and filtered using digital filter 7 . Only then are the data processed in this way weighted with the respective power factor via multiplier 2 and superimposed in adders 3 with the corresponding previously processed binary data of further channels. Finally, in D / A converters 8, the conversion into analogue transmission signals takes place, which are transmitted via the air interface or the high-frequency part 9 of the transmitter shown in FIG. 1 to a receiver, for example a base station of a mobile radio network operator. The present invention thus differs from the known structure shown in FIG. 7 essentially in the order of processing the binary data of the individual channels, the scrambling and the filtering being preferred over the weighting with the power factor according to the invention. The advantage of this structure is that the data supplied to the individual filters 7 can only assume two values (+1, -1) due to the binary transmission method, so that a filter 7 is constructed very simply and, for example, by means of a ROM memory or another Ren very simple memory can be replaced, which will be described in more detail below.

The structure shown in FIG. 1 is a complex WCDMA transmitter, ie after the spreading with the spreading code, the complex binary data A, B of a channel are multiplied separately by a scrambling code component, filtered separately and weighted separately , wherein the power factor for the A component data and B component data of a channel is identical. With the help of the adders 3 , the I-component data or Q-component data of the individual channels are added and finally converted to digital analog separately.

The filters 7 shown in FIG. 1 are in particular so-called digital RRC filters. The weighting of the individual data is advantageously carried out with the aid of a multiple xer or can be configured as hard-wired if the weighting value or power factor does not change. If necessary, the weighting can also be carried out by a digital multiplier (e.g. 4 × 8 bits).

An exemplary construction of a filter 7 shown in FIG. 1 is shown in FIG. 2. In this case, the filter 7 consists of a shift register 11 , into which the binary data to be transmitted are shifted with a certain data frequency ft, a counter 10 running synchronously with a certain oversampling frequency fs of the transmitter and a ROM memory 12 . The oversampling frequency fs is, for example, 32 MHz, while the data frequency ft is, for example, 4 MHz, the binary data of a channel being spread and scrambled and supplied to the shift register 11, for example with a data word length of 1 bit.

In the embodiment shown in FIG. 2, the counter 10 is in the form of a 3-bit counter and the shift register 11 is in the form of an 8-bit shift register, so that the shift register 11 keeps eight consecutive data values. Correspondingly, the downstream ROM memory 12 is always driven by a 3-bit data word from the counter 10 and an 8-bit data word from the shift register 11 . Corresponding result or readout values for all possible data value combinations of the shift register 11 are stored in the ROM memory 12 for all oversampling times. These result values to be stored are calculated as the additive superimposition of the filter impulse responses belonging to the individual values of a data value sequence and are read out from the ROM memory 12 in synchronism with the oversampling clock fs.

The, for example, 8-bit result values read from the ROM memory 12 are fed to a multiplexer or multiplier 2 , which weights the result values with the respective power factor. Channels that are not used can be taken into account in that the power factor is set to the value "0" for them. The downstream elements 3 , 6 and 8 correspond to the adders 3 and 6 or the D / A converter 8 shown in FIG. 1 and each operate at the oversampling frequency fs.

The length of the impulse responses to be stored or the sampling frequency and the data word width are linearly involved in the complexity of the ROM memory 12 , while the number of individual impulse responses exponentially enters the complexity of the ROM memory 12 in accordance with the shift register length.

In the case of a multi-code transmitter which has, for example, two data channels and one control channel, the filter structure 10-12 shown in FIG. 2 must be integrated six times with the subsequent multiplexer 2 . Allows the actual chip technology correspondingly higher clock rates, instead of the implementation of multiple parallel data paths also a time-division multiplex-activation of a smaller number of assemblies 7 Filteran possible, in which case a minimal Fil teranordnung is required. 7

If the superposition of a large number of individual impulse responses is neces sary when displaying filters 7 of higher order, several filter arrangements 7 can be operated in parallel with a corresponding offset of the sampling time. (In addition, there is also the possibility of time-division multiplex activation of the filter arrangements in this case.) Both the superposition of several complete curves (or only one complete curve) and only one partial curve can be stored in each filter block or in each filter arrangement . The output signals of the individual filter blocks are then superimposed with the aid of a downstream adder.

An example of this principle is shown in FIG. 3 for the case of only one single impulse response per filter block. In this exemplary embodiment, only the filter is stored in the form of a curve for the two states of a binary character in a ROM memory. The superimposition of the various instantaneous values of the individual characters is carried out by an external summing element.

As shown in Fig. 3, the filter structure or filter arrangement 7 comprises on the input side a multiplexer 13 , in the example shown a 1: 8 multiplexer, several curve generators 14 controlled via one bit of the multiplexer 13 , each of which has an 8 bit on the output side Output data word with the oversampling frequency fs, and a summing element 17 already mentioned. The filter arrangement 7 ft to the data frequency (eg, 4 MHz) bitwise to guided spread and scrambled binary data is supplied via the multiplexer 13 the curve generators 14 in a round-running mode, that is, the individual curve genes generators 14 provide an output of Mul successively each tiplexers 13 supplied and stored in a 1 bit memory 15 of the corresponding curve generator 14 (with a bit frequency of, for example, 4 MHz ÷ 8). After eight cycles, the data value stored in the corresponding memory 15 is replaced by a new bit of the multiplexer 13 . Each curve generator 14 also includes a counter 20 , for example a 6-bit counter, which counts all the positions of the curve with the oversampling frequency fs. The 1-bit memory 15 points to the positive or negative curve shape corresponding to the data and, together with the corresponding counter 20, supplies an address (for example a 7-bit address) for a ROM memory 16 at each sampling point in time, which is identical to that shown in FIG . shown ROM 2 is comparable to the 12th The ROM 16 thus outputs the corresponding value of the selected waveform, for example in the form of an 8-bit data word, at each sampling time of the oversampling frequency fs. Each of the curve generators 14 shown in FIG. 3 has an identical structure, so that the structure of the first curve generator 14 is only shown as an example in FIG. 3. The sampled values provided by the individual curve generators 14 are added in the summing element 17 and supplied with the oversampling frequency fs to the multiplexer 2 already explained with reference to FIG. 2 for power factor evaluation. After minor modifications, time division multiplexing of the curve generators 14 is possible.

In Fig. 4, another embodiment for the configuration of the filter 7 shown in Fig. 1 is shown. Each filter branch or filter block comprises a ROM memory 12 which has already been explained with reference to FIG. 2 and which is controlled in each case by an output partial value of the shift register 11 and the counter 10 (cf. FIG. 2). Each filter block provides a time period of the filter impulse response, similar to the exemplary embodiment shown in FIG. 3 here, too, a plurality of impulse response parts being divided into parallel filter branches.

The example shown in FIG. 4 is an example of a filter of length 32 with eight times oversampling (fs = 32 MHz) at a data frequency of ft = 4 MHz. The filter shown in FIG. 4 thus corresponds to a 256 tap FIR filter. The continuously spread and scrambled data stream is supplied to the shift register 11 , which in the present case is a 32-bit shift register, the 4 × 8 bit output signals of which, together with the 3-bit output signal of the 3-bit counter 10, the individual ROM Address memory 12 . As in the embodiment shown in FIG. 2, the data-dependent parts of the ROM memory addressing are made by the shift register 11 , while the counter 10 takes over the remaining part of the ROM memory addressing with respect to oversampling. In each ROM memory 12 , the superimposed impulse response parts of the possible combinations of, for example, eight adjacent input data are stored for a period of the total filter impulse response, so that the final 8-bit filter impulse response by combining the individual impulse responses with the aid of the summing element 17 can be obtained.

In Fig. 5, another embodiment for the configuration of the filter 7 is shown, this embodiment example representing a development of the arrangement shown in Fig. 2. In this exemplary embodiment, the multiplexer 2 required according to FIG. 2 is integrated in the ROM memory 12 . For this purpose, the curve profiles of the filter impulse response associated with the individual power or weighting factors or the corresponding sample values are additionally stored in the ROM memory 12 , so that depending on the power factor defined, for example, via a 4-bit data word, the from the counter 10 and the shift register 11 delivered address signal corresponding sample of the matching curve can be read out. Otherwise, the functioning of this exemplary embodiment corresponds to that of the exemplary embodiment shown in FIG. 2, although the memory requirement of the ROM memory 12 inevitably increases in accordance with the resolution of the weighting.

The previously described embodiments for the filter 7 shown in Fig. 1 assume that the individual Fil tern 7 a continuous data stream is supplied. However, should the data stream be switched on or off, swing-in or swing-out problems arise which are based on the fact that only 1-bit memory is used to store the states "+1" and "-1". However, at the moment a channel is switched on, the data values of the first characters that are not yet valid and at the time of switching off the data values of the subsequent characters must correspond to the defined value "0".

This problem can be solved by using a larger memory. Accordingly, the superimposition of further curves for determining the filter impulse response are to be stored in the ROM memory 12 , with these additional curves taking into account that the symbols or characters to be filtered have different levels.

In FIG. 6, a development of off shown in Fig. 2 is shown with a guide example logic for turning on and decay, wherein the logic comprises an additional memory 18 and an additional one-time counter 19. The memory 18 can be implemented by a 1-bit memory, while the one-time counter 19 can, for example, deliver a 3-bit output signal which, together with the output signal of the memory 18, drives the ROM memory 12 . As he already mentioned, additional sample values are stored in the ROM memory 12 , so that the ROM memory 12 has an increased memory requirement compared to FIG . Both the memory 18 and the one-time counter 19 are activated by a start signal, the memory 18 also receiving a control signal indicating the on or off oscillation state, while the one-time counter 19 operates at the data frequency ft (for example 4 MHz) becomes. The one-time counter 19 is used in combination with the memory 18 to generate additional addresses for the ROM memory 12 , among which samples for the pulse response are stored, which take the incoming or outgoing zeros into account when settling in or out, so that when these special addresses occur, the ROM memory 12 inevitably outputs imupl responses for incoming zeros in the event of a settling process and impulse responses for leading zeros in the case of a decaying process.

Claims (22)

1. A method for transmitting code division multiplex signals, comprising the steps:

• a) coding of binary data to be transmitted with a certain spreading code and a certain scrambling code,
• b) filtering the data thus encoded,
• c) weighting of the filtered data with a certain power factor,
• d) converting the data weighted by the power factor into an analog signal, and
• e) transmitting the analog signal to a receiver.

2. The method according to claim 1, characterized, that the binary data is complex data of a complex signal, which in step a) with a complex scrambling code are multiplied. 3. The method according to claim 2, characterized, that in steps b) and c) get individual in step a) components of the complex multiplication with the com complex scrambling code filtered separately, separately with a Power factor weighted and then to data of an in- Phase component and data of a quadrature component combi be kidneyed, each subjected to steps d) and e) become. 4. The method according to claim 3, d ä marked by that the data of the in-phase component and the data of the Qua dratur component after step c) corresponding and transmit data to at least one other channel adds and subjected to steps d) and e), the previously added data also steps a) -c) un have been trained.   5. Device for transmitting code multiplex signals, with a coding device ( 1 , 4 , 5 ) for coding binary data to be transmitted with a specific spreading code and a specific scrambling code,
with a filter device ( 7 ) for filtering the thus coded data,
with a weighting device ( 2 ) for weighting the filtered data with a specific power factor,
with a digital / analog converter device ( 8 ) for converting the data weighted with the determined power factor into an analog signal, and
with a transmitting device ( 9 ) for transmitting the analog signal to a receiver. 6. The device according to claim 5, characterized in that the binary data are in complex form, and that the complex binary data from the coding device ( 1 , 4 , 5 ) are multiplied by a complex scrambling code. 7. The device according to claim 6, characterized in that
that a filter device ( 7 ) and a weighting device ( 2 ) is provided for individual components of the complex multiplication performed by the coding device ( 1 , 4 , 5 ), and
that adding devices ( 6 ) are provided which add the data supplied by the individual weighting devices ( 2 ) to data of an in-phase component and data of a quadrature component, each of which has a corresponding digital / analog converter device ( 8 ) and one corresponding transmission device ( 9 ) are supplied. 8. The device according to claim 7, characterized in that for the branch of the in-phase component and the branch of the quadrature component each a further adding device ( 3 ) is provided, which the data of the in-phase component or the quadrature Component added with corresponding data of the in-phase component and the quadrature component of at least one further channel. 9. Device according to one of claims 5-8, characterized in that the weighting device ( 2 ) is formed by a multiplexer for multiplying the filtered data output by the filter arrangement ( 7 ) with the determined power factor. 10. Device according to one of claims 5-9, characterized in
that the filter arrangement ( 7 ) comprises a shift register ( 11 ) and a memory arrangement ( 12 ),
that the shift register ( 11 ), the binary data output by the encoder ( 1 , 4 , 5 ) with a certain data frequency (ft) are supplied, and
that a filter impulse response is stored in the memory arrangement ( 12 ) for each combination of the data values held in the shift register ( 11 ),
wherein the filter impulse response associated with these data values is read out as filtered data from the memory arrangement ( 12 ) depending on the data values currently held in the shift register ( 11 ) with a specific operating frequency (fs). 11. The device according to claim 10, characterized in that the filter device ( 7 ) comprises a with the operating frequency (fs) clocked counter ( 10 ) for generating a control signal for the memory arrangement ( 12 ). 12. The device according to any one of claims 5-8 and according to claim 10 or 11, characterized in that the weighting device is integrated in the memory arrangement ( 12 ) such that in the memory arrangement ( 12 ) for each combination of those in the shift register ( 11th ) held data values and for each power factor a filter impulse response is stored, with the memory arrangement ( 12 ) depending on the data values currently held in the shift register ( 11 ) and the power factor to be fed to the memory arrangement ( 12 ) with a specific operating frequency ( fs) the filter impulse response assigned to these data values and this power factor is read out as filtered and weighted data. 13. Device according to one of claims 10-12, characterized in that
that special samples for determining the filter impulse response are stored in the memory arrangement ( 12 ) for transient and oscillation cases, and
that a logic (18, 19) is provided which receives a Steuersi gnal, which indicates whether a transient or off exists oscillating fall, and in this case, the specific samples of the memory array (12) adressierendes Adres sensignal for the memory array (12 ) generated. 14. The apparatus according to claim 13, characterized in that the special len sample values stored in the memory arrangement ( 12 ) for the transient response of the impulse response for leading zeros and for the decay case correspond to the pulse response for trailing zeros. 15. The apparatus of claim 13 or 14, characterized in that the logic comprises a one-time counter ( 19 ) clocked with the data frequency (ft) and a memory ( 18 ) receiving the control signal. 16. Device according to one of claims 5-9, characterized in that the filter device ( 7 ) comprises a plurality of filter blocks operated in parallel and an adding device ( 17 ) for adding the individual output signals of the individual filter blocks, each filter block having a partial impulse response for that of the filter device ( 7 ) supplies binary data. 17. The apparatus according to claim 16, characterized in
that the filter device ( 7 ) on the input side comprises a multiple xer ( 13 ) to which the binary data of the coding device ( 4 , 5 ) are supplied with a certain data frequency (ft), and
that each filter block ( 14 ) is designed in the form of a curve generator with a first memory ( 15 ), a counter ( 20 ) and a second memory ( 16 ),
wherein in every second memory ( 16 ) samples of a complete impulse response of a positive and a negative pulse are stored, which are addressed via an output signal of the counter ( 20 ) and the first memory ( 15 ) of the same filter block ( 14 ), and
wherein the multiplexer ( 13 ) cyclically addresses the first memories ( 15 ) of the individual filter blocks ( 14 ) and the counter ( 20 ) of the individual filter blocks ( 14 ) with a certain operating frequency (fs) depending on the binary data value supplied to it samples stored in the corresponding second memory ( 16 ) are counted. 18. The apparatus according to claim 17, characterized in that the samples of the same curve profiles are stored in the second memories ( 16 ) of the individual filter blocks ( 14 ). 19. The apparatus according to claim 18, characterized in that each filter block comprises a memory arrangement ( 12 ) which is addressed by a shift register ( 11 ),
wherein the shift register ( 11 ) from the coding device ( 1 , 4 , 5 ) output binary data for generating corre sponding address signals for the individual memory arrays ( 12 ) are supplied, and
wherein from each memory arrangement ( 12 ), depending on the corresponding address signal, a sample value stored therein with a specific operating frequency (fs) is read out as a partial impulse response and supplied to the adding device ( 17 ). 20. The apparatus according to claim 19, characterized in that the memory arrangements ( 12 ) of the individual filter blocks are controlled jointly by a counter clocked with the operating frequency ( 10 ). 21. Device according to one of claims 5-20, characterized in that the coding device comprises a first coding unit ( 1 ) for coding the binary data to be transmitted with the determined spreading code and a second coding unit ( 4 , 5 ) for coding the with Spread code encoded data with the scrambling code includes. 22. Use of a device according to one of claims 5- 21 in a WCDMA transmission arrangement of a mobile radio system.