DE19827026A1 - Synchronous counter for high clock rates - Google Patents

Abstract

The counter has toggle stages and gates. At least the higher value counter toggle stages (CL) apart from the highest value stage each have an associated additional memory toggle stage. The inputs of the higher value counter toggle stages are each connected to a logic circuit. The output signal of the previous lower value counter toggle stage and its associated memory stage are fed to the logic circuit. Preferably the toggle stages are D type flip flops. Alternatively the counter toggle stages may be a JK flip flops. The logic circuit may be an AND gate which outputs a logic signal.

Description

The invention relates to a synchronous counter for high clock occurred with flip-flops and logic circuits, the inputs the counter flip-flops are upstream.

Synchronous counters / frequency dividers are in digital technology known for a long time. They are called integrated circuits manufactured or realized in Asics. To control the tilt stages are in data inputs of the higher-order flip-flops Logic circuits upstream. This counter type is at for example in "semiconductor circuit technology" from Tietze and Schenk, Springer Verlag, 9th edition on pages 243-247 explained.

The problem with the counter circuits is that either the logic circuits have to be cascaded or - especially with D flip-flops - particularly complicated logic circuits are required, the inputs of which are the outputs all previous flip-flops must be fed.

The object of the invention is therefore to reali a simple specifying counter for high frequencies.

A counter according to the invention is described in claim 1. Advantageous further developments are in the subclaims given.

The regular architecture of the Counter, so that this for integration and implementation in Gate arrays is suitable.

Embodiments of the invention are based on figures described in more detail.  

Show it:

Fig. 1 shows a first embodiment of the invention,

Fig. 2 shows an embodiment with D flip-flops and

Fig. 3 examples of logic circuits.

In Fig. 1 is a synchronous counter with JK flip-flops Darge provides. These flip-flops have internal feedback from the output to the input, which is activated when the corresponding data input and the clock input are at logic 1. If both data inputs are at logic 1, the logic state of the flip-flop changes after the next clock pulse.

The binary synchronous counter contains counter flip-flops CF0-CFn (FF - flip-flop / flip-flop). The least significant most often their state-changing flip-flop is designated CF0, which highest quality with CFn. These flip-flops give that down tigest bit LSB or the most significant bit MSB.

Each counter flip-flop CF1-CFn-1 is a memory niskippstufe MS1-MSn-1 (M - Memory) assigned, the Da input D each with a data output Q the counter flip stage is connected. The least significant counter flip level än changes with each clock pulse, the state of the second tilt stage CF1 with every second clock pulse, etc. The logical close Levels of flip-flops MF1-MFn-1 correspond to those of ordered flip-flop - however, they are spaced two consecutive clock pulses delayed. This temporal Delay is exploited to be as simple as possible via logic circuits L2-Ln a time range between two Clock pulses within the counting period of the affected count tipping out to change the state of the to initiate the next higher flip-flop. Using JK flip-flops can do this by an AND operation (or OR link depending on the selected input signal len).  

With the low-level counter flip-flops, the memory flip flop can be dispensed with; in Fig. 1 this has only happened at the least significant flip-flop.

Fig. 2 shows a synchronous counter constructed with D flip-flops. These flip-flops take over the logic signal at data input D with the next clock pulse. In principle, the counter circuit is constructed in the same way. A logic circuit CD0 to CDn is connected upstream of the inputs of the D flip-flops CD0-CDn. With the least significant flip-flops CD0, this consists of an inverter that is switched on between output Q and data input D (or the inverting data output is connected directly to the data input). For the next higher-order D counter flip-flop CD1, the logic circuit CL1 consists of an exclusive OR gate (exclusive NOR gate) and in the higher order flip-flops each from the combination of an AND gate and an exclusive OR gate ( Fig. 3).

With the help of the memory flip-flops MF1-MFn-1 each the state gated out, starting from the counter was 0 the counter flip-flop goes to logical 1 and the logical state of the memory flip-flop still on the logi is 0.

A counting method is achieved for both counters, which does not correspond to the dual counting method, however includes all combinations so that the same count period is aimed.

In Fig. 3, the logic circuit for the counter flip-flops CF2-CFn is shown, which consists of an AND gate, which has an inverting input, and an exclusive OR gate ter.

Fig. 4 shows the implementation with a multiplexer MUX, the inputs A and B of the data output Q or the inverted data output Q is fed across and the control input S is connected to the output of one of the AND gates AND. Boolean transformations are of course possible.

The realization of a fast synchronous counter is not on the use of the tilt provided in the examples step types limited.

Claims (5)

1. Synchronous counter with flip-flops and gates, characterized in
that at least the higher-order counter flip-flops (CL1-CLn-1) - apart from the highest-order counter flip-flop (CLn) - are each assigned a further memory flip-flop (HF1 to HFn-1), which adopts the logical state of the counter flip-flop one clock pulse later , and
that inputs of the higher-order counter flip-flops (CF3 to CFn-1) each have a logic circuit (L2, ...; CL0, CL2, ...) connected upstream, which outputs the output signal of the previous lower-order counter flip-flop (CF1-CFn-1; CD1 - CDn-1) and their associated memory flip-flop (NF1-MFn-1) is supplied. 2. Synchronous counter according to claim 1, characterized, that provided as counter flip flops JK flip flops (CF0-CFn) hen are. 3. Synchronous counter according to claim 1, characterized, that as counter and memory flip flops D flip flops, the have a data input (D), are provided and that the Logic circuits (CL1 to CLn) of a higher order counter flip-flop (CD2-CDn-1) each have an output signal from the previous going lower-order counter flip-flop (CD1-CDn-1) and their assigned memory flip-flop (MF1-MFn-1) and her own output signal is supplied, 4. Synchronous counter according to claim 2, characterized, that an AND operation is provided as the logic circuit, which emits a logical signal.   5. Synchronous counter according to claim 2, characterized, that as a logic circuit an AND operation with nachgeschal Exclusive OR / NOR link is provided.