DE19742958A1 - Co-processor for signal decoding for e.g. mobile telephone - Google Patents

Abstract

The co-processor (10) provides the auxiliary functions for a Viterbi decoding method using a metric calculator (20), which has an input value read in for each trellis step, for calculating several branch metrics, e.g. upper and lower branches, with a memory (24) holding condition metrics, e.g. old and new metrics. A path selection device (22) calculates new metrics and output values (TRAN, MAXU, MAXL) using the calculated branch metrics and the stored condition metrics, with the new condition metrics stored in the memory.

Description

The invention relates to a coprocessor and a signal processing device. In particular, the invention is for Use when decoding signals according to the Viterbi Appropriate method or related method. The invention can for example in a mobile phone, in particular a telephone according to the GSM standard (GSM = Global System for Mobile Communications) can be used.

For the transmission of digital data over a disturbed channel redundant coding methods are often used to over to be able to correct as far as possible wearing errors. In such a method that according to the GSM standard used for mobile phones is a convolutive Coding of the sent data is provided. In a convoy Each data bit to be sent is followed by educational coding a predetermined scheme with data bits sent earlier connected. There is usually a shift control in the transmitter ster provided with a suitable linking device.

The received data are processed using a Viterbi method with probability-based decisions (soft deci sions) decoded. Such a procedure is in the article "The Viterbi Algorithm" by G. David Forney, Jr. in Proceedings of the IEEE, March 1973, pages 268-278, be wrote. A so-called trellis is used in this process as a logical structure. A trellis represents you "rolled up" sequence of states and transitions in the transmitter Each trellis step corresponds to a bit sent.

Fig. 6 shows an example of such a trellis step in a system having four states s = 0, 1, 2, 3. The four al th states is assigned to each of a designated as a metric plausibility lichkeitswert old_metric (s). This value indicates the probability that the old state s has been reached by a path determined in the previous Viterbi procedure.

A received bit is evaluated in the i-th trellis step shown in FIG . For this purpose, the values upper_branch (s) and lower_branch (s) are determined for each new state s, which designate the probability calculated on the basis of the received data, whether the received bit is a "0" transition or a "1" transition in the transmitter represents. These two possibilities are illustrated by arrows in FIG. 6, the solid arrows indicating an upper branch (corresponding to a "0" transition in the transmitter) and the dashed arrows indicating a lower branch (corresponding to a "1" transition). In order to calculate a new metric new_metric (s) for each new state, the most probable extension of the previously determined paths is determined. For example, the following formula is evaluated for the new state 1:

new_metric (1) = max ((old_metric (2) + upper_branch (1)),
(old_metric (3) + lower_branch (1))).

The "+" sign here denotes an operation to inflate probabilities. If the probability represented by negative logarithms this operation the ordinary addition.

For future trellis steps, every new state takes only one path into account, namely the one that was judged to be more likely. All other paths who the discarded. As a data sent according to the GSM standard block must always end in state 0 of the transmitter Receive a data block based on the information received most likely path. The whole The process described so far is called channel decoding (channel decoding).  

A situation that is associated with the convolutive coding Shift register and a logic device compare bar is also in the radio transmission of the transmission signals in front. Reflections of the transmitted signals result in un Different long transmission distances between the transmitter and the receiver, which together in the antenna of the receiver men walking. The multipath propagation cause channel distortion gene returned by an equalizer in the receiver should be made common. Since the multipath spread in their physical effect is roughly a convolutive one Corresponds to coding, a procedure is also used for equalization ren used, the Viterbi process for sewer decoration dation is very similar and therefore also in the following should be referred to as the Viterbi process. The difference the method described above is used in each Trellis step the highest metric of all "1" transitions and calculates the highest metric of all "0" transitions to that most likely received bits in this step teln.

Required for the two versions of the Viterbi process Such calculations are relatively complex since they are in Must be done in real time. If a program controlled processor provided for executing the method is, this must be efficient and clocked quickly. This is complex and particularly problematic in radio telephones Matic, because many other processes run out in real time must be managed and because of the performance a processor in general also increases its power consumption takes. Dedicated hardware circuits for the Viterbi-Ver Driving, however, are usually not very flexible and can only ent do neither equalization nor channel decoding. A relatively large chip area is therefore required.

The invention accordingly has the task of the mentioned Pro solve problems and provide funds that allow  a Viterbi process with sufficient throughput at gerin low processor load and with relatively little hardware effort to perform.

According to the invention, this task is performed by a coprocessor with the features of claim 1 and by a Signalver working device with the features of claim 11 ge solves.

The invention is based on the basic idea, the Viterbi process Ren to divide appropriately, so that often repeated calculations outsourced to a dedicated coprocessor. Surprisingly, this is possible in a way that very little communication effort between the coprocessor and a main processor with a high degree of swapping allow necessary calculations. The solution according to the invention relies on the trellis step as the interface between the coprocessor and the main processor or another To provide control device. With every trellis step at least some input and output values over this cut job exchanged. The branch calculated by the coprocessor However, metrics are stored in a storage device of the Ko processor held and from trellis step to trellis step updated.

The invention enables a large number of coprocessors repetitive process steps are outsourced, so that the main processor is relieved of other tasks and generally no such powerful main processor used must become. The outsourced process steps are true very numerous, but not particularly complex in each case. It are essentially additions, comparisons and Assignments. The coprocessor therefore only needs a small amount Chip area. Because the coprocessor does not have the complete Vi executes the terbi process, it is flexible and can be integrated into use a variety of different operating modes.  

The coprocessor preferably processes each individual trellis step independently, d. H. after a start signal from the main processor without further interaction with the main processor. The calculations carried out by the coprocessor can then run parallel to processes in the main processor.

The output values calculated by the coprocessor are preferred Transition values and / or maximum metric values and / or others Values of interest for further signal processing are. Values are referred to here as maximum metric values that correspond to a maximum probability. Depending on the representation of the probabilities (for the game as positive or negative logarithm) can be Values by maximum formation or by a minimum bil calculation or by other operations.

The coprocessor is preferred both for equalization and can be used for channel decoding. This allows one particularly flexible use of the coprocessor. When equalizing in preferred embodiments, setpoints for calculating the Branch metrics used.

The coprocessor provides for storing the state metrics preferably a memory device with several memory banks ken, in preferred embodiments a paral Read access or parallel read access to minde At least two of these memory banks are provided. This will the processing speed increased.

In preferred embodiments, the coprocessor is as hard-wired hardware circuit and the main processor as programmable processor. This allows a ho he processing speed of the coprocessor at the same early flexible control and flexible pre- and post-processing Processing of the data by the main processor. The coprocessor and the main processor communicate in preferred embodiment forms predominantly or mainly via input  and / or output registers, which are also during processing part of a trellis step from the main processor are legible and / or writable.

Further preferred embodiments of the invention are Ge subject of the subclaims.

An embodiment currently preferred by the inventors example of the invention and several alternative embodiments will now be more precise with reference to the drawings wrote. They represent:

Fig. 1 is a block diagram of some components of a processing device signal,

Fig. 2 shows a data flow of the occurring defects in a coprocessor Tenden data streams,

Fig. 3 is a flowchart of processing of a Trellisschritts in a path selection device,

Fig. 4 is a state diagram of the processing of a trellis step by the coprocessor,

FIGS. 5a to Fig. 5c waveforms of the communication between a main processor and the coprocessor, and

Fig. 6 is an exemplary illustration of a Trellisschritts.

The signal processing device shown in detail in FIG. 1 is designed as an integrated circuit for use in a GSM mobile phone. A coprocessor 10 and a digital signal processor serving as the main processor 12 are connected to one another via a bus 14 . Components such as a memory device 16 , an input / output device 18 and other modules, for example timers, are also connected to the bus 14 , which has a width of 16 bits, for example. With the exception of the coprocessor 10 , the components of the signal processing device listed in this paragraph are known per se.

The coprocessor 10 , as illustrated in FIG. 2, has a metric calculation device 20 , a path selection device 22 and a storage device 24 . The storage device 24 is in turn divided into four memory banks 26 a to 26 d, each of which has 32 memory words of 16 bits each. The path selection device 22 is connected via a line bundle with the four memory banks 26 a to 26 d, so that parallel access to the memory device 24 is possible. In the embodiment described here, two memory banks are read and one memory bank is written in a single cycle. This corresponds to parallel access to three memory banks or parallel read access to two memory banks.

The arrows shown in FIG. 2 represent data flows between the elements of the coprocessor 10 or from and to the main processor 12 . In the exemplary embodiment described here, communication takes place between the coprocessor 10 and the main processor 12 via registers of the coprocessor 10 , which the main processor 12 accesses via the bus 14 . The address of the register to be addressed, a read / write indication and the data to be written or read out are transmitted on the bus 14 . In contrast, within the coprocessor 10 line bundles for data exchange between the metric calculation device 20 , the path selection device 22 and the storage device 24 are provided. In alternative embodiments, the data flows shown in FIG. 2 can be transmitted through other hardware structures.

The registers of the coprocessor 10 are used both for communication with the main processor 12 and for holding values that are required in the coprocessor 10 during the calculation process. In the exemplary embodiment described here, the registers are each 16 bits wide. A control register, a status register, nine input registers INP (0: 8), four transition registers for storing a maximum of 64 transition bits TRAN (0: 63) and two registers for storing two maximum metric values MAXU and MAXL are provided. In alternative embodiments, other data values can be stored and exchanged between the coprocessor 10 and the main processor 12 . For example, in addition to the transition bits TRAN (0: 63), trust values can be output for the individual transitions.

The status register stores the control values VTCEQ, VTCSTATE and VTCRATE. These control values are set by the signal processor 12 by writing to the status register in order to adapt the work of the coprocessor 10 to the current requirements. The control value VTCEQ determines whether the coprocessor should work for equalization or for channel decoding. The control values VTCSTATE and VTCRATE indicate the number of trellis states or the data rate (ratio of bits transmitted via the channel to actual data bits) in the channel decoding mode. In the exemplary embodiment described here, the coprocessor 10 supports 16 and 64 states such as data rates of 1/2, 1/3 and 1/6. Other control values and other status numbers and data rates are possible in alternative embodiments.

In the equalization mode, which is always based on a trellis with 16 states, a total of eight setpoints are generated by the main processor 12 in preparation for the processing of a data block and are written into the input registers INP1 to INP8. These setpoints are derived from an estimated channel impulse response for the radio transmission link and correspond to an expected output signal of a receiver module of the mobile phone for each bit sent in every state. Because either a "0" or a "1" can be sent in each of the 16 states, theoretically 32 setpoints can occur, but only eight have to be calculated for reasons of symmetry.

For each trellis step (ie each bit received), the main processor 12 now writes a further input value with a width of 10 bits into the input register INP0. This input value corresponds to the value actually received by the mobile phone, which was digitized by an analog / digital converter and suitably processed by a preprocessing device. After being triggered by the main processor 12 , the coprocessor 10 now automatically calculates 32 branch metrics, namely a branch metric upper_branch (s) for each of the 16 states s, which indicates the probability of a “0” transition in the transmitter, and a branch metric lower_branch (s) indicating the probability of a "1" transition in the transmitter. This calculation is defined by the following tables:

For example, the branch metric upper_branch for state 12 is the sum of the input registers INP8 and INP0. The following symmetries apply:

upper_branch (s) = -upper_branch (s + 8)
lower_branch (s) = -lower_branch (s + 8).

In Kanaldekodiermodus, which will be considered here at the example of 16-state, and the data rate 1/2, serve as a transition values for each trellis step two distance values which were calculated keitswerten from the main processor 10 on the basis of Bitwahrscheinlich. The bit probability values in turn result from the output values of the equalization method.

The main processor 10 writes the two distance values in the input registers INP0 and INP1 in each trellis step. Additional input registers for storing setpoints are not required for channel decoding. From the two input values, the coprocessor 12 calculates an upper and a lower branch metric for each state in accordance with the following tables:

For this calculation, the symmetries listed above apply and in addition:

upper_branch (s) = -lower_branch (s).  

Similarly, with 64 states, 128 branch metrics become calculated. If the data rate is 1/3 or 1/6, four input values are required which are in the input register INP0 until INP3 are written.

The path selector 22 includes the hardware circuitry necessary to perform the calculations shown in FIG. 3 in the form of a flow chart for each trellis step. In these calculations, the upper and lower branch metrics are processed by the metric calculator 20 to calculate new state metrics. The state metrics are compared and the most likely path for each state is selected. The path selection device 22 firstly outputs the calculated transitions and secondly the maximum probabilities for the upper and lower branches by writing these output values into the transition registers or into the registers for storing the maximum metric values. The main processor 12 can access these registers.

In the exemplary embodiment described here, the path selection device 22 is designed as a hard-wired hardware circuit. The loop shown in the flowchart of FIG. 3 is implemented as a counter, for example, and corresponding arithmetic units are provided for the arithmetic operations.

The old and new state metrics are stored in the four memory banks 26 a to 26 d of the memory device. The memory banks 26 a and 26 c contain only the metrics of even states, and the memory banks 26 b and 26 d contain the metrics of odd states. In each trellis step, the old metrics are read and new metrics are written. Since the memory bank pairs 26 a, 26 b on the one hand and 26c, 26d on the other hand alternate with regard to their roles as storers for old and new metrics. If, for example, old metrics are read from the memory bank pair 26 a, 26 b in a trellis step and new metrics are written into the memory bank pair 26 c, 26 d, then the roles in the following trellis step are reversed and the old metrics are from the memory bank pair 26 c, 26 d read and written as processed new metrics in the memory bank pair 26 a, 26 b ge. Since the memory content does not change between successive trellis steps, this method makes the new metrics of each trellis step available as old metrics in the next trellis step.

The assignment of the memory bank pairs 26 a, 26 b and 26 c, 26 d as memory for old or new metrics is determined by a control signal VTCEVEN, which is generated by the path selection device 22 and whose value is available in the control register for reading by the main processor 12 . In each trellis step, this control signal changes its signal state (see FIG. 5c), as a result of which the roles of the memory bank pairs 26 a, 26 b and 2 Ec, 26 d are interchanged. This ensures that the path selection device 22 always accesses the correct memory bank pairs in order to read out the old metric values and to write in the new metric values.

The sequence for a trellis step shown in FIG. 3 begins in block 28 with the initialization of the maximum metric values MAXU and MAXL and the state counter. In block 30 , which consists of two memory accesses 32 and 34 executed in parallel, the metric upper_metric for the most likely path extended by the new upper branch and the metric lower_metric for the most probable path extended by the new lower branch are calculated. Due to the structure of the transitions in the trellis, the two memory accesses 32 and 34 always take place on the old metrics of an even and an odd state, so that always two parallel memory banks (depending on the state of the control signal VTCEVEN either on the memory banks 26th a, 26 b or the memory banks 26 c, 26 d) can be accessed.

In block 36 , the calculated metrics upper_metric and lower_metric are first compared (comparison 38). The larger metric that corresponds to the more likely extension of the previous path is selected and saved as a new metric for the current state (memory access 40 or 44 ). Furthermore, the transition bit TRAN is set depending on the transition selected for the path extension (assignments 42 and 46 ). The new metric new_metric is stored in the memory access 40 or 44 , depending on the state of the control signal VTCEVEN, in the memory bank pair 26 a, 26 b or 26 c, 26 d provided for the new metric.

In order to determine the greatest probability of a path extension with an upper or a lower transition in an entire trellis step for the equalization mode, the calculated lower metric lower_metric is compared in query 48 with the maximum metric value MAXL of the states of the trellis step considered previously. If a greater probability has been determined for the current state, the maximum metric value MAXL is increased accordingly by the assignment 50 . Analogously, the maximum formation for the upper transition takes place with the upper metric upper_metric and the maximum metric value MAXU in query 52 and assignment 54 . The maximum metric values MAXU and MAXL as output values of the coprocessor 10 are only required in the equalization mode; in the exemplary embodiment described here, however, they are calculated in all modes.

Finally, the status counter is incremented (step 56 ) and the method is continued with the next status, unless the maximum status number STATE has been reached (query 58 ). The STATE value is, depending on the control value VTCSTATE, either 63 (with 64 states) or 15 (with 16 states).

The sequence shown in Fig. 3 in sequential form can be implemented in hardware in any parallelized or interlocking form. In the exemplary embodiment described here, a three-stage pipeline structure is provided. In the first stage, the branch metrics and the old state metrics are read. In the second stage, the addition, comparison and selection take place, and in the third stage the calculation results are output. Since the reading memory accesses 32 and 34 take place in a pipeline stage other than the writing memory access 40 or 44 , these two access types are also carried out in parallel. Overall, therefore (with the pipeline filled) three memory accesses take place in each clock cycle, the read memory accesses 32 and 34 relating to an already started, later run of the loop shown in FIG. 3 and the write memory access 40 and 44 to one not yet complete completed, previous loop pass. Because of this pipeline processing, only 20 clock cycles are required to calculate a trellis step with 16 states and only 68 clock cycles to calculate a trellis step with 64 states.

In the exemplary embodiment described, the internal registers for the metrics upper_metric and lower_metric are monitored with regard to their value range. An overflow of these registers is recognized and displayed as error bit VTCOVERF in the control register. The steps required for this are not shown in FIG. 3 for reasons of clarity.

The state diagram of FIG. 4 represents a very abstract view of the sequence shown in FIG. 3 and of the calculation of the branch metrics by the metric calculation device 20. After a transition 60 , which is triggered by a suitable reset signal from the main processor 12 , there is the coprocessor 10 in an idle state IDLE. The processing is initiated by the main processor 12 by setting a control bit VCTACT in the control register of the coprocessor 10 (transition 62 ). The coprocessor 10 is thereby initialized in accordance with block 28 of FIG. 3 and put into an ACTIVE working state.

In the working state ACTIVE each loop 3 corresponds to running of Fig. A transition 64 in Fig. 4. The respective refreshes elle state is counted clock-controlled, are processed until all competent de. If this is the case (query 58 in FIG. 3), the coprocessor 10 resets the control bit VCTACT in order to indicate the end of the processing of the trellis step. The coprocessor 10 changes to the idle state IDLE (transition 66 ). In order to trigger the processing of the next trellis step by the coprocessor 10 , the main processor 12 again sets the control bit VCTACT in the control register of the coprocessor 10 . This in turn results in the transition 62 to the ACTIVE working state. During this transition, the control signal VTCEVEN is inverted by the coprocessor 10 in order to switch the memory bank pairs.

In general, the main processor 12 can read and write all the registers of the coprocessor 10 and all memory cells of the storage device 24 as long as the coprocessor 10 is in the idle state IDLE. When the coprocessor 10 is active (working state ACTIVE), the main processor 12 can write the first four input registers INP0 to INP3 and read the four transition registers and the two registers for storing the maximum metric values MAXU and MAXL without disturbing the ongoing calculation process. This allows inputs for the next trellis step and outputs of the last trellis step to be read in and out during a running calculation of the coprocessor 10 . This functionality is achieved by a suitable intermediate storage of the values required for the calculation of the current trellis step as well as the calculation results of the current trellis step.

FIGS. 5a to Fig. 5c illustrate the interaction between the main processor 12 and the coprocessor 10 degrees. The beginning of the processing of a data block is shown here, namely in FIG. 5a the value profile of the control bit VCTACT, in FIG. 5b the idle or working state of the coprocessor 10 and in FIG. 5c the value profile of the control signal VCTEVEN.

Before time t ₁ , main processor 12 prepares the processing of a data block. It first initializes the memory device 24 with suitable initial status metrics and then writes the desired configuration data into the status register of the coprocessor 10 . If the equalization mode of the coprocessor 10 was selected, the main processor 12 also writes eight pre-calculated setpoints in the input registers INP1 to INP8.

To process the first bit of the data block, the main processor 12 now loads corresponding values into the input register INP0 and, depending on the operating mode, possibly into further input registers. The coprocessor 10 is now started by setting the control bit VCTACT at the time t ₁ and independently calculates a trellis step. This calculation is completed at time t ₂ . In the interval between the times t ₁ and t ₂ , the main processor 10 already writes the input values required for the next trellis step into the input register INP0 and, if appropriate, into the further input registers INP1 to INP3.

The completion of the calculations is signaled to the main processor 12 at time t ₂ in that the coprocessor 10 resets the control bit VCTACT. Since the input values required to calculate the second trellis step already exist in the input registers of the coprocessor 10 , the coprocessor 10 can be started again immediately by setting the control bit VCTACT (time t ₃ ).

During the calculation of the second trellis step s in the interval between the times t ₃ and t ₄ , the main processor 12 first reads the required output values from the four transition registers and the two registers for storing the maximum metric values MAXU and MAXL. The values of the first trellis step stored in these output registers are not overwritten during the ongoing calculation of the second step. The main processor 12 can now postprocess the read values, for example to determine a value for the data bit likely received and a reliability indication in the equalization from the maximum metric values MAXU and MAXL by subtraction and scaling. In channel decoding mode, the processor stores the transition bits in order to be able to trace the most likely path in the trelis after the processing of the data block has been completed.

Even before the time t ₄ , ie during the calculation of the second trellis step, the main processor 12 , as already described, writes the input data required for the third trellis step into the input register of the coprocessor 10 . This means that no communication between the main processor 12 and the coprocessor 10 is required during the rest phase after the time t ₄ , so that this rest phase (time interval t ₄ to t ₅ ) can be kept very short. The coprocessor 10 is therefore kept almost constantly in the ACTIVE working state during the described sequence and is therefore used very well. For test or diagnostic purposes, however, the content of the memory device 24 can be read out by the main processor 12 during the idle phases of the coprocessor 10 (idle state IDLE).

Reference list

10th

Coprocessor

12th

Main processor

14

bus

16

Storage device

18th

Input / output device

20th

Metric calculator

22

Path selector

24th

Storage device

26

a memory bank

26

b memory bank

26

c memory bank

26

d memory bank

28-58

Various calculation steps when processing a trellis step

60-66

Transitions

Claims (15)

1. coprocessor ( 10 ) for providing auxiliary functions for a Viterbi decoding method, with:

• a metric calculation device ( 20 ) which is set up to read in at least one input value (INP) for each individual trellis step and to calculate a plurality of branch metrics (upper_branch, lower_branch) depending on the at least one input value (INP),
• - A storage device ( 24 ) for storing status metrics (old_metric, new_metric), and
• - a path selecting means (22) which is adapted (upper_branch, lower_branch) for each trellis step as a function of the calculated by the metric calculating means (20) branch metrics and the data stored in the storage device state metrics (old_metric) new state metrics (new_metric) and from to calculate initial values (TRAN, MAXU, MAXL), to write the new state metrics (new_metric) into the memory device ( 24 ) and to output the output values (TRAN, MAXU, MAXL) or to make them available for output.

2. Coprocessor according to claim 1, characterized in that the coprocessor ( 10 ) independently calculates the output values (TRAN, MAXU, MAXL) from the at least one input value (INP). 3. coprocessor according to claim 1 or claim 2, characterized, that the output values transition values (TRAN) and / or Maxi metric values (MAXU, MAXL) are. 4. Coprocessor according to one of claims 1 to 3, characterized in that the coprocessor ( 10 ) is set up to work either in an equalization mode or in a channel decoding mode. 5. coprocessor according to claim 4, characterized in that the coprocessor ( 10 ) is set up to store setpoints (INP) and to use these setpoints (INP) in the equalization mode when calculating the branch metrics (upper_branch, lower_branch) of each trellis step. 6. Coprocessor according to one of claims 1 to 5, characterized in that the memory device ( 24 ) is divided into a plurality of memory banks ( 26 a- 26 d), and that the state metrics (old_metric, new_metric) stored in the memory device ( 24 ) are distributed over at least two of these memory banks ( 26 a- 26 d). 7. coprocessor according to claim 6, characterized in that the path selection device ( 22 ) is set up to access at least two memory banks ( 26 a- 26 d) of the memory device ( 24 ) in parallel. 8. coprocessor according to one of claims 1 to 7, characterized in that the coprocessor ( 10 ) is designed as a hard-wired hardware circuit. 9. Coprocessor according to one of claims 1 to 8, characterized in that the coprocessor ( 10 ) is set up to read the at least one input value (INP) from a main processor ( 12 ) and the output values (TRAN, MAXU, MAXL) to output to the main processor ( 12 ) or to provide for output to the main processor ( 12 ). 10. Coprocessor according to claim 9, characterized in that the coprocessor ( 10 ) has input registers for the input values (INP) and output registers for the output values (TRAN, MAXU, MAXL), and that these registers during the processing of a trellis step by the Main processor ( 12 ) are at least partially readable and / or writable. 11. Signal processing device with a main processor ( 12 ) and a coprocessor ( 10 ) connected thereto, characterized in that the coprocessor ( 10 ) has the features of claim 9 or 10. 12. Signal processing device according to claim 11, characterized in that the main processor ( 12 ) is a programmable, digital signal processor. 13. Signal processing device according to claim 11 or 12, characterized in that the coprocessor ( 10 ) is set up to calculate a single NEN trellis step parallel to in the main processor ( 12 ) from running processes. 14. Signal processing device according to claim 13, characterized in that the main processor ( 12 ) is set up to transmit the at least one input value (INP) to the coprocessor ( 10 ) before each trellis step, then to initiate the calculation of the trelis step in the coprocessor ( 10 ) , and finally read the output values (TRAN, MAXU, MAXL) at least partially from the coprocessor ( 10 ). 15. Signal processing device according to claim 14, characterized in that the transmission of the at least one input value (INP) to the coprocessor ( 10 ) takes place during the calculation of the previous trellis step by the coprocessor ( 10 ), and that the at least partial reading of the output values (TRAN , MAXU, MAXL) from the coprocessor ( 10 ) during the calculation of the subsequent trellis step by the coprocessor ( 10 ).