DE19741483C2 - Superconducting single-flux quantum interface circuit for converting a "return-to-zero" signal representation into a "non-return-to-zero" signal representation - Google Patents

Abstract

Superconducting single-flux quantum circuits generate digital output voltages that operate in return-to-zero (RZ) mode, that is, return to voltage zero between two consecutive logic levels "1". The disclosed interface circuit with superconducting components serves to operate these circuits together with semiconductor circuits, which are usually operated in non-return-to-zero mode. DOLLAR A An embodiment consisting of two hybrid circuits, a D flip-flop, an XOR gate and an RS flip-flop can be realized with only about 20 Josephson contacts. This interface circuit allows operation at high speed and low power dissipation, e.g. B. in niobium technology at 4.2 K.

Description

To determine the reliability of RSFQ circuits, error rate measurements by of special interest. To make a direct comparison of different technologies enable, the same measuring devices should be used. These measuring devices, e.g. B. from Anritsu MD6420A, Tektronix SX4610 or Hewlett Packard 71603B [1], need on their Data inputs Signals in which the amplitude is between two consecutive times "1" does not go back to "0". Such an output signal scheme of those to be examined Switching is called non-return-to-zero (NRZ) mode.

From the publication [3] is a su praleitende RSFQ interface circuit known that an RS flip-flop at the output the interface circuit contains. However, this will be between two at its entrance hit SFQ data pulses always by the clock pulse in its logical "zero state" reset. A conversion of the SFQ data pulses from RZ display to NRZ display is not possible with this interface circuit.

If an RS flip-flop from the RSFQ logic family is used for the detection of SFQ pulses [2] the problem is that if there are several consecutive "1" s at the output, the RS flip-flop must first be reset to "0" before another SFQ pulse is detected can be. The output signal drops briefly to "0" between two "1". This behavior corresponds to a Return-to-Zero (RZ) mode and can be used in the Determination of error rates despite correct functioning should be interpreted as errors and straight at high clock frequencies lead to distortion of the eye diagram [3], so that SFQ- Output circuits are required that work according to the NRZ mode. For the measurement Logical interfaces are required from error rates, which follow an output signal the NRZ mode.

This problem is solved by an inventive Interface circuit with the in claim 1 specified features solved. Advantageous Next educations are specified in the subclaims.  

Show it:

Fig. 1: Block diagram and truth table of the NRZ circuit;

Fig. 2: Electrical equivalent circuit diagram of the NRZ circuit;

Fig. 3: Result of a SPICE simulation of the NRZ circuit;

Fig. 4: Microscopic picture of the realized NRZ circuit.

According to Fig. 2, the interface consists of several modules from the RSFQ family [2]: two hybrid circuits, an XOR gate, a D flip-flop and an RS flip-flop with an input buffer. Such a circuit was developed and designed from optimized RSFQ library modules.

literature

[1] R. Koch, "Digital Superconductor Circuits", dissertation at INFO-Verlag, Karlsruhe, ISBN 3-88190-241-4, 1999.
[2] K. Likharev and V. Semenov - "RSFQ Logic / Memory Family: a New Josephson Junction Technology for Sub-Teraherz Clock Frequency Digital Systems", IEEE Trans. On Appl. Super conductivity, vol. 1, pp. 3-24, Jan. 91.
[3] OA Mukhanov, SV Rylov, DV Gaidarenko, NB Dubash, VV Borzenets, "Josephson Output Interfaces for RSFQ Circuits", IEEE Trans. Appl. Superconductivity, Vol. 7, No. 2, June 1997, pp. From 2826 to 2831.

Claims (8)

1. Superconducting single-flux quantum (SFQ -) - interface circuit for converting a "return-to-zero" (RZ) signal representation into a "non-return-to-zero" signal representation, characterized in that a RS flip-flop at the output of the interface is only switched if a logical value of the SFQ data pulses at the input of the interface changes. 2. SFQ interface circuit according to claim 1, characterized in that the RS- Flip flop is implemented in SFQ logic, has an SFQ / DC converter and not through an external clock is operated. 3. SFQ interface circuit according to claims 1 or 2, characterized in that with the exception of the RS flip-flop at the output all other gates with SFQ clock pulses via a clock line in the opposite direction to the SFQ data pulses on data lines can be controlled. 4. SFQ interface circuits according to one of claims 1 to 3, characterized ge indicates that an XOR (equivalence) gate has an input signal with a um compares a clock delayed input signal and thus a change in logical value at the input. 5. SFQ interface circuit according to one of claims 1 to 4, characterized characterized in that the input signal delayed by one clock, the RS flip-flop on Output sets. 6. SFQ interface circuit according to claims 4 or 5, characterized in that the output signal of the XOR gate, that is when the logic value changes Interface input that resets the RS flip-flop at the output. 7. SFQ interface circuit according to one of claims 4 to 6, characterized characterized in that the delay of the input signal by one clock over a clocked D flip-flop is formed. 8. SFQ interface circuit according to claim 7, characterized in that the Input signal and the output signal of the D flip-flop each via a hybrid circuit be branched.