DE19735349B4 - Vektorprozessor und Verfahren zu dessen Betrieb - Google Patents

Vektorprozessor und Verfahren zu dessen Betrieb Download PDF

Info

Publication number
DE19735349B4
DE19735349B4 DE19735349A DE19735349A DE19735349B4 DE 19735349 B4 DE19735349 B4 DE 19735349B4 DE 19735349 A DE19735349 A DE 19735349A DE 19735349 A DE19735349 A DE 19735349A DE 19735349 B4 DE19735349 B4 DE 19735349B4
Authority
DE
Germany
Prior art keywords
register
vector
scalar
registers
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19735349A
Other languages
German (de)
English (en)
Other versions
DE19735349A1 (de
Inventor
Moataz A. Santa Clara Mohamed
Heon Chul Cupertino Park
Le Trong Monte Sereno Nguyen
Roney Sau Don Sunnyvale Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE19735349A1 publication Critical patent/DE19735349A1/de
Application granted granted Critical
Publication of DE19735349B4 publication Critical patent/DE19735349B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE19735349A 1996-08-19 1997-08-14 Vektorprozessor und Verfahren zu dessen Betrieb Expired - Fee Related DE19735349B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69958596A 1996-08-19 1996-08-19
US08/699,585 1996-08-19

Publications (2)

Publication Number Publication Date
DE19735349A1 DE19735349A1 (de) 1998-04-02
DE19735349B4 true DE19735349B4 (de) 2006-12-14

Family

ID=24809983

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19735349A Expired - Fee Related DE19735349B4 (de) 1996-08-19 1997-08-14 Vektorprozessor und Verfahren zu dessen Betrieb

Country Status (6)

Country Link
JP (1) JPH10143494A (zh)
KR (1) KR100267089B1 (zh)
CN (1) CN1152300C (zh)
DE (1) DE19735349B4 (zh)
FR (1) FR2752629B1 (zh)
TW (1) TW346595B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103002276B (zh) * 2011-03-31 2017-10-03 Vixs系统公司 多格式视频解码器及解码方法
US20140082333A1 (en) * 2011-12-22 2014-03-20 Elmoustapha Ould-Ahmed-Vall Systems, apparatuses, and methods for performing an absolute difference calculation between corresponding packed data elements of two vector registers
CN104011664B (zh) * 2011-12-23 2016-12-28 英特尔公司 使用三个标量项的超级乘加(超级madd)指令
CN102750133B (zh) * 2012-06-20 2014-07-30 中国电子科技集团公司第五十八研究所 支持simd的32位三发射的数字信号处理器
KR102179385B1 (ko) 2013-11-29 2020-11-16 삼성전자주식회사 명령어를 실행하는 방법 및 프로세서, 명령어를 부호화하는 방법 및 장치 및 기록매체
GB2543303B (en) * 2015-10-14 2017-12-27 Advanced Risc Mach Ltd Vector data transfer instruction
US10108581B1 (en) * 2017-04-03 2018-10-23 Google Llc Vector reduction processor
US11893393B2 (en) 2017-07-24 2024-02-06 Tesla, Inc. Computational array microprocessor system with hardware arbiter managing memory requests
US11409692B2 (en) * 2017-07-24 2022-08-09 Tesla, Inc. Vector computational unit
CN114116513B (zh) * 2021-12-03 2022-07-29 中国人民解放军战略支援部队信息工程大学 多指令集架构向risc-v指令集架构的寄存器映射方法及装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0517013A2 (en) * 1991-05-14 1992-12-09 Nec Corporation Information processing system capable of operating a plurality of vector pipeline sets in two different modes
EP0646877A2 (en) * 1993-10-05 1995-04-05 Fujitsu Limited Computer system and method for processing vector data

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5081573A (en) * 1984-12-03 1992-01-14 Floating Point Systems, Inc. Parallel processing system
US5001662A (en) * 1989-04-28 1991-03-19 Apple Computer, Inc. Method and apparatus for multi-gauge computation
EP0681236B1 (en) * 1994-05-05 2000-11-22 Conexant Systems, Inc. Space vector data path

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0517013A2 (en) * 1991-05-14 1992-12-09 Nec Corporation Information processing system capable of operating a plurality of vector pipeline sets in two different modes
EP0646877A2 (en) * 1993-10-05 1995-04-05 Fujitsu Limited Computer system and method for processing vector data

Also Published As

Publication number Publication date
KR100267089B1 (ko) 2000-11-01
FR2752629B1 (fr) 2005-08-26
KR19980018065A (ko) 1998-06-05
JPH10143494A (ja) 1998-05-29
FR2752629A1 (fr) 1998-02-27
CN1188275A (zh) 1998-07-22
CN1152300C (zh) 2004-06-02
DE19735349A1 (de) 1998-04-02
TW346595B (en) 1998-12-01

Similar Documents

Publication Publication Date Title
DE19735350B4 (de) Vektorprozessor zum Ausführen paralleler Operationen und Verfahren hierfür
DE19735348B4 (de) Vektorprozessor zur Einzelbefehl-Mehrdaten-Verarbeitung unter Verwendung von mehreren Bänken von Vektorregistern und zugehöriges Verfahren zum Betreiben desselben
DE102018005181B4 (de) Prozessor für einen konfigurierbaren, räumlichen beschleuniger mit leistungs-, richtigkeits- und energiereduktionsmerkmalen
DE69625256T2 (de) Mikrorechner
DE69503046T2 (de) Mehrfachbefehlssatzabbildung
DE69233412T2 (de) Vorrichtung und Rechnerprogrammprodukt zur Ausführung von Verzweigungsbefehlen
DE69709078T2 (de) Verwaltungssystem zur datenverarbeitung
DE69525097T2 (de) Prozessorarchitektur für gemischte Funktionseinheiten
DE69530520T2 (de) Computerprogrammprodukt zur Verwendung von Mehrfachbefehlssätzen
DE102018005216A1 (de) Prozessoren, Verfahren und Systeme für einen konfigurierbaren, räumlichen Beschleuniger mit Transaktions- und Wiederholungsmerkmalen
DE69032635T2 (de) Verfahren und Vorrichtung zur Erkennung von Betriebsmittelkonflikten in einer Pipeline-Verarbeitungseinheit
DE69707486T2 (de) Architektur eines integrierten bausteins zur digitalen signalverarbeitung
DE69801673T2 (de) Co-prozessordatenzugangskontrolle
DE102018005172A1 (de) Prozessoren, verfahren und systeme mit einem konfigurierbaren räumlichen beschleuniger
DE102018006889A1 (de) Prozessoren und Verfahren für bevorzugte Auslegung in einem räumlichen Array
DE102018130441A1 (de) Einrichtung, Verfahren und Systeme mit konfigurierbarem räumlichem Beschleuniger
DE102018006735A1 (de) Prozessoren und Verfahren für konfigurierbares Clock-Gating in einem räumlichen Array
DE102018006791A1 (de) Prozessoren, Verfahren und Systeme mit einem konfigurierbaren räumlichen Beschleuniger mit einem Sequenzer-Datenflussoperator
DE102018125232A1 (de) Einrichtung und Verfahren für komplexe Multiplikation und Akkumulation
DE68927783T2 (de) Mikroprozessor mit äusserem steuerungsspeicher
DE112014006508T5 (de) Prozessoren, Verfahren, Systeme und Anweisungen für Fliesskommaaddition mit drei Quellenoperanden
DE202008017916U1 (de) Virtuelle Architektur und virtueller Befehlssatz für die Berechnung paralleler Befehlsfolgen
DE112012003864T5 (de) Mehrfach adressierbare Registerdateien und dazugehörige Formatumwandlungen
DE2949375A1 (de) Gleitkommaprozessor
DE102018125805A1 (de) Systeme, verfahren, und vorrichtungen für skalarproduktoperationen

Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee