DE19731944A1 - Charge-carrier lifetimes determining circuit for semiconductor wafer - Google Patents

Abstract

The test device comprises a semiconductor substrate (W) with two upper layers for determining charge carrier lifetime within the substrate. Within the substrate are an N-type conducting layer (Ba) with relatively low impurities and a second N-type conducting layer (Bu) with a higher impurity level, together forming the upper, N-type conducting layer. A third, P-type, conducting layer forms the second main layer. An electrode region (C) has a relatively high impurity level is placed in the top surface of the first layer (Ba). The test element group has a cathode region and function region and the areas of the cathode region to the function region are in ratio between 1/1750000 and 1/4500.

Description

The invention relates to a test element group for Lifetime evaluation of load carriers in one Semiconductor substrate.

Lifetime values of charge carriers such as electrons or holes form an important criterion regarding the different Characteristic curves and properties of semiconductor devices, especially of power semiconductors. As is known for a lifetime evaluation of separate semiconductor wafers besides the semiconductor wafers manufactured for production, with which a lifetime evaluation is carried out.

Fig. 29 shows a plan view of a semiconductor wafer W with test element group (TEG test element groups) according to the prior art. A large number of test element groups TEG formed on the semiconductor wafer W are shown in FIG. 29.

FIG. 30 shows a sectional view of the test element group TEG shown in FIG. 29. The test element groups correspond to diodes consisting of a cathode region C with a doping N⁺, a base layer Ba with N⁻ and an anode region A with P⁺, which are each arranged one above the other.

In the known method, the charge carrier lifetime value is evaluated by observing the change in the current flowing in a diode according to FIG. 30 in chronological order. Fig. 31 shows schematically a circuit arrangement according to the known evaluation method. A test element group TEG is shown as a diode and a load resistor is connected in series with a pulse power source PS, which provide a pulsating wave (pulsating voltage). A measurement of differences in the voltage between the two terminals of the load resistor using an oscilloscope Os gives the current flowing in the diode, as a result of which a change in the characteristic curve of the diode can be observed in chronological order, which relates to the charge carrier lifetime value.

FIG. 32 shows a circuit arrangement, and in particular details of the construction of the circuit shown in FIG. 31. Output signals of a function generator FG and the positive and negative connections of the power supplies G1 and G2 are fed to a pulse generation circuit PGC via coaxial cables. The pulse generation circuit PGC supplies an infinitely small signal via the coax cables for amplification to a sufficient amplitude, which is required as a power source, and outputs this at the output connections. A chip (not shown) attached to a holder H and a resistor R are attached in series with the positive and negative terminals of the pulse generation circuit PGC. A test needle PN is connected to both terminals of the resistor R for detecting the voltage, which is then fed to the oscilloscope Os for analysis by means of a computer CM.

Fig. 33 shows a timing signal of a current flowing in the test element group in the form of a diode current, as it is brought to the display by means of the oscilloscope Os. The vertical and horizontal axes show the current value and the time. When a predetermined value of a pulse voltage changes from a forward value to a backward value at a time Ta in the circuit shown in Fig. 31, the current decreases to the smallest negative value at a time Tb and then gradually increases to zero . If 10% of the current value is obtained at a time Tc when the smallest negative value is 100%, the time Tc-Tb required for a 90% decrease is determined as the blocking delay time (recovery time) Trr.

The blocking delay time Trr is determined by the lifetime value of the Charge carriers affected. So the lifetime value is the Test element groups by determining the blocking delay time Trr derivable. Deriving the lifetime value requires but not only the measurement of the blocking delay time Trr, but also a simulation of the same. A comparison between simulation results and measured values leads to a derivation of the lifetime value of the test element groups.

A simulation of those in the electrodes of the test element groups prevailing current density is determined by means of the service life values τn and τp of the respective electrons and holes as parameters carried out. A lock delay time Trr (Sim) is called Obtain the result of the simulation, the reference symbol (Sim) indicates that the value is the result of a simulation acts. To simplify the simulation, it is assumed that the lifetime values τn and τp are the same.

Fig. 34 shows a schematic representation of a method for obtaining the lifetime value τ of real test element groups TEG. According to the representation in this figure, in which the vertical and horizontal axes denote the blocking delay time Trr (Sim) from the simulation and the service life value τ, the simulation results are plotted to form a characteristic curve L of a specific current density. Here, the blocking delay time Trr obtained by an actual measurement is obtained at the same current density as if the characteristic curve L were obtained. The point on the characteristic curve L at the blocking delay time Trr results in a service life value (indicated by an arrow in FIG. 34), which indicates the service life value τ of the semiconductor wafer shown in FIG. 29.

A similar measurement and simulation according to the above Description with a different current density can Reliability of the lifetime value τ obtained Improve semiconductor wafer W.

Because the evaluation of the service life values is carried out according to the formation of test element groups in one Evaluation slice (semiconductor slice for evaluation), which according to the above description regardless of the actual Product disc is, the lifetime value of the load carrier one of the chips actually used for production be evaluated. Therefore, the evaluation of the products is not directly, but only indirectly.

Furthermore, the known method shown in FIG. 32 requires a function generator FG, positive and negative power supply sources G1 and G2, the pulse generation circuit PGC, the holding device H, the resistor R, the test needle PN and the oscilloscope Os, so that the method is very complex overall .

The invention is therefore based on the object Test element group for a lifetime evaluation of To design load carriers of the type mentioned at the outset in such a way that a simple determination of the exact Lifetime value of the load carrier is guaranteed.

According to the invention, this object is achieved by means of a Test pattern area for life evaluation, which on a Semiconductor substrate with a first and a second main surface is designed to evaluate the charge carrier life in the semiconductor substrate, the semiconductor substrate comprising: a first line layer of a first line type with a relative low impurity concentration, the first  Line layer forms the first main surface, a second Line layer of the first line type with a relatively large one Impurity concentration, and a third line layer one second line type, different from the first line type , and forms the second major surface, where a Electrode area with a relatively large concentration of impurities selectively in a surface area of the first conduction layer is formed on one side of the first main surface.

The object is further achieved according to the invention by a Evaluation pattern area for life evaluation, based on a Semiconductor substrate with a first and a second main surface is formed, for evaluating the charge carrier life in the Semiconductor substrate, wherein a first conduction layer of a first Line type and a second line layer of a second Line type that is different from the first line type each form the first and second main surface, and the first conduction layer comprises: an electrode region with relative large impurity concentration in a surface area is formed on one side of the first main surface, and a connection area with a relatively low Impurity concentration to connect the electrode area and the second conduction layer, an area ratio between the electrode area on the first main surface and an area on the second main surface called Serves electrode area is determined such that the Stress values when simulating the evaluation of the Carrier life can be isolated from each other by Obtaining voltage values at a reference current value for the respective large number of discrete values to indicate the Carrier life as a parameter.  

According to the invention, the electrode region is preferably at one Break line (incised line) of the semiconductor substrate arranged.

Furthermore, the electrode area is preferably on a chip formed for an evaluation of the semiconductor substrate is provided.

Furthermore, the electrode area is preferably in a chip arranged, which is intended for use as a product.

By means of the construction of the test element group for a lifetime evaluation of the load carriers in one Semiconductor substrate, it is possible to directly evaluate the To carry out the carrier lifetime of the semiconductor substrate, wherein the semiconductor substrate itself as a semiconductor device integrated elements. Compared to building others Semiconductor substrates that are provided for an evaluation, the construction according to the present invention enables Carrying out the evaluation of the carrier lifetime of the Semiconductor substrate with great accuracy, the Reliability of the evaluation is improved.

According to the present invention, the location of the measured Values of the test element group in a simple way by comparison with the values obtained from the simulation. This improves the accuracy and also the reliability the evaluation.

Furthermore, the evaluation of the Lifetime with electrode areas with different areas be performed. This further improves reliability the evaluation.  

According to the further structure of the present invention, there is none Electrode area arranged in the chip, which as a product is provided and actually as a semiconductor device on the Semiconductor substrate is used. Therefore, the influence on the chip prevented by the formation of additional elements will.

Furthermore, the evaluation of the Chips that are used for evaluation or for use as Product are intended to be carried out, even if that Semiconductor substrate is divided (i.e. scratched and broken). There is therefore no restriction to the time before Division of the semiconductor substrate, since the evaluation into one suitable time can be carried out. In particular, can in the further embodiment of the invention, the evaluation be performed after the chip is used as a product was, so that the structure of the invention thus the requirements fulfilled for an evaluation in chronological order (service life).

It is therefore within the scope of the present invention by means of Test element groups for a lifetime evaluation possible, one direct evaluation of the carrier lifetime with regard to perform the product intended semiconductor wafer. Further assign the test element groups for a lifetime evaluation such a structure that improved accuracy the evaluation in relation to a simplification procedure the lifetime evaluation is possible.

Advantageous refinements of the Invention marked.

The invention is described below using exemplary embodiments Reference to the drawings explained in more detail. Show it:  

Fig. 1 is a plan view of a structure of a semiconductor wafer with test element groups according to a first embodiment,

Fig. 2 is a sectional view illustrating the structure of a test element group according to the first embodiment,

Fig. 3 is a sectional view illustrating the structure of a semiconductor wafer having a test element group according to the first embodiment,

Fig. 4 is a graph showing a profile of the impurity concentration of the test element group shown in Fig. 3,

Fig. 5 is a circuit diagram showing a configuration of a measurement system for the characteristics of the test element group according to the first embodiment,

Fig. 6 is a circuit diagram showing the equipment of the assembly shown in Fig. 5,

Fig. 7 is a perspective view showing the construction of the holding device shown in Fig. 6,

Fig. 8 is a flowchart for illustrating the method for obtaining the characteristics of the test element group according to the first embodiment,

Fig. 9 is a graph showing a profile of the IV characteristic,

Fig. 10 is a flow chart showing a simulation process according to the first embodiment,

Fig. 11 is a perspective view showing the sectional structure of a modeled test element group for simulations,

Fig. 12 is a plan view illustrating the correlation between a real test element group, and the modeled test element group according to Fig. 11,

Fig. 13 is a graph showing respective results obtained by means of an actual measurement and simulation,

Fig. 14 is a plan view showing the arrangement of the chips on the semiconductor wafer,

Fig. 15 is a plan view showing the construction of the test element groups which are arranged on a scribe line (target Burch edge) according to a second embodiment,

Fig. 16 is a plan view showing the construction in the space reserved for testing purposes chip formed test element group according to a third embodiment,

Fig. 17 is a plan view for illustrating the structure of the formed product in the intended for purposes chip test element groups according to a fourth embodiment,

Fig. 18 is a plan view showing the structure of a plurality of test element groups, which are formed according to a fifth embodiment taken along the scribed line,

Fig. 19 is a sectional view illustrating the structure taken along a line XIX-XIX of FIG. 18,

Fig. 20 is a graph showing an analysis with respect to the test element groups according to the fifth embodiment,

Fig. 21 is a graph for illustrating results obtained by the known method by tests of the test element groups according to the invention,

Fig. 22 is a graph showing the analysis of the 21 results illustrated in FIG.

Fig. 23 is a plan view for illustrating the structure with a plurality of test element groups, which are formed both in the for a test or use as a product intended chip according to the fifth embodiment,

Fig. 24 is a flowchart for illustrating a procedure for obtaining characteristics of the plurality of test element groups according to the fifth embodiment,

Fig. 25 is a sectional view illustrating the structure according to a sixth embodiment,

Fig. 26 is a perspective view showing the construction of a test element group according to the sixth embodiment,

Fig. 27 is a sectional view illustrating the structure according to the sixth embodiment,

Fig. 28 is a perspective view illustrating the construction according to the sixth embodiment,

Fig. 29 is a plan view illustrating an arrangement of a known test element group for lifetime evaluation,

Fig. 30 is a sectional view showing a structure of a known test element group for lifetime evaluation,

Fig. 31 is a circuit diagram showing the circuit structure for the known evaluation method, which is used in the known test element group for a life evaluation,

Fig. 32 is a schematic diagram showing the circuit construction of devices shown in Fig. 31,

Fig. 33 is a signal timing for illustrating the reverse recovery time trr and

Fig. 34 is a schematic diagram to illustrate the known method of the lifetime evaluation.

First embodiment

The present exemplary embodiment relates to test element groups for lifetime evaluation, where a direct evaluation of the Load carrier lifespan for one product use  provided semiconductor wafer is possible. Here, the same reference numerals and symbols to designate the same or similar components as in the prior art used.

Fig. 1 shows in plan view the structure of an intended for use as a product wafer W with corresponding test element groups TEG. The test element groups are arranged in the form of squares in the plane shown in FIG. 1. The semiconductor wafer W comprises the bipolar IG transistors (insulated gate bipolar transistor IGBT) as integrated elements, not shown.

FIG. 2 shows the structure of the test element group shown in FIG. 1 in a sectional view. The test element group has a layer structure and corresponds to a diode. Furthermore, a cathode region C with the doping N⁺ is partially formed in the surface region of the base region Ba.

Fig. 3 shows a sectional view of the structure of the semiconductor wafer W. The semiconductor wafer W includes an area with IGBT elements and in the vicinity of these IGBT elements corresponding test element groups. A cathode electrode is formed in the cathode area C of the test element group. A collector electrode of the IGBT elements is formed on the lower surface of the semiconductor wafer W and serves as an anode electrode of the test element group. Referring to FIG. 3, the test element group shown in Fig. 2 is formed simultaneously, when the IGBT elements are formed in the semiconductor wafer W.

FIG. 4 shows a schematic representation of the impurity concentration in the test element group with respect to the depth according to the arrow shown in FIG. 3. The vertical and horizontal axes denote the impurity concentration C (imp) and the depth D. As a profile of the impurity concentration C (imp) of the test element group in this figure, a solid line corresponds to the case that the test element group has a buffer area Bu according to FIG. 3, and a broken line serving as a reference line indicates the case that the test element group has no buffer area.

According to FIG. 4, the profile of the impurity concentration of the test element group shows no buffer area Bu has a symmetrical curve from the cathode region C to the anode region A, the high values on both ends of the cathode and anode region C and A and low values in an intermediate range.

Furthermore, the profile (the profile) of the impurity concentration of the test element group according to FIG. 3 shows an asymmetrical profile due to the presence of the buffer area Bu.

At the end of the description of the structure of the test element group is now a procedure for evaluating the Charge carrier lifespan with the test element groups equipped semiconductor wafer according to the present Described embodiment.

In the evaluation method, ON voltage values obtained by actually measuring a real test element group and those obtained by simulation are compared with each other. The facilities required for the evaluation are first described below. Fig. 5 shows a circuit arrangement of the measuring circuit with respect to the evaluation method according to the present embodiment. FIG. 6 shows a schematic illustration of the devices for forming the measuring circuit shown in FIG. 5.

In FIG. 5, a voltage source 10, a current measuring device and the test element group having a diode structure are connected in series to each other. A Signalverlaufsaufnehmer 20 of FIG. 6 represents a desired voltage ready and records the current to, and thus serves as a voltage source 10 and a current meter as shown in Fig. 5. At a holding means H is equipped with the test element groups chip mounted.

Fig. 7 shows a perspective view of the details of the structure of the holding device H with the chip attached to it. The holding device H comprises output electrodes 30 and 40 , which are connected to the anode and the cathode of the test element group, respectively. The output electrode 30 is connected to the anode electrode of the test element group by means of pressure bonding and the output electrode 40 is connected to the cathode electrode of the test element group via a line. The measurement of the I-V characteristic curves (current-voltage characteristic curves) by means of the signal curve pickup 20 according to FIG. 6 is carried out with the test element group attached to the holding device H.

When comparing the structure of the devices according to FIGS. 6 and 32, it can be seen that fewer devices are required for the evaluation method according to the invention according to FIG. 6 than are required according to FIG. 32 in the known evaluation method. This is possible because the known evaluation method processes characteristic curves (dynamic characteristic curves) that change in time sequence, while the present evaluation method processes characteristic curves that have no relation to a change in time (static characteristic curves), as will be described in detail below.

A sequence of the present evaluation method is now described below. FIG. 8 shows a flowchart to illustrate the process for obtaining the ON voltage values Vf through actual measurement of real test element groups.

First, a controller for performing the automatic measurement takes control (step SA0). The control device measures the test element group in order to achieve the profile of an IV characteristic curve according to FIG. 9 (step SA1). In particular, the control device forms a correlation between the voltages applied to the cathode electrode and anode electrode of the test element group and the current flowing between these two electrodes.

According to FIG. 9, the control device receives the IN-voltage values Vf at a reference current value I ₀ on the basis of the profile (characteristic curve) obtained (step SA2). The reference current value I ₀ can be set as desired by a user in the control device. Control ends with a step SA3.

A simulation flow will now be described. Fig. 10 shows a flow chart for illustrating the simulation run. The process begins with step SB0. A user enters predetermined conditions regarding the structure of the test element group such as size, impurity concentration in the simulation device according to step SB1. In step SB2, the user sets a plurality of carrier lifetime values as parameters of the simulation.

In step SB3, the simulation device performs a simulation of the IV characteristics of the test element group. Specifically, an internal state of the test element group is simulated under the predetermined conditions for one of the load carrier life values entered by the user. The simulation leads to courses of IV characteristic curves (profiles), as shown in FIG. 9, which only apply to the lifetime value used. In step SB4, a query is carried out as to whether all simulations for all service life values from step SB2 according to step SB3 have been completed, ie whether the simulation as a whole has been completed or not. If the answer is "YES", the process proceeds to step SB5. If the answer is "NO", then the flow returns to step SB3 for further execution for one of the remaining life values.

In step SB5, ON voltage values Vf (Sim) corresponding to the reference current value I _{0 are obtained} in relation to a multiplicity of courses of the IV characteristic curves, which in turn were obtained for respective service life values in accordance with step SB3. If all ON voltage values Vf (Sim) have been obtained, the process is ended with step SB6.

In the simulation, the modeled test element group with a cylindrical structure according to FIG. 11 is used instead of a real test element group in the form of a square. Fig. 12 shows the relationship between the real test element group, and the modeled test element group in a plan view. As shown in this figure, the outer edge of each component of the modeled test element group is determined by a circle within the corresponding component of the real test element group. The cathode region C of the modeled test element group comprises, for example, an outer edge which is arranged tangentially and internally to the cathode region C of the real test element group. If a component of the real test element group thus comprises a square with a respective side length of 2r, then the corresponding component of the modeled test element group comprises a circle with the radius r.

The modeled test element group with a cylindrical structure is symmetrical in a section parallel to its lower surface with respect to its center. It is therefore possible to decrease one of the coordinates in the simulation, which results in a fast simulation. Furthermore, the respective lifetime values τe and τp of the electrons and holes are assumed to be the same in the simulation, although their real values are different from one another. However, an error due to this assumption is small and therefore negligible. Since the ON voltage values Vf (Sim) are obtained by obtaining courses of the IV characteristic curves, some adjustments are necessary with regard to the difference in the area of each component between the real and the modeled test element group, as shown in FIG. 12. In the simulation the current value is therefore multiplied by 4 / π in step SB5 in FIG. 10 to obtain the ON voltage values Vf (Sim). The value 4 / π is derived from an area ratio 4: π of a square to a circle arranged within the square with the maximum size.

FIG. 13 shows a graphical representation of profiles (profiles) of the IV characteristic curves with respect to the measured values and the simulation results of the test element groups. In the figure, the current value of the simulation is printed out after multiplication by the value 4 / π. White circles denote the measured values of the test element groups and black symbols such as circles and triangles denote the simulation results for the respective service life values. The correlation between these markings and lifetime values is shown in the figure. The real test element group in this figure comprises a cathode region in the form of a square with the respective side length of 100 μm.

It is now assumed that the reference current value I ₀ assumes the value of 6 mA. According to FIG. 13, the intersection points of the courses of the IV characteristic curves and the horizontal axis with the current value of 6 mA identify the ON voltage values Vf and Vf (Sim). The figure shows at this point that the ON voltage values Vf indicated by the white circles (measured values) between the ON voltage values Vf (Sim) with a lifetime value of 20 µs indicated by black squares and those with one Lifetime value of 10 µs, indicated by black circles, both of which were obtained by simulation, are printed out. The charge carrier lifetime value can thus be assigned to a range from 10 to 20 µs within the real test element group.

Another detailed comparison is also possible. There both ON voltage values using the white and black Circles are indicated, each at 1.2 V and close to each other the carrier lifetime value can be within the real test element group can be assumed to be 10 µs.

To clarify the following description, a such a conclusion regarding the lifetime value Compare the ON voltages below as "conclusion" designated.

The reliability of the means given above Process life values obtained can be compared with those values which are obtained using the known method and the test element group according to the invention are obtained, be checked. The result of the comparison is shown below described with reference to a fifth embodiment.  

The test element groups for lifetime evaluation according to present embodiment are in a semiconductor substrate arranged, which is intended for use as a product. This leads to a direct evaluation of the carrier lifetime and to a high reliability of the lifetime evaluation. Furthermore, fewer facilities are required for the Lifetime evaluation according to that described above Method of the first embodiment compared to that known methods.

Although only test element groups in the form of a square in the example described above to clarify the Any shape such as triangles and simulation can be used the like in the test element groups of the present Embodiment can be used.

Second embodiment

The same components and elements corresponding to the The above description will be the same below Symbols and reference numerals designated and not again explained.

Fig. 14 shows a plan view of the semiconductor wafer W with the semiconductor chip CH. In the context of the second exemplary embodiment, the test element groups according to the first exemplary embodiment are formed on a scored line (saw line, predetermined breaking edge) between the chips CH. FIG. 15 shows, in an enlarged plan view, a part of FIG. 14 denoted by a broken line . To simplify the illustration, the reference symbols "CH1" to "CH4" are assigned to the respective chips (starting at the top right) in a clockwise direction.

It should be noted that the charge carrier lifetime values are variable depending on their position on the semiconductor wafer W. Therefore, a large number of test element groups are arranged in many places, so that a conclusion can be drawn on the service life values in a more precise manner. The charge carrier lifetime values with respect to the chips CH1 and CH4 can be determined by means of a test element group arranged on the upper side in FIG. 15. In the same way, a charge element group on the lower side in FIG. 15 can be used to infer the charge carrier life values of the chips CH2 and CH3.

If the semiconductor wafer W shown in FIG. 14 is divided into the corresponding chips CH for use as a product, then no trace of the test element groups formed on the scratched line remains in the chips CH. In the case of integrated circuits, there is therefore no influence of the test element groups on the use of the chips CH. Furthermore, it is not necessary to reserve an area for the test element groups within the chips CH that are intended as a product.

Third embodiment

While according to the second exemplary embodiment the test element groups are arranged along a scratched line, the test element groups can also be arranged in a chip for test purposes. FIG. 16 shows a top view of the semiconductor wafer W with the test element groups formed in the chip for test purposes (test chip), which serves as a replacement for the arrangement shown in FIG. 15.

A chip CH4 as shown in FIG. 16 is not used as a product but as a test chip for the chips CH1 to CH3. With the arrangement of the test element group in the chip CH4 for test purposes, it is possible to draw conclusions about the charge carrier lifespan of the chips CH1 to CH3. In the same way as in the second exemplary embodiment, no traces of the test element groups occur in the chips CH1 to CH3 to be used as a product.

Furthermore, the test element group remains in the chip CH4 after the Chips CH1 to CH3 have been removed. Unlike that Case of the second embodiment, in which the along the scratched line arranged test element groups are lost, in the third exemplary embodiment it is possible to carry out an evaluation of life even after the chips become one Have become a product.

Fourth embodiment

In this exemplary embodiment, the test element groups are arranged in the chip provided as the product. Fig. 17 shows a top view of the structure of such a chip in which the test element groups are arranged within the intended product as chips CH1. The test element group is arranged in an area except for an area RG that serves as one element.

In addition to a direct evaluation of the charge carrier Lifetime values of the CH1 chip used for product use there is another advantage of the present Embodiment in that the evaluation at any time can be done regardless of whether this time before or after dividing the semiconductor wafer. The Test element group can also be in the chips CH2 to CH4 be arranged. The respective procedures for executing the Test element groups according to the second to fourth However, exemplary embodiments are not to be seen exclusively. It For example, it is possible to use the test element groups in both Chip CH4, which is intended for test purposes, as well as along the to arrange the scratched line.  

Fifth embodiment

Fig. 18 shows a top view of the structure of a plurality of test element groups having different areas, which are arranged along a scribed line. FIG. 19 shows a sectional view along a line XIX-XIX according to FIG. 18. According to FIG. 19, a multiplicity of cathode regions C are provided for providing the multiplicity of test element groups.

The evaluation based on the large number of test element groups with different areas referenced by the areas of the A further cathode regions C in the test element groups Change one compared to the conclusion according to the first Embodiment.

Fig. 20 shows a graph with the vertical axis indicating the ON voltage values Vf and the horizontal axis indicating the length L with respect to the cathode regions C. The length L with respect to the cathode regions C corresponds to half the length of one side of a square of the real test element group , or the radius of a circle of the modeled test element group. Since an area is proportional to a square of the length, this figure shows a correlation between the life values, the areas of the cathode areas C and the ON voltage values Vf.

In the first embodiment, there was no change in the area of the test element groups in the conclusion. In contrast, the present exemplary embodiment comprises modified areas, so that, as shown in FIG. 20, data are represented not by points but by lines. This improves the reliability of the conclusion compared to the first embodiment.

In the graph of Fig. 20 is the real test element group of the charge carrier lifetime value, indicated by white circles, very close to the simulation result with the charge carrier lifetime of 10 microseconds, which is arranged by black circles. The charge carrier lifetime value of the real test element group can thus be assumed to be approximately 10 µs.

The workload in an analysis can be reduced by using a display device for inputting respective data for the real and the modeled test element group, which are obtained by the processes according to FIGS . 8 and 10 (service life value τ, length L and ON voltage value Vf as Parameters), and for automatically printing this data for a display according to FIG. 20.

According to the description in the context of the first embodiment can by means of the method described above obtained lifetime value are checked by comparisons the same with the lifetime value, which by means of the known Process using the invention Test element group was obtained.

Figs. 21 and 22 show graphs corresponding to Figs. 33 and 34, respectively . In Fig. 21, the vertical axes on the left and right sides indicate a current value I in the test element group and a current density, respectively, and the horizontal axis denotes time regarding the application of a pulse voltage. In this graphic representation, white circles denote values of the real test element group in which each side of a square of the emitter region E is 100 μm and black triangles denote simulation results in which the lifetime value τ is 8 μs for obtaining a relation as shown in FIG. 22. Fig. 22 is a graphical representation obtained by forming lines between simulation results for each current value at every predetermined value of the load resistance. The vertical and horizontal axes each show the blocking delay time Trr and the service life value τ. The blocking delay time Trr of the real test element group can be read at 5.85 μs from FIG. 21. In Fig. 22, black squares correspond to the case where the current value at the predetermined value of the pulse voltage is ± 10 mA. The lifetime value at the intersection of the lines drawn between the black squares and the blocking delay time of 5.85 µs is 8 µs.

Thus, the lifespan values achieved using the present and the known method are 10 µs and 8 µs. Taking into account the fact that only sample service life values can be obtained using the known method, it is ensured that the service life values can be concluded using the present method. Fig. 22 also shows the case where the current values at the predetermined value of the load resistor are each ± 20 mA to ± 100 mA. The blocking delay time Trr for the current values of ± 20 mA and ± 100 mA is 4.17 µs and 2.29 µs, respectively.

Although the test element groups are arranged along the scribed line as described above, the plurality of test element groups are not only arranged along the scribed line. Fig. 23 shows a top view of the structure of a plurality of test elements groups of chips CH1 and CH2, which are provided for product purposes, and chips CH3 and CH4, which are provided for the evaluation of the chips CH1 and CH2.

A large number of test element groups are included in the chip CH1 different areas. The chip CH4 includes one Large number of randomly distributed test element groups. The CH3 chip  is almost completely occupied with a test element group Increasing the variation of the area of the cathode areas C.

In this embodiment, step SB7 is added to the flow of FIG. 10 due to the formation of the plurality of test element groups. Fig. 24 is a flow chart showing a simulation process including the step SB7. Step SB7 is inserted between steps SB4 and SB5 according to FIG. 10 to check whether the simulation was carried out for all areas of the test element groups. If the answer in step SB7 is "YES", the flow next goes to step SB5. On the other hand, if the answer is "NO", then the process returns to step SB3 to carry out a simulation of the remaining areas of the test element groups. With respect to the flow shown in Fig. 8, the processing of steps SA0 to SA3 is required for each area.

Training the multitude of test element groups with the Cathode areas C in different areas according to the The present exemplary embodiment improves the reliability the load carrier lifetime evaluation.

Sixth embodiment

Referring to Fig. 20, the ON voltage values Vf are isolated from each other in the simulation for each lifetime value because the area (length) of the cathode area C is smaller. On the other hand, if the area of the cathode region C is large, and for example the length L is about 3 × 10 ³ μm, then the simulation results are close to each other.

Are the simulation results close to each other and is the measured value of the real test element group between them Simulation results arranged, then it is difficult  find out which result is close to the measured value lies. However, it is very easy if the simulation results are isolated from each other. It is therefore desirable to provide the areas of the cathode regions C small, so that the Simulation results are isolated from each other. Here means the statement "The area of the cathode region C is small "that the cathode area C is small compared to the Anode area A. It will be described below how the Dimensions of the cathode area C are to be set Reduction of an area ratio between the area of the Cathode area and that of the anode area A. Zur Description of an area ratio requires that a standard area must be determined for clarification. Therefore is the area of the components on the wafer first described.

Fig. 25 shows a sectional view of the semiconductor wafer W by means of a dash-dotted line and separated from the semiconductor wafer W chip CH with a solid line. As can be seen from the figure, when the chip CH is separated from the semiconductor wafer W, the area of the anode region A to form a pair with the cathode region C changes from a state before to a state after the division. It is therefore important to clearly define respective areas as a cathode and anode area C and A to form a pair that belongs together.

As shown in FIG. 26, both the cathode and anode regions C and A in the chip CH comprise six surfaces including the top and bottom surfaces and the side surfaces. The area of the cathode region C is regarded as the area which forms the upper surface of the chip CH having these surfaces. In the same way, the anode region A is regarded as a surface which forms the lower surface of the chip CH having the six surfaces.

Fig. 27 is a sectional view for illustrating the extent to which the anode area A a cathode region C corresponds. The intersection of the center line, which passes through the center of the cathode region C and the anode region A, indicates that an area 5h five times as long as the height h of the semiconductor wafer W (chip CH) in the anode region A (with a width of 10h including the right one) and left sides) forms a pair with the cathode region C. The area within this area actually serves as the anode area for the cathode area C, and the current flows from the anode area A to the cathode area C, as shown by the arrows in the figure.

The area actually serving as anode area A is referred to below as functional area WT. Furthermore, the ratio of the areas between the emitter area E and the functional area WT is referred to as an area Ra (an area of the cathode area C to that of the functional area WT). Fig. 28 shows a perspective view of the cathode region C and the functional area WT.

How the area of the cathode region C is made small so that the simulation results differ from each other in the manner described above will now be described. Referring to Fig. 20, when the ratio Ra is 1, the rightmost data with the length L of about 3 × 10 ³ µm is obtained. According to the figure, a sufficient distance is maintained between the respective data of the area of length L below 10 ² μm. Since an area is proportional to the square of the length, it is sufficient to form the emitter region E so that the area ratio Ra is in a range of about 1/1 750,000 to 1/4500.

The reduction in the area ratio makes it easy to Way the correlation between the actual measurement and the Monitor simulation. Furthermore, the accuracy of the Evaluation improved, which also improves the Reliability of the result is achieved.

The invention thus relates to test element groups for improvement the accuracy of the evaluation of Lifetime values. The test element groups include one Base area, which is selectively a cathode area in one Surface part thereof, and an anode area. The intersection of a center line of the cathode area and the Anode area forms a functional area which is within a Span of 5h is d. H. five times the height h one Semiconductor wafer. The functional area forms a pair with the Cathode area and serves as the current anode area for the Cathode area. Since an area ratio of the cathode area too the functional area is smaller, ON voltage values Vf isolated from each other with respect to the respective service life values will. The cathode region is therefore designed in such a way that the area ratio of the area of the cathode area to that of the functional area between about 1/1 750 000 and 1/4500 lies.

Claims (9)

1. Test pattern area for evaluating the service life, which is formed on a semiconductor substrate (W, CH) with a first and second main surface, for evaluating the charge carrier life in the semiconductor substrate, the semiconductor substrate comprising:
a first line layer (Ba) of a first line type (N) with a relatively low impurity concentration, the first line layer forming the first main surface,
a second line layer (Bu) of the first line type (N) with a relatively large impurity concentration, and
a third line layer (A) of a second line type (P), which is different from the first line type (N), and forms the second main surface, an electrode region with a relatively large impurity concentration being selectively in a surface region (C) of the first line layer on one side of the is formed first main surface. 2. Evaluation pattern area for the service life evaluation, which is formed on a semiconductor substrate (W, CH) with a first and second main surface, for evaluation of the charge carrier service life in the semiconductor substrate,
wherein a first conduction layer (Ba, C) of a first conduction type and a second conduction layer (A) of a second conduction type, which is different from the first conduction type, each form the first and second main surface, and the first conduction layer comprises:
an electrode region (C) with a relatively large impurity concentration, which is formed in a surface region on one side of the first main surface,
and a connection area (Ba) with a relatively low impurity concentration for connecting the electrode area and the second conduction layer,
wherein an area ratio between the electrode area on the first main surface and an area on the second main surface serving as the electrode area is determined such that the voltage values are isolated from each other in simulating the evaluation of the carrier life by obtaining voltage values (Vf) at a reference current value (I ₀ ) for the respective large number of discrete values for specifying the charge carrier life as a parameter. 3. Evaluation pattern area for life evaluation according to Claim 2, wherein the electrode region (C) a plurality of Has electrode areas with different areas. 4. Evaluation pattern area for life evaluation Claim 1, wherein the electrode region (C) along a scribed line is arranged on the semiconductor substrate. 5. Evaluation pattern area for life evaluation Claim 3, wherein the plurality of electrode regions along a scratched line is arranged on the semiconductor substrate.   6. Evaluation pattern area for life evaluation Claim 1, wherein the electrode region (C) on the Semiconductor substrate in a chip provided for the evaluation is arranged. 7. Evaluation pattern area for life evaluation Claim 3, wherein the plurality of electrode areas on the Semiconductor substrate are arranged in a chip, which for Evaluation is provided. 8. Evaluation pattern area for life evaluation Claim 1, wherein the electrode region (C) on the Semiconductor substrate is arranged in a chip which for Use as a product is intended. 9. Evaluation pattern area for life evaluation Claim 3, wherein the plurality of electrode areas on the Semiconductor substrate are arranged in a chip, which for Use as a product is intended.