DE19716674A1 - Semiconductor component with two or more chips for multiple switch - Google Patents

Semiconductor component with two or more chips for multiple switch

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Publication number
DE19716674A1
DE19716674A1 DE1997116674 DE19716674A DE19716674A1 DE 19716674 A1 DE19716674 A1 DE 19716674A1 DE 1997116674 DE1997116674 DE 1997116674 DE 19716674 A DE19716674 A DE 19716674A DE 19716674 A1 DE19716674 A1 DE 19716674A1
Authority
DE
Germany
Prior art keywords
chips
semiconductor
housing
support plate
semiconductor component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE1997116674
Other languages
German (de)
Inventor
Stefan Schmauser
Xaver Schloegel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE1997116674 priority Critical patent/DE19716674A1/en
Publication of DE19716674A1 publication Critical patent/DE19716674A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The component includes at least two semiconductor chip (1). Each chip is fitted to its own supporting plate (2) and wire-bonded (6) to a bent connecting element (5) which protrudes from the package (3). The plate itself forms the uncovered underside of the package. The selected number of preassembled chips are moulded together before the upper connecting strip is separated from the plates, and the lower strip is detached from the connecting elements. The mould material covers only the chips and their wire bonds, and not the undersides of the plates.

Description

Die Erfindung betrifft ein Halbleiter-Bauteil, insbesondere für Mehrfachschalter. In der Leistungselektronik werden heutzutage häufig Halbleiter-Bauteile eingesetzt, bei denen mehrere, d. h. zumindest zwei, Halbleiter-Bauelemente bzw. Halbleiter-Chips in einem Gehäuse angeordnet sind. Aufgrund der Technologie moderner Halbleiter-Bauelemente - es handelt sich hierbei in der Regel um MOS-Transistoren - ist es notwendig, daß eine elektrische Trennung der einzelnen Halbleiter-Chips vorgesehen ist.The invention relates to a semiconductor component, in particular for multiple switches. In power electronics Nowadays semiconductor components are often used in which several, d. H. at least two semiconductor components or Semiconductor chips are arranged in a housing. Because of the technology of modern semiconductor components - it acts are usually MOS transistors - it is necessary that an electrical separation of the individual Semiconductor chips is provided.

Aus der US 5,019,893 ist ein derartiges Halbleiter-Bauteil bekannt, bei dem in einem Gehäuse zwei Trageplatten angeordnet sind, die elektrisch isoliert voneinander beabstandet sind. Auf jeder dieser Trageplatten ist ein Halbleiter-Chip angeordnet. Die Halbleiter-Chips sind aufgrund der isolierten Beabstandung der Trageplatten ebenfalls voneinander isoliert. Das Gehäuse umgibt die Trageplattenanordnung mit den Chips vollständig, so daß der Nachteil besteht, daß die insbesondere bei Leistungsbauelementen in erheblichem Maße anfallenden Wärme über das Gehäuse abgeführt werden muß.Such a semiconductor component is known from US Pat. No. 5,019,893 known, in which two support plates in a housing are arranged, which are electrically isolated from each other are spaced. There is a on each of these support plates Semiconductor chip arranged. The semiconductor chips are due to the isolated spacing of the support plates also isolated from each other. The housing surrounds the Support plate arrangement with the chips completely, so that the The disadvantage is that in particular Power components heat to a significant extent must be dissipated through the housing.

Der Erfindung liegt somit die Aufgabe zugrunde, ein Halbleiter-Bauteil vorzusehen, bei dem mit geringem Aufwand eine verbesserte Wärmeabfuhr gewährleistet ist.The invention is therefore based on the object Provide semiconductor device in which with little effort an improved heat dissipation is guaranteed.

Diese Aufgabe wird erfindungsgemäß mit den im Patentanspruch 1 angegebenen Merkmalen gelöst.This object is achieved with the in claim 1 specified features solved.

Es sind zumindest zwei Halbleiter-Chips vorgesehen, die jeweils auf voneinander getrennten Trageplatten angeordnet sind. Weiterhin ist ein Gehäuse vorgesehen, das eine Unterseite aufweist, die eine Seite der Trageplatte, die vom Halbleiterchip abgewandt ist, freiläßt. Auf diese Weise deckt das Gehäuse die Trageplatte auf der dem Halbleiter-Chip abgewandten Seite der Trageplatte nicht ab, so daß die vom Halbleiter-Chip erzeugte Wärme leicht über die Trageplatte abführbar ist.At least two semiconductor chips are provided, the each arranged on separate support plates are. Furthermore, a housing is provided, the one Underside, which has one side of the support plate, from the  Semiconductor chip is facing away, leaves free. That way covers the housing the support plate on the semiconductor chip facing away from the support plate, so that the from Semiconductor chip easily generates heat via the support plate is dissipatable.

Weitere vorteilhafte Ausgestaltungen der Erfindung sind in den Unteransprüchen angegeben.Further advantageous embodiments of the invention are in specified in the subclaims.

Nachfolgend wird die Erfindung unter Bezugnahme auf die Zeichnung erläutert.The invention is described below with reference to FIG Drawing explained.

Fig. 1 zeigt im Querschnitt ein erfindungsgemäßes Halbleiter-Bau­ teil und Fig. 1 shows a cross section of a semiconductor construction according to the invention and

Fig. 2 zeigt als schematische Darstellung eine Draufsicht auf eine Leadframe-Halbleiter-Chipanordnung. Fig. 2 shows a schematic representation of a top view of a leadframe semiconductor chip assembly.

In Fig. 1 ist eine Trageplatte 2 dargestellt, auf der ein Halbleiter-Chip 1 angeordnet ist. Weiterhin ist ein Anschlußelement 5 vorgesehen, das auf gebogene Weise an den Halbleiter-Chip herangeführt ist. Zum Kontaktieren des Anschlußelements 5 und des Halbleiterchips 1 ist eine Bondverbindung 6 vorgesehen.In Fig. 1, a support plate 2 is shown, on which a semiconductor chip 1 is arranged. Furthermore, a connection element 5 is provided which is brought to the semiconductor chip in a curved manner. A bonding connection 6 is provided for contacting the connection element 5 and the semiconductor chip 1 .

Weiterhin ist ein Gehäuse 3 vorgesehen, das die Trageplatte 2 mit dem Chip 1 einschließlich einem Teil des Anschlußelementes 5 mit der Bondverbindung abdeckt. Das Gehäuse 3 ist derart ausgebildet, daß es seitlich mit der Trageplatte 2 abschließt, diese jedoch auf der Unterseite, d. h. der vom Halbleiter-Chip 1 abgewandten Seite, nicht abdeckt.Furthermore, a housing 3 is provided which covers the support plate 2 with the chip 1 including a part of the connection element 5 with the bond connection. The housing 3 is designed such that it closes laterally with the support plate 2 , but does not cover it on the underside, ie the side facing away from the semiconductor chip 1 .

Gemäß Fig. 2 ist eine Leadframe-Anordnung zu sehen, bei der ein oberes Band B ausgebildet ist, von dem die Trageplatten 2 abgehen. Weiterhin ist ein unteres Band U ausgebildet, das zur Trageplatte 2 benachbarte Anschlußelemente 5 verbindet, wobei zwischen jeweils zwei Anschlußelementen 5, die einer Trageplatte 2 zugeordnet sind, ein drittes Anschlußelement vorgesehen ist, das direkt mit der Trageplatte 1 verbunden ist. FIG. 2 is seen an arrangement of the lead frame, wherein an upper band B is formed, from which depart the supporting plates 2. Furthermore, a lower band U is formed, 5 adheres adjacent to the support plate 2, connecting elements, wherein a third connection element is provided between each two connection elements 5, which are associated with a support plate 2 which is directly connected to the support plate. 1

Wie aus Fig. 2 weiterhin erkenntlich ist, wird zur Herstellung des Halbleiter-Bauteils auf jede Trageplatte 2 ein Halbleiter-Chip 1 aufgebracht, der sodann mittels Bondverbindungen 6 mit einem jeweils in die Nähe herangeführten Anschlußelement 5 verbunden ist. Das mit der Trageplatte 1 verbundene Anschlußelement dient zur elektrischen Kontaktierung der Halbleiter-Chipseite, die mit der Trageplatte 1 verbunden ist. Nach dieser Vormontage, werden entsprechend der gewünschten Anzahl vormontierte Halbleiter-Chips von einem Gehäuse 3 mittels Preßmasse eingeschlossen, deren Außenränder in Fig. 2 mittels der gestrichelten Linie 4 angedeutet ist. Nachdem der Halbleiterchip vom Gehäuse umgeben ist, wird das obere Verbindungsband B von den Trageplatten 1 abgetrennt. Weiterhin werden die Verbindungen zwischen den Anschlußelementen 5, die durch das untere Band U gebildet sind, getrennt. Auf diese Weise entsteht ein Halbleiter-Bau­ teil, das voneinander elektrisch isolierte Anschlüsse aufweist, bei dem auch die Trageplatten 2 voneinander elektrisch isoliert sind. Wie aus Fig. 2 weiterhin zu sehen ist, werden ebenfalls die Räume zwischen den Trageplatten und über die Trageplatten seitlich hinausgehende Bereiche von der Preßmasse des Gehäuses 3 umgeben. Auf diese Weise entsteht eine Unterseite des Gehäuses 3, die sowohl mit den Trageplatten als auch mit den Anschlußelementen abschließt, wobei die der Chip zugewandten Seite gegenüberliegenden Seite der Trageplatte 2 nicht von der Preßmasse abgedeckt ist.As can also be seen from FIG. 2, a semiconductor chip 1 is applied to each support plate 2 in order to produce the semiconductor component, which semiconductor chip 1 is then connected by means of bond connections 6 to a connecting element 5 which is brought into the vicinity. The connection element connected to the support plate 1 is used for electrical contacting of the semiconductor chip side which is connected to the support plate 1 . After this pre-assembly, according to the desired number of pre-assembled semiconductor chips are enclosed by a housing 3 by means of a molding compound, the outer edges of which are indicated in FIG. 2 by the dashed line 4 . After the semiconductor chip is surrounded by the housing, the upper connecting band B is separated from the support plates 1 . Furthermore, the connections between the connection elements 5 , which are formed by the lower band U, are separated. In this way, a semiconductor construction is created, which has mutually electrically insulated connections, in which the support plates 2 are electrically insulated from each other. As can also be seen from FIG. 2, the spaces between the support plates and areas extending laterally beyond the support plates are also surrounded by the molding compound of the housing 3 . In this way, an underside of the housing 3 is formed , which closes both with the support plates and with the connection elements, the side of the support plate 2 facing the chip not being covered by the molding compound.

Auf diese Weise kann das Halbleiter-Bauteil mit seinem Gehäuse beispielsweise so montiert werden, daß auf der Unterseite des Halbleiter-Bauteiles über die einseitig freiliegende Trageplatte 2, die durch die Halbleiter-Chips im Betrieb erzeugte Wärme leicht abführbar ist.In this way, the semiconductor component with its housing can be mounted, for example, in such a way that on the underside of the semiconductor component via the support plate 2 , which is exposed on one side, the heat generated during operation by the semiconductor chips can be easily dissipated.

Claims (4)

1. Halbleiter-Bauteil mit1. Semiconductor component with - zumindest zwei Halbleiter-Chips (1), die jeweils auf voneinander getrennten Trageplatten (2) angeordnet sind und einem Gehäuse (3), dadurch gekennzeichnet, daß das Gehäuse (3) eine Unterseite aufweist, die eine Seite der Trageplatte (2), die vom Halbleiter-Chip (1) abgewandt ist, freiläßt.- At least two semiconductor chips ( 1 ), which are each arranged on separate support plates ( 2 ) and a housing ( 3 ), characterized in that the housing ( 3 ) has an underside, which is one side of the support plate ( 2 ), which faces away from the semiconductor chip ( 1 ). 2. Halbleiter-Bauteil nach Anspruch 1, dadurch gekennzeichnet, daß das Gehäuse (3) aus Preßmasse hergestellt ist.2. Semiconductor component according to claim 1, characterized in that the housing ( 3 ) is made of molding compound. 3. Halbleiter-Bauteil nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, daß das Gehäuse (3) an der Trageplatte (2) anliegt.3. Semiconductor component according to one of claims 1 or 2, characterized in that the housing ( 3 ) bears on the support plate ( 2 ).
DE1997116674 1997-04-21 1997-04-21 Semiconductor component with two or more chips for multiple switch Ceased DE19716674A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE1997116674 DE19716674A1 (en) 1997-04-21 1997-04-21 Semiconductor component with two or more chips for multiple switch

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DE19716674A1 true DE19716674A1 (en) 1998-08-20

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19843479A1 (en) * 1998-09-22 2000-03-30 Siemens Ag Semiconducting component
EP1291916A2 (en) * 2001-09-10 2003-03-12 Delphi Technologies, Inc. Electric module
DE10149774A1 (en) * 2001-10-09 2003-04-24 Bosch Gmbh Robert Process for packing electronic modules comprises applying a power semiconductor chip on a base plate, applying a logic chip on the base plate, connecting the logic chip with the semiconductor chip, and packing the module
DE102006049949B3 (en) * 2006-10-19 2008-05-15 Infineon Technologies Ag Semiconductor module, has flat conductor chip island defining electrically conducting portion and insulation layer, and semiconductor chip arranged on electrically conducting portion and positively bonded on insulation layer
DE10013255B4 (en) * 1999-03-18 2009-12-17 Hitachi, Ltd. Resin encapsulated electronic device for use in internal combustion engines
US7923827B2 (en) 2005-07-28 2011-04-12 Infineon Technologies Ag Semiconductor module for a switched-mode power supply and method for its assembly

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019893A (en) * 1990-03-01 1991-05-28 Motorola, Inc. Single package, multiple, electrically isolated power semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5019893A (en) * 1990-03-01 1991-05-28 Motorola, Inc. Single package, multiple, electrically isolated power semiconductor devices

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19843479A1 (en) * 1998-09-22 2000-03-30 Siemens Ag Semiconducting component
DE10013255B4 (en) * 1999-03-18 2009-12-17 Hitachi, Ltd. Resin encapsulated electronic device for use in internal combustion engines
EP1291916A2 (en) * 2001-09-10 2003-03-12 Delphi Technologies, Inc. Electric module
EP1291916A3 (en) * 2001-09-10 2005-10-19 Delphi Technologies, Inc. Electric module
DE10149774A1 (en) * 2001-10-09 2003-04-24 Bosch Gmbh Robert Process for packing electronic modules comprises applying a power semiconductor chip on a base plate, applying a logic chip on the base plate, connecting the logic chip with the semiconductor chip, and packing the module
US7042085B2 (en) 2001-10-09 2006-05-09 Robert Bosch Gmbh Method for packaging electronic modules and multiple chip packaging
US7923827B2 (en) 2005-07-28 2011-04-12 Infineon Technologies Ag Semiconductor module for a switched-mode power supply and method for its assembly
DE102006049949B3 (en) * 2006-10-19 2008-05-15 Infineon Technologies Ag Semiconductor module, has flat conductor chip island defining electrically conducting portion and insulation layer, and semiconductor chip arranged on electrically conducting portion and positively bonded on insulation layer
US8330252B2 (en) 2006-10-19 2012-12-11 Infineon Technologies Ag Integrated circuit device and method for the production thereof

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