DE19711483C2 - Vertical MOS transistor and method for its production - Google Patents

Description

With regard to ever faster components at higher In Density of integration takes the structure sizes more integrated Circuits from generation to generation. This also applies for CMOS technology. It is generally expected (see for example Roadmap of Semiconductor Technology, Solid State Technology 3, (1995), p. 42 ff) that around 2010 MOS- Transistors with a gate length of less than 100 nm be set.

On the one hand, attempts are being made to develop planar MOS transistors with such gate lengths by scaling the CMOS technology that is common today. However, negative electrical properties occur which can be eliminated with great effort (see, for example, K. Takeuchi, T. Yamamoto, A. Furuka wa, T. Tamura, K. Yoshida, High performance sub-tenth micron CMOS using advanced boron doping and WSi ₂ dual gate process, Symp. VLSI-Technology 9, (1995); A. Hori, H. Nakaoka, H. Umi moto, K. Yamashita, M. Takase, N. Shimizu, B. Mizuno, S Odanaka, A 0.05 µm-CMOS with Ultra Shallow Source / Drain Junctions Fabricated by 5 keV Ion Implantation and Rapid Thermal Annealing, IEDM 1994, 485; T. Hori, A 0.1 µm CMOS Technology with Tilt-Implanted Punchthrough Stopper (TIPS ), IEDM 1994, 75; T. Izawa, K. Watanabe, S. Kawamura, 21-ps 0.1 µm CMOS Devices Operating at Room Temperature, Elec. Dev. Lett. 14 (11), 533-535, (1993); Y. Mii, S. Wind, Y. Taur, Y. Lii, D. Klaus, J. Bucchignano, An Ultra-Low Power 0.1 µm CMOS, Symp. VLSI Technology, 9, (1994); K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, K. Nakajima, H. Miyamoto, T. Hashimo to, I. Sa saki, 0.1 µm Delta-doped MOSFET Using Post Low energy Implanting Selective Epitaxy, Symp. VLSI Technology, 21, (1994); H. Hu, LT Su, Y. Yang, DA Antoniadis, HI Smith, Channel and Source / Drain Engineering in High-Performance sub-0.1 µm NMOSFETs using X-Ray lithography, Symp. VLSI-Technology, 17, (1994); M. Yoshimi, H. Hazama, M. Takahaski, S. Kambayashi, T. Wada, K. Kato, H. Tango, Two-Dimensional Simulation and Measurement of High-Performance MOSFET's Made on a Very Thin SOI Film, Trans. Elec . Dev. 36, 493-503, (1989).

One way to overcome these difficulties is to use a modified substrate material. By using so-called SOI substrates, which comprise a monocrystalline silicon layer, an insulating layer arranged underneath and a carrier disk made of silicon, it is possible to increase the packing densities and reduce the process costs. The components are realized in the monocrystalline silicon layer, so that they are insulated down to the carrier substrate by the insulating layer. They show reduced capacities, better sub-threshold gradients and better pn junctions, so that they are faster, have a lower power consumption and show lower leakage currents. A disadvantage of this SOI technology lies in the SOI substrates themselves, which are unsatisfactory in terms of homogeneity today and are also very expensive to produce. Additional problems occur at the silicon SIO ₂ interfaces (see, for example, A. Usami, T. Natori, A. Ito, S. Ishigami, Y. Tokuda, T. Wada, Study of Electrical Properties of Defects in SOI Films by Wa fer Bonding, Mat. Res. Soc. Symp. Proc. 262, (1992); J. Boussey-Said, N. Guillemot, J. Stoesmenos, D. Tsoukalas, Oxidation Stacking Faults in SIMOX and SOI Structures Obtaining by Wafer -Bonding, J. Electrochem. Soc. 140 (2), 544, (1993); C. Oules, A. Halimaoui, JL Regolini, A. Perio, G. Bomchil, SOI Structures Obtained by Epitaxial Growth of Silicon over Porous Silicon , J. Electrochem. Soc. 139 (12), 3595, (1992)).

At the same time, vertical gates are used to achieve short gate lengths le transistors examined (see for example L. Risch, W. H. Krautschneider, F. Hofmann, H. Schäfer, Vertical MOS Tran  sistor with 70 nm channel length, ESSCERC 1995, 101-104; H. Gossner, F. Wittmann, W. Hansch, I. Eisele, T. Grabolla, D. Behammer, Vertical MOS-Technology with Sub-0.1 µm Channel Lengths, Elec. Lett. 31, 1394-1396, (1995)). In doing so Layer sequences according to source, channel and drain det, the ring-shaped of gate dielectric and, gate electrode are surrounded. These vertical MOS transistors are in the Ver equal to planar MOS transistors in terms of their freq quency and logic properties so far unsatisfactory.

The invention has for its object a vertical MOS transistor with improved high-frequency properties admit. Furthermore, a method for the production thereof can be specified.

According to the invention, this problem is solved by a MOS Transistor according to claim 1 and by a method of the Sen manufacture according to claim 5. Further refinements of Invention emerge from the subclaims.

On a main surface of a substrate, preferably one monocrystalline silicon wafer or the monocrystalline Silicon layer of an SOI substrate is one to the main surface vertical, mesa-shaped layer sequence arranged. It includes a source layer, a channel layer and a drain layer in vertical succession. At least on the surface the channel layer is a gate dielectric and a gate electrode arranged trode. The gate electrode opposite is on the Surface of the layer sequence on a dielectric structure ordered, the height of which is at least as great as that of the Schich sequence is. The dimension of the layer sequence between the Gate dielectric and the dielectric structure is so ge chooses that the MOS transistor is completely depleted. Before preferably this dimension is less than or equal to Layer thickness of the channel layer. This behaves electrically MOS transistor like a planar MOS transistor in SOI Technology that is completely impoverished. At the same time, the  Problems with the use of SOI substrates regarding the Homogeneity and the interfaces avoided.

It is within the scope of the invention that the layer sequence contains layers of silicon, Si _1-x Ge _x with x <1, Si _1-y C _y with y <1 and / or germanium.

The cross section of the layer sequence parallel to the main surface can have any shape. In particular, it is in the frame the invention, the layer sequence with a rectangular, to form a round or annular cross section. Is the cross cut ring-shaped, so is the dielectric structure on the inner surface of the ring and the gate electrode on the outer outer surface of the ring or vice versa.

It is within the scope of the invention on the surface of the electrical structure to provide a conductive structure that can be wired in the sense of a backgate electrode. In In this case, you can apply a potential to the conductive structure affects the potential in the channel layer rivers.

Preferably, the vertical MOS transistor is used self-adjusting process steps. This will a mesa structure on a main surface of a substrate forms a layer sequence in the vertical to the main surface Drain layer, a channel layer, a source layer and one Has top layer. The vertical layer sequence is in front preferably formed by epitaxial growth. By Epi layers formed by taxie can be thick with egg with an accuracy of approx. 1 percent.

A first insulating layer is deposited in such a way that their layer thickness in layer parts that are parallel to Main area are arranged, is larger than in others Layer parts. By isotropically etching the first insulating Layer becomes the surface of the mesa structure on the sides  walls of the mesa structure are exposed. On the surface of the Cover layer and remains on the main surface of the substrate part of the first insulating layer to protect the Surface.

Then the channel is at least on the surface layer formed a gate dielectric. It becomes a conductive layer deposited over the mesa structure.

A second insulating layer is subsequently formed and planarized, which essentially covers the mesa structure. The second insulating layer is etched back Partial surface of the conductive layer, that is, in upper part of the mesa structure, exposed.

Then the conductive layer is partially removed, so that between the cover layer and the second insulating Layer creates a gap with an isolation structure is replenished. In this way it is self-adjusted from the conductive layer formed a gate electrode.

The top layer becomes selective to the second insulating Layer, the insulation structure and the source layer ent distant. A first is created above the source layer Trench that is laterally delimited by the isolation structure. Spacers are formed on the flanks of the first trench. These spacers are used together with the insulation structure and the second insulating layer used as an etching mask the source layer, the channel, in an anisotropic etching process layer and structure the drain layer. This creates a second ditch. The sequence of layers is also created Source layer, channel layer and drain layer with a ring shaped cross section. The width of the ring is determined by the Width of the spacers determined. It is independent of a pho tolithography adjustable.  

Then at least the flanks of the second Gra bens covered with a dielectric structure.

To reduce the connection resistance of the drain layer it within the scope of the invention, before the deposition of the first isolating layer on the flanks of the mesa structure isolie to form spacers. By implantation in the main area the substrate is then a connection area for the Drain layer formed. The insulating spacers protect the flanks of the mesa structure.

It is within the scope of the invention that the dielectric Structure in the second trench dielectric spacers on the flan the second trench, a conductive core in the middle the dielectric spacer that is connected to the substrate and has a dielectric cover. Alternatively the dielectric structure completely fills the second trench dig on.

The contact holes preferably become the source layer self-adjusting opened by the spacers on the flanks of the first trench can be removed by selective etching.

In the following the invention is based on exemplary embodiments play, which are shown in the figures, explained in more detail tert.

Fig. 1 shows a section through an SOI substrate with a mesa structure with a drain layer, a channel layer, a source layer and a cover layer, the flanks of which are provided with spacers.

Fig. 2 shows the section through the substrate after the whole area according to deposition of a first insulating layer.

Fig. 3 shows the section according to isotropic etching back of the first insulating layer.

Fig. 4 shows the section after thermal oxidation, from separation of a conductive layer, pre-structuring of the conductive layer and deposition and etching back of a planarizing second insulating layer.

Fig. 5 shows the cross section after formation of a gate electrode by etching back the conductive layer.

Fig. 6 shows the section after removing the cover layer and formation of spacers on the flanks of a first Gra bene.

Fig. 7 shows the section after structuring the source layer, channel layer and drain layer.

Fig. 8 shows the section after formation of a dielectric structure in a second trench and self-adjust the opening of contacts to the source layer.

Fig. 9 shows the section after formation of metal contacts to the source layer, the gate electrode and the drain layer.

Fig. 10 shows a section through a silicon substrate with connection areas for a drain layer and a measurement structure with a drain layer, a channel layer, a source layer and a cover layer, the flanks of which are covered with spacers.

Fig. 11 shows the section through the substrate after deposition and etching back of a first insulating layer, Bil dung of a gate dielectric, deposition and before patterning of a conductive layer, formation of egg ner second planarizing layer, etching back the conductive layer to form a gate electrode, removing the top layer , Formation of spacers and structuring of the source layer, channel layer and drain layer.

Fig. 12 shows the cross section after formation of dielectric spacers on the sidewalls of the second trench.

Fig. 13 shows a section through the substrate after formation of a doped polysilicon filling in the second trench and a dielectric cover above the doped polysilicon filling.

Fig. 14 shows the section through the substrate after self-opening of contact holes to the source layer and the formation of metal contacts to the source layer, to the drain layer and to the gate electrode.

On a main surface of an SOI substrate, which has a silicon carrier wafer 11 , an insulating layer 12 and a silicon layer 13 , a mesa structure is formed which has a drain layer 14 , a channel layer 15 , a source layer 16 and a cover layer 17 . The drain layer 14 is formed, for example, from n-doped silicon with a doping concentration of 10 ²¹ cm ^-3 and a thickness of 100 nm. The channel layer 15 is formed, for example, from p-doped silicon with a dopant concentration of 10 ¹⁸ cm ^-3 in a thickness of 100 nm. The source layer 16 is formed, for example, from n-doped silicon with a dopant concentration of 10 ²¹ cm ^-3 in a layer thickness of 200 nm. The cover layer 17 is formed for example from 500 nm thick Si ₃ N ₄ .

The mesa structure is preferably produced by epitaxial growth using a process gas containing Si ₂ H ₂ Cl ₂ , B ₂ H ₆ and AsH ₃ in the temperature range 840 ° C. to 920 ° C. and in the pressure range 500 Pa to 2000 Pa for doped silicon layers accordingly the drain layer 14 , channel layer 15 and source layer 16 and by applying a 500 nm thick Si ₃ N ₄ layer. The mesa structure is then formed by anisotropically etching this layer sequence using a photolithographically formed mask. The mesa structure has, for example, an edge length of 0.6 μm and has a square cross section (see FIG. 1).

SiO ₂ spacers 18 are formed on the flanks of the mesa structure by conformal deposition of an SiO ₂ layer and anisotropic etching back of the SiO ₂ layer. The SiO ₂ spacers have a width of approximately 50 nm.

Subsequently, in the monocrystalline silicon layer 13, a connection region 19 for the drain layer 14 is formed by ion implantation, for example with As. In the area 19 an impurity concentration of, for example, 10 ²¹ cm ^{-3 is} set.

Subsequently, a metal silicide layer 110 is formed to further reduce the connection resistance of the drain layer 14 on the surface of the connection region 19 . The metal silicide layer 110 is formed, for example, in a self-aligned manner by applying a metal layer, for example from cobalt and selective silicide formation on the surface of the silicon.

There follows the non-conformal deposition of a first insulating layer 111 (see FIG. 2). The first insulating layer 111 is deposited in a non-conforming manner in the sense that layer parts parallel to the main surface are thicker than other layer parts. In particular, the layer parts arranged on the side walls of the measurement structure are significantly less thick than the horizontal layer parts. The first insulating layer 111 has a thickness of 500 nm in horizontal parts, for example, while it has a thickness of 250 nm in the region of the flanks of the mesa structure. The first insulating layer 111 is formed, for example, in an LPCVD process using a process gas containing SiH ₄ and O ₂ .

The is insulating layer 111 is etched back by isotropic etching with, for example, NH ₄ F, HF. The etching continues until the flanks of the mesa structure are exposed. This means that both the first insulating layer 111 and the SiO ₂ spacer 18 are removed on the flanks of the mesa structure. Since the first insulating layer 111 has a significantly greater layer thickness in horizontal layer parts, a protective layer 111 'remains on the surface of the metal silicide layer 110 and the cover layer 17 in a self-aligned manner (see FIG. 3).

Thermal oxidation is carried out to form a gate dielectric 112 made of SiO ₂ on the flanks of the drain layer 14 , channel layer 15 and source layer 16 . The thermal oxidation is carried out at 800 ° C. The gate dielectric 112 is formed in a layer thickness of 5 nm.

A conductive layer 113, for example made of doped polysilicon, metal silicide, or a combination of the two, is deposited over the entire surface. For example, the conductive layer 113 is formed to a thickness of 200 nm. With the aid of a photolithographically structured mask (not shown), the conductive layer 113 is structured such that it covers the mesa structure and extends partially above the metal silicide layer 110 . The conductive layer 113 is insulated from the metal silicide layer 110 by the protective layer 111 ′ arranged in between (see FIG. 4).

Subsequently, a second insulating layer 114 is deposited, planarized and etched back to such an extent that the second insulating layer 114 is approximately comparable in height to the height of the mesa structure. The planarization is carried out, for example, by chemical mechanical polishing. The etching back takes place, for example, by reactive ion etching.

By etching with choline selective to SiO ₂ and Si ₃ N ₄ , a gate electrode 113 'is formed by structuring the conductive layer 113 (see FIG. 5). The etching of the conductive layer 113 is continued until the material of the conductive layer 113 is removed approximately to the level of the boundary layer between the source layer 16 and the channel layer 15 . This creates a gap between the second insulating layer 114 and the cover layer 17 , which is filled with an insulation structure 115, for example made of SiO ₂ (see FIG. 5). The insulation structure 115 is approximately level with the second insulating layer 114 and the cover layer 17 .

The cover layer 17 is then selectively removed from SiO ₂ and silicon, for example with H ₃ PO ₄ at 155 ° C. A first trench 116 is formed , on the flanks of which Si ₃ N ₄ spacers 117 are formed. The Si ₃ N ₄ spacers 117 are formed, for example, by conformal deposition of an Si ₃ N ₄ layer and anisotropic etching back of the Si ₃ N ₄ layer. The Si ₃ N ₄ spacers 117 have a width of 30 nm (see FIG. 6).

The Si ₃ N ₄ spacer 117 , the insulation structure 115 and the second insulating layer 114 are used together as a mask when structuring the source layer 16 , channel layer 15 and drain layer 14 . The structuring takes place, for example, by anisotropic dry etching with HBr, NF ₃ , O ₂ , He. The anisotropic etch continues until the surface of the insulating layer 12 is exposed. This creates a second trench 118 (see FIG. 7).

From the source layer 16 , the channel layer 15 and the drain layer 14 , only a narrow ring remains after the structuring, the width of which is predetermined by the width of the Si ₃ N ₄ spacer 117 . The annular drain layer 14 is connected in a ring shape by the connection region 19 .

The second trench 118 is then filled with a dielectric structure 119, for example made of SiO ₂ (see FIG. 8).

By selectively removing the Si ₃ N ₄ spacers 117 , a source contact hole 120 , which has a width of approximately 30 nm, is opened in a self-adjusted manner. The Si ₃ N ₄ spacers 117 are removed selectively to SiO ₂ and silicon at 155 ° C., for example using H ₃ PO ₄ (see FIG. 8).

After formation of a gate contact hole and drain contact hole by means of photolithographic process steps, a gate contact 121 , a source contact 122 and a drain contact 123 are formed by depositing and structuring a metal layer, for example made of Ti, TiN, W (see FIG. 9).

The photolithographic process steps required in the manufacture for pre-structuring the conductive layer 113 (see FIG. 4) and for opening the contact holes for the gate electrode and the drain contact are not critical with regard to the arrangement and size of the mesa structure.

In a further exemplary embodiment, a mesa structure is formed on a main surface of a substrate 21 , which is, for example, a p-doped monocrystalline silicon wafer, which comprises a drain layer 22 , a channel layer 23 , a source layer 24 and a cover layer 25 (see FIG. 10). The drain layer 22 is preferably formed in a thickness of 100 nm from n-doped silicon with a dopant concentration of 10 ²¹ cm ^-3 . The channel layer 23 is formed in a thickness of 100 nm from p-doped silicon with a doping concentration of 10 ¹⁸ cm ^-3 . The source layer 24 is formed in a thickness of 200 nm from n-doped silicon with a dopant concentration of 10 ²¹ cm ^-3 ge. The cover layer 25 is formed with a thickness of 500 nm from Si ₃ N ₄ . The mesa structure is layered by epitaxial growth of appropriately doped silicon and an Si ₃ N ₄ layer and subsequent structuring by anisotropic dry etching, for example with CHF ₃ , O ₂ (top layer 25 ) and HBr, Cl ₂ , O ₂ , He (rest ) using a photolithographically generated mask. The mesa structure, for example, has a square cross-section with an edge length of 0.6 µm, which corresponds to the minimum structure size that can be produced in the technology used.

SiO ₂ spacers 26 with a thickness of 50 nm are formed on the flanks of the mesa structure.

By implantation with As, a connection region 27 is formed on the side of the mesa structure in the substrate 21 . The implantation is carried out, for example, at 50 keV with a dose of 5 × 10 ¹² cm ^-2 . On the surface of the connection region 27 , a metal silicide layer 28 is produced by depositing a metal layer of Ti, cobalt and selective silicide formation. The metal silicide layer 28 and the connection region 27 reduce the connection resistance of the drain layer 22 .

Analogously as described in the first exemplary embodiment, the non-conformal deposition of an insulation layer and etching back of the insulation layer takes place, a protective layer 29 being formed on horizontal upper surfaces. Then a conductive layer is deposited and roughly structured so that it covers the mesa structure. A first insulation layer is deposited, planarized and etched back, the height of which approximately coincides with the cover layer. This exposes the upper area of the conductive layer. The conductive layer is structured by selective etching to SiO ₂ and Si ₃ N ₄ , a gate electrode 211 being produced in the process. There is a gap between the cover layer 25 and the first insulating layer 210 , which is filled with an insulation structure 212 made of SiO ₂ . The insulation structure 212 , the first insulating layer 210 and the cover layer 25 are approximately level with one another.

Then the cover layer 25 is removed selectively to SiO ₂ and silicon, for example with H ₃ PO ₄ at 155 ° C. As in the first exemplary embodiment, a first trench is formed. The surface of the source layer 24 is exposed. Si ₃ N ₄ spacers 213 with a width of 30 nm are formed on the flanks of the first trench (see FIG. 11).

Using the Si ₃ N ₄ spacer 213 , the insulation structure 212 and the first insulating layer 210 as a mask, the source layer 24 , the channel layer 23 and the drain layer are formed with the aid of anisotropic dry etching using, for example, HBr, NF ₃ , O ₂ , He 22 structured. A second grave 214 is formed, which extends into the p-doped substrate 21 . An annular layer sequence is formed from the source layer 24 , the channel layer 23 and the drain layer 22 , the width of the ring being predetermined by the width of the Si ₃ N ₄ spacer 213 .

A dielectric spacer 215, for example made of SiO _{2 and} having a width of 100 nm, is subsequently formed on the flanks of the second trench 214 (see FIG. 12). The dielectric spacer 215 covers the surface of the source layer 24 , channel layer 23 , drain layer 22 and the connection region 27 that is exposed on the flanks of the second trench 214 . The remaining free space in the second trench 214 is subsequently filled with a conductive filling 216 made of p-doped polysilicon (see FIG. 13). The conductive filling 216 is in electrical connection with the substrate 21 . The conductive filling 216 is etched back below the edges of the dielectric spacer 215 . A dielectric cover 217, for example made of SiO _{2, is} applied to the conductive filling 216 . The dielectric cover 217 is essentially level with the dielectric spacer 215 . The dielectric cover 217 and the dielectric spacer 215 envelop the conductive filling 216 , so that it is only in electrical connection with the substrate 21 .

By removing the Si ₃ N ₄ spacer 213 selectively to silicon and SiO ₂ , a contact hole to the source layer 24 is opened in a self-aligned manner. Through photolithographic process steps, a contact hole to the gate electrode 211 and a contact hole to the connection region 27 are opened to the side of the annular layer sequence. A gate contact 218 , a source contact 219 and a drain contact 220 are formed by depositing a metal layer, for example made of Ti, TiN, W, and structuring the metal layer (see FIG. 14). Preferably, the contact holes to gate electrode 211 and connection region 27 are opened before the Si ₃ N ₄ spacer 213 is removed in order to avoid problems in removing the photoresist from the narrow contact holes to the source layer 24 .

Claims (10)

1. Vertical MOS transistor,

• 1. a vertical, mesa-shaped layer sequence is arranged on a main surface of a substrate ( 21 ) and has a source layer ( 24 ), a channel layer ( 23 ) and a drain layer ( 22 ),
• 2. in which at least on the surface of the channel layer ( 23 ) a gate dielectric ( 221 ) and a gate electrode ( 211 ) are arranged,
• 3. a dielectric structure ( 215 ) is arranged on the side of the layer sequence opposite the gate electrode ( 211 ), the height of which is at least as large as that of the layer sequence,
• 4. in which the dimension of the layer sequence between the gate dielectric ( 221 ) and the dielectric structure ( 215 ) is chosen so that the MOS transistor is completely depleted.

2. MOS transistor according to claim 1, in which the layer sequence contains layers of silicon, Si _1-x Ge _x with x <1, Si _1-y C _y with y <1 and / or germanium. 3. MOS transistor according to claim 1 or 2, wherein the dimension of the layer sequence between the gate dielectric ( 221 ) and the dielectric structure ( 215 ) is less than or equal to the layer thickness of the channel layer ( 23 ). 4. MOS transistor according to one of claims 1 to 3, wherein a conductive structure ( 216 ) is arranged adjacent to the dielectric structure ( 215 ). 5. Method for producing a MOS transistor,

• 1. in which a mesa structure is formed on a main surface of a substrate ( 11 , 12 , 13 ) which has a drain layer ( 14 ), a channel layer ( 15 ), a source layer ( 16 ) and a cover layer in the vertical sequence of layers ( 17 ) has
• 2. in which a first insulating layer ( 111 ) is deposited in such a way that its layer thickness in layer parts which are arranged parallel to the main surface is greater than in other layer parts,
• 3. in which the surface of the mesa structure is exposed on the side walls of the mesa structure by isotropic etching of the first insulating layer ( 111 ),
• 4. a gate dielectric ( 112 ) is formed at least on the surface of the channel layer ( 15 ),
• 5. in which a conductive layer ( 113 ) is deposited which covers the mesa structure,
• 6. in which a second insulating layer ( 114 ) is formed and planarized,
• 7. the surface of the conductive layer ( 113 ) is partially exposed by etching back the second insulating layer ( 114 ),
• 8. in which the conductive layer ( 113 ) is partially removed, so that between the cover layer ( 17 ) and the second insulating layer ( 14 ) there is a gap which is filled with an insulation structure ( 115 ),
• 9. in which the cover layer ( 17 ) is removed selectively with respect to the second insulating layer ( 114 ), the insulation structure ( 115 ) and the source layer ( 16 ), so that a first trench ( 116 ) is formed above the source layer ( 16 ),
• 10. in which spacers ( 117 ) are formed on the flanks of the first trench ( 116 ),
• 11. in which the source layer ( 16 ), the channel layer ( 15 ) and the drain layer ( 14 ) is selectively structured by anisotropic etching to the second insulation layer ( 114 ), to the insulation structure ( 115 ) and to the spacers ( 117 ), so that a second trench is created ( 118 ),
• 12. in which at least the flanks of the second trench ( 118 ) are covered with a dielectric structure ( 119 ).

6. The method according to claim 5, wherein the drain layer ( 14 ), the channel layer ( 15 ) and the source layer ( 16 ) by epitaxially growing silicon, Si _1-x Ge _x with x <1, Si _1-y C _y is formed with y <1 and / or germanium. 7. The method according to claim 5 or 6,

• 1. in which insulating spacers ( 18 ) are formed on the flanks of the mesa structure before the first insulating layer ( 111 ) is deposited,
• 2. in which a connection region ( 19 ) for the drain layer ( 14 ) is formed by implantation in the main surface of the substrate.

8. The method according to any one of claims 5 to 7, wherein the dielectric structure in the second trench ( 214 ) dielectric spacer ( 215 ) on the flanks of the second trench ( 214 ), a conductive core ( 216 ) which is connected to the substrate ( 21 ) and has a dielectric cover ( 217 ) covering the conductive core ( 216 ). 9. The method according to any one of claims 5 to 7, wherein the dielectric structure ( 119 ) fills the second trench ( 118 ). 10. The method according to claim 8 or 9, in which a contact to the source layer ( 16 ) is opened by selectively removing the spacers ( 117 ) from the flanks of the first trench ( 116 ).